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1. 发明申请

US20080192877A1 PHASE ALIGNMENT MECHANISM FOR MINIMIZING THE IMPACT OF INTEGER-CHANNEL INTERFERENCE IN A PHASE LOCKED LOOP 审中-公开
标题翻译：用于最小化相位锁定环路中整数通道干扰的影响的相位对准机制
公开(公告)号：US20080192877A1
公开(公告)日：2008-08-14
申请号：US12029456
申请日：2008-02-11
申请人： Oren E. Eliezer , Manouchehr Entezari , Robert B. Staszewski , Sumeer Bhatara
发明人： Oren E. Eliezer , Manouchehr Entezari , Robert B. Staszewski , Sumeer Bhatara
IPC分类号： H04L7/00
CPC分类号： H03L7/1806 , H03L2207/50
摘要： A novel and useful apparatus for and method of minimizing the impact of interference on the phase error performance in a phase locked loop (PLL) at integer channels by adjustment of the phase of the interfering signal such that its impact on the reference signal is minimized. Phase control is achieved by use of the digital architecture of the ADPLL and its insensitivity to an arbitrary phase bias introduced between its digitally represented output and reference phase signals. The optimal phase relationship for each integer channel is determined through a calibration procedure in which the phase is swept and the optimal phase is recorded. Before the transmission of a payload on an integer channel, the phase relationship between the output RF signal and the input reference signal is adjusted to the value found to be optimal for that frequency, based on the values previously recorded during the calibration procedure.
摘要翻译：一种新颖有用的装置和方法，其通过调整干扰信号的相位来最小化干扰对整个信道的锁相环（PLL）中的相位误差性能的影响，使得其对参考信号的影响最小化。通过使用ADPLL的数字架构实现相位控制，并且对其数字化表示的输出和参考相位信号之间引入的任意相位偏置不敏感。通过校准程序确定每个整数通道的最佳相位关系，其中扫描相位并记录最佳相位。在整数通道上传输有效负载之前，输出RF信号和输入参考信号之间的相位关系被调整为基于在校准过程中先前记录的值而针对该频率发现的最佳值。

2. 发明申请

US20090325494A1 Transmitter PLL with Bandwidth on Demand 有权
标题翻译：发射器PLL带宽带宽
公开(公告)号：US20090325494A1
公开(公告)日：2009-12-31
申请号：US12412790
申请日：2009-03-27
申请人： Robert Bogdan Staszewski , Khurram Waheed , Sudheer K. Vemulapalli , Manouchehr Entezari , Imran Bashir
发明人： Robert Bogdan Staszewski , Khurram Waheed , Sudheer K. Vemulapalli , Manouchehr Entezari , Imran Bashir
IPC分类号： H04B7/00
CPC分类号： H03L7/085 , H03L7/093 , H03L7/0991 , H03L2207/50 , H04L27/361
摘要： An embodiment of the present invention provides transmitter having a phase locked loop that has a dynamically controllable loop bandwidth. A transmit modulator is coupled to the PLL for performing vector modulation in response to transmission symbols. Each transmission symbol comprises an amplitude signal and a phase signal. A controller is coupled to the PLL and to the transmit modulator and is operable to detect when a criteria of the transmission symbols crosses a threshold and to adjust loop bandwidth in response to crossing the threshold. The criteria of the transmission symbols may be a function of the amplitude signal or a function of the phase signal, and may be the amplitude signal, a first derivative of the amplitude signal, a second derivative of the amplitude signal, a square of the amplitude signal, a derivative of the amplitude signal squared, the phase signal, or a derivative of the phase signal.
摘要翻译：本发明的一个实施例提供具有锁相环的发射机，其具有动态可控的环路带宽。发射调制器耦合到PLL以响应于发射符号执行矢量调制。每个发送符号包括振幅信号和相位信号。控制器耦合到PLL和发射调制器，并且可操作以检测发射符号的标准何时跨越阈值并响应于跨越阈值来调整环路带宽。传输符号的标准可以是振幅信号或相位信号的函数的函数，并且可以是振幅信号，振幅信号的一阶导数，振幅信号的二阶导数，幅度的平方信号，幅度信号平方的导数，相位信号或相位信号的导数。

3. 发明授权

US5886994A Apparatus and method for mapping high density E1 signals into a digital cross-connect matrix space 失效
标题翻译：将高密度E1信号映射成数字交叉连接矩阵空间的装置和方法
公开(公告)号：US5886994A
公开(公告)日：1999-03-23
申请号：US673012
申请日：1996-07-01
申请人： Stephen A. Deschaine , Manouchehr Entezari , Mark J. Nietubyc , Werner L. Heissenhuber
发明人： Stephen A. Deschaine , Manouchehr Entezari , Mark J. Nietubyc , Werner L. Heissenhuber
IPC分类号： H04J3/16 , H04Q11/04 , H04J3/02
CPC分类号： H04Q11/04 , H04J3/1635 , H04Q2213/13076 , H04Q2213/13103 , H04Q2213/13106 , H04Q2213/13166 , H04Q2213/13213 , H04Q2213/13292 , H04Q2213/13299
摘要： Apparatus and method are provided which map E1 signals into a logical space of a predetermined number of DS1 signals. 24 selected DS0 signals that are part of each E1 signal are mapped into the space of one DS1 signal in the logical space. The remaining eight DS0 signals of every three E1 signal are then interleavingly mapped into the space of one DS1 signal in the logical space. Depending on the defined logical space, additional E1 signals are mapped into the logical space in the same manner until the predetermined number of DS1 signal spaces in the defined logical space are filled.
摘要翻译：提供了将E1信号映射到预定数量的DS1信号的逻辑空间中的装置和方法。作为每个E1信号的一部分的24个选择的DS0信号被映射到逻辑空间中的一个DS1信号的空间中。每三个E1信号的剩余八个DS0信号随后交错地映射到逻辑空间中一个DS1信号的空间。根据定义的逻辑空间，附加的E1信号以相同的方式映射到逻辑空间中，直到定义的逻辑空间中的预定数量的DS1信号空间被填满。

4. 发明申请

US20100135368A1 UPSAMPLING/INTERPOLATION AND TIME ALIGNMENT MECHANISM UTILIZING INJECTION OF HIGH FREQUENCY NOISE 审中-公开
标题翻译：使用高频噪声的注射/插入和时间校准机制
公开(公告)号：US20100135368A1
公开(公告)日：2010-06-03
申请号：US12326781
申请日：2008-12-02
申请人： Jaimin A. Mehta , Sameh S. Rezeq , Manouchehr Entezari , Robert B. Staszewski
发明人： Jaimin A. Mehta , Sameh S. Rezeq , Manouchehr Entezari , Robert B. Staszewski
IPC分类号： H04B1/38 , G06F17/17 , H04L25/03
CPC分类号： H04L27/38 , H03H17/0671 , H04L27/3863 , H04L27/3872 , H04L27/3881 , H04L27/389
摘要： A novel and useful apparatus for and method of upsampling/interpolating a discrete-time input sample stream with time alignment utilizing the addition of randomized high frequency noise. The upsampling mechanism is an effective implementation of a second order interpolator that eliminates the need for a conventional filter as the filtering action is effectively built into the mechanism. The upsampling mechanism takes the derivative of the discrete-time input sample stream, thereby effectively providing another order of interpolation over a conventional interpolator. Before outputting the interpolated signal, an integrator takes the integral of the interpolated samples. Any processing performed between the derivative and integrator blocks effectively provides an additional order of interpolation. High frequency noise (i.e. dithering) is added to the differentiated samples in order to eliminate the spectral regrowth spurs that would otherwise appear in the output after rounding. Delay alignment is performed on the differentiated samples in order to time align both phase/frequency and amplitude samples that are processed on different paths.
摘要翻译：一种新颖有用的装置和方法，其利用随机化的高频噪声的添加，利用时间对准对离散时间输入样本流进行上采样/内插。上采样机制是二阶插值器的有效实现，其消除了对传统滤波器的需要，因为滤波动作被有效地内置到机构中。上采样机制采用离散时间输入采样流的导数，从而有效地为常规内插器提供了另一个内插次序。在输出内插信号之前，积分器取内插样本的积分。在导数和积分器块之间执行的任何处理有效地提供了一个额外的内插次序。将高频噪声（即抖动）加到差分采样中，以消除在舍入后将出现在输出中的频谱再生马刺。对差分样本执行延迟对齐，以便对在不同路径上处理的相位/频率和振幅样本进行时间对齐。

5. 发明授权

US5883898A Apparatus and method for mapping E1 signals into a digital cross-connect matrix space 失效
标题翻译：将E1信号映射到数字交叉连接矩阵空间中的装置和方法
公开(公告)号：US5883898A
公开(公告)日：1999-03-16
申请号：US673102
申请日：1996-07-01
申请人： Stephen A. Deschaine , Manouchehr Entezari , Mark J. Nietubyc , Werner L. Heissenhuber
发明人： Stephen A. Deschaine , Manouchehr Entezari , Mark J. Nietubyc , Werner L. Heissenhuber
IPC分类号： H04J3/16 , H04Q11/04 , H04J3/02
CPC分类号： H04Q11/04 , H04J3/1635
摘要： Apparatus and method are provided which map E1 signals into a logical space of a predetermined number of DS1 signals. 24 selected DS0 signals that are part of the first E1 signal are mapped into the space of a first DS1 signal in the logical space. The 8 DS0 signals of the first E1 signal are then mapped into the space of a second DS1 signal in the logical space. Depending on the defined logical space, additional E1 signals may be mapped into the logical space of two DS1 signals in the same manner until the predetermined number of DS1 signal spaces in the defined logical space are filled.
摘要翻译：提供了将E1信号映射到预定数量的DS1信号的逻辑空间中的装置和方法。作为第一E1信号的一部分的24个选择的DS0信号被映射到逻辑空间中的第一DS1信号的空间中。然后，第一E1信号的8个DS0信号被映射到逻辑空间中的第二DS1信号的空间中。根据定义的逻辑空间，附加的E1信号可以以相同的方式映射到两个DS1信号的逻辑空间，直到在定义的逻辑空间中的预定数量的DS1信号空间被填充。

6. 发明授权

US08126401B2 Transmitter PLL with bandwidth on demand 有权
标题翻译：发射器PLL，带宽需求
公开(公告)号：US08126401B2
公开(公告)日：2012-02-28
申请号：US12412790
申请日：2009-03-27
申请人： Robert Bogdan Staszewski , Khurram Waheed , Sudheer K. Vemulapalli , Manouchehr Entezari , Imran Bashir
发明人： Robert Bogdan Staszewski , Khurram Waheed , Sudheer K. Vemulapalli , Manouchehr Entezari , Imran Bashir
IPC分类号： H04B1/00
CPC分类号： H03L7/085 , H03L7/093 , H03L7/0991 , H03L2207/50 , H04L27/361
摘要： An embodiment of the present invention provides transmitter having a phase locked loop that has a dynamically controllable loop bandwidth. A transmit modulator is coupled to the PLL for performing vector modulation in response to transmission symbols. Each transmission symbol comprises an amplitude signal and a phase signal. A controller is coupled to the PLL and to the transmit modulator and is operable to detect when a criteria of the transmission symbols crosses a threshold and to adjust loop bandwidth in response to crossing the threshold. The criteria of the transmission symbols may be a function of the amplitude signal or a function of the phase signal, and may be the amplitude signal, a first derivative of the amplitude signal, a second derivative of the amplitude signal, a square of the amplitude signal, a derivative of the amplitude signal squared, the phase signal, or a derivative of the phase signal.
摘要翻译：本发明的一个实施例提供具有锁相环的发射机，其具有动态可控的环路带宽。发射调制器耦合到PLL以响应于发射符号执行矢量调制。每个发送符号包括振幅信号和相位信号。控制器耦合到PLL和发射调制器，并且可操作以检测发射符号的标准何时跨越阈值并响应于跨越阈值来调整环路带宽。传输符号的标准可以是振幅信号或相位信号的函数的函数，并且可以是振幅信号，振幅信号的一阶导数，振幅信号的二阶导数，幅度的平方信号，幅度信号平方的导数，相位信号或相位信号的导数。

7. 发明授权

US5926480A Digital cross-connect system to digital loop carrier interface unit 失效
标题翻译：数字交叉连接系统到数字环路载波接口单元
公开(公告)号：US5926480A
公开(公告)日：1999-07-20
申请号：US673118
申请日：1996-07-01
申请人： Stephen A. Deschaine , Clemente G. Garcia , Edward P. Traupman , Manouchehr Entezari , Mark J. Nietubyc , Werner L. Heissenhuber
发明人： Stephen A. Deschaine , Clemente G. Garcia , Edward P. Traupman , Manouchehr Entezari , Mark J. Nietubyc , Werner L. Heissenhuber
IPC分类号： H04J3/06 , H04J3/16 , H04Q11/04 , H04J3/02
CPC分类号： H04Q11/04 , H04J3/0685 , H04J3/1635 , H04Q2213/13076 , H04Q2213/13103 , H04Q2213/13106 , H04Q2213/13166 , H04Q2213/13213 , H04Q2213/13292 , H04Q2213/13299 , H04Q2213/1336 , H04Q2213/13381
摘要： An interface unit (12) for interfacing a digital loop carrier (16) to a digital cross-connect (14) comprises a control interface (22) coupled between the digital cross-connect (14) and digital loop carrier (16) for conversion and communication of control messages therebetween. A timing interface (32) is further coupled between the digital cross-connect (14) and digital loop carrier (16) for generally synchronizing the operations thereof. Further, a matrix interface (30) is coupled between the digital cross-connect (14) and digital loop carrier (16) for converting data rates and formats of data in the digital cross-connect (14) and digital loop carrier (16), so that network signals received by the digital loop carrier (16) are converted from a first format to a second format and communicated by the matrix interface (30) to the digital cross-connect (14) for cross-connection, and cross-connected data are converted from the second format to the first format and communicated to the digital loop carrier (16).
摘要翻译：用于将数字环路载波（16）与数字交叉连接（14）接口的接口单元（12）包括耦合在数字交叉连接（14）和数字环路载波（16）之间用于转换的控制接口（22）以及其间的控制消息的通信。定时接口（32）还被耦合在数字交叉连接（14）和数字环路载体（16）之间，以使其操作大致同步。此外，矩阵接口（30）耦合在数字交叉连接（14）和数字环路载体（16）之间，用于转换数字交叉连接（14）和数字环路载体（16）中的数据速率和数据格式，，使得由数字环路载波（16）接收的网络信号从第一格式转换为第二格式，并由矩阵接口（30）传送到数字交叉连接（14）进行交叉连接，连接的数据从第二格式转换为第一格式并传送到数字环路载体（16）。

8. 发明授权

US5875191A Apparatus and method for mapping telecommunications signals onto a subscriber bus 失效
标题翻译：将电信信号映射到用户总线上的装置和方法
公开(公告)号：US5875191A
公开(公告)日：1999-02-23
申请号：US768316
申请日：1996-12-17
申请人： Stephen A. Deschaine , Manouchehr Entezari , Rudolph B. Klecka, III
发明人： Stephen A. Deschaine , Manouchehr Entezari , Rudolph B. Klecka, III
IPC分类号： H04J3/16 , H04Q11/04 , H04J3/02
CPC分类号： H04Q11/04 , H04J3/1635 , H04J3/1641 , H04Q2213/13003 , H04Q2213/13031 , H04Q2213/1309 , H04Q2213/13098 , H04Q2213/13166 , H04Q2213/13174 , H04Q2213/13176 , H04Q2213/13216 , H04Q2213/13291 , H04Q2213/13292 , H04Q2213/13299 , H04Q2213/13381
摘要： Two T1 signals are mapped onto a subscriber bus (26) in a subscriber loop equipment (10) for transport between a bank control unit (20) and channel units (22), for example. The data channels and the signaling and control channels of the first T1 signal are mapped onto a first data stream, and the data channels and the signaling and control channels of the second T1 signal are mapped onto a second data stream. The data streams are bit-interleaved for transport on the subscriber bus (26).
摘要翻译：例如，两个T1信号被映射到用户环路设备（10）中的用户总线（26）上，用于在存储体控制单元（20）和通道单元（22）之间传输。数据信道和第一T1信号的信令和控制信道被映射到第一数据流，并且第二T1信号的数据信道和信令和控制信道被映射到第二数据流。数据流被比特交织以用于在用户总线（26）上传输。

9. 发明授权

US5809029A Apparatus and method for mapping telecommunications signals onto a subscriber bus 失效
标题翻译：将电信信号映射到用户总线上的装置和方法
公开(公告)号：US5809029A
公开(公告)日：1998-09-15
申请号：US767689
申请日：1996-12-17
申请人： Stephen A. Deschaine , Manouchehr Entezari , Rudolph B. Klecka, III
发明人： Stephen A. Deschaine , Manouchehr Entezari , Rudolph B. Klecka, III
IPC分类号： H04J3/16 , H04Q11/04
CPC分类号： H04J3/1635 , H04J3/1641 , H04Q11/04 , H04Q11/0478 , H04J2203/0044 , H04J2203/0048 , H04J2203/0089 , H04Q2213/1309 , H04Q2213/13098 , H04Q2213/13176 , H04Q2213/13216 , H04Q2213/13292 , H04Q2213/13299 , H04Q2213/13381
摘要： In a subscriber loop equipment (10) having a subscriber bus (26), there is provided an odd data stream carrying a first set of data time slots of an E1 signal and a first set of signaling and control time slots of the E1 signal, and an even data stream carrying a second set of data time slots of the E1 signal and a second set of signaling and control time slots of the E1 signal. The odd and even data streams are bit-interleaved and transported on the subscriber bus (26).
摘要翻译：在具有用户总线（26）的用户环路设备（10）中，提供携带E1信号的第一组数据时隙和E1信号的第一组信令和控制时隙的奇数数据流，以及携带E1信号的第二组数据时隙和E1信号的第二组信令和控制时隙的偶数数据流。奇数和偶数数据流在用户总线（26）上进行位交织和传输。

10. 发明申请

US20120244824A1 MINIMIZATION OF RMS PHASE ERROR IN A PHASE LOCKED LOOP BY DITHERING OF A FREQUENCY REFERENCE 审中-公开
标题翻译：通过频率参考的最小化在相位锁定环路中的RMS相位误差
公开(公告)号：US20120244824A1
公开(公告)日：2012-09-27
申请号：US11832292
申请日：2007-08-01
申请人： Manouchehr Entezari , Robert B. Staszewski , Thomas Almholt , Oren E. Eliezer
发明人： Manouchehr Entezari , Robert B. Staszewski , Thomas Almholt , Oren E. Eliezer
IPC分类号： H04B15/00 , H04B1/04
CPC分类号： H03L7/1806 , H03L2207/50
摘要： A novel and useful apparatus for and method of minimizing the phase distortions experienced at the output of a phase locked loop (PLL) by dithering of its input frequency reference to overcome additive interference that is parasitically suffered on it. The frequency reference signal is dithered in a controlled manner using either indirect or direct coupling. The dither signal may be a single clock or is generated by switching between two or more of the existing clock signals generated, or may be produced by a dedicated pseudo-random noise generator having specific spectral properties. In indirect coupling, the dither signal is coupled through a bond wire sufficiently close in proximity to the frequency reference circuit input. This dominates the jitter inflicted onto the frequency reference signal and upconverts its spectral content to higher frequency, thus eliminating the more damaging low-frequency jitter caused by the interfering RF signal. In direct coupling, the dither signal is coupled to the reference frequency input using a network of components directly connected thereto.
摘要翻译：一种用于通过抖动其输入频率参考来最小化在锁相环（PLL）的输出处经历的相位失真的新颖且有用的装置，以克服寄生在其上的附加干扰。频率参考信号以受控的方式使用间接或直接耦合进行抖动。抖动信号可以是单个时钟，或者是通过在所生成的两个或更多个现有时钟信号之间进行切换来产生，或者可以由具有特定频谱特性的专用伪随机噪声发生器产生。在间接耦合中，抖动信号通过在频率参考电路输入附近足够接近的接合线耦合。这支配着对频率参考信号造成的抖动，并将其频谱内容上变频到更高的频率，从而消除了由干扰RF信号引起的更有害的低频抖动。在直接耦合中，抖动信号使用直接与其连接的部件的网络耦合到参考频率输入。

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