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1. 发明授权

US08421077B2 Replacement gate MOSFET with self-aligned diffusion contact 有权
标题翻译：具有自对准扩散接触的替代栅极MOSFET
公开(公告)号：US08421077B2
公开(公告)日：2013-04-16
申请号：US12795973
申请日：2010-06-08
申请人： Sameer H. Jain , Carl J. Radens , Shahab Siddiqui , Jay W. Strane
发明人： Sameer H. Jain , Carl J. Radens , Shahab Siddiqui , Jay W. Strane
IPC分类号： H01L29/10
CPC分类号： H01L29/7833 , H01L21/76834 , H01L21/76897 , H01L29/4966 , H01L29/517 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6659
摘要： A replacement gate field effect transistor includes at least one self-aligned contact that overlies a portion of a dielectric gate cap. A replacement gate stack is formed in a cavity formed by removal of a disposable gate stack. The replacement gate stack is subsequently recessed, and a dielectric gate cap having sidewalls that are vertically coincident with outer sidewalls of the gate spacer is formed by filling the recess over the replacement gate stack. An anisotropic etch removes the dielectric material of the planarization layer selective to the material of the dielectric gate cap, thereby forming at least one via cavity having sidewalls that coincide with a portion of the sidewalls of the gate spacer. A portion of each diffusion contact formed by filling the at least one via cavity overlies a portion of the gate spacer and protrudes into the dielectric gate cap.
摘要翻译：替代栅极场效应晶体管包括至少一个自对准接触，其覆盖在电介质栅极盖的一部分上。在通过去除一次性栅极堆叠而形成的空腔中形成替换栅极堆叠。替换栅极堆叠随后被凹入，并且具有与栅极间隔物的外侧壁垂直重合的侧壁的电介质栅极盖通过在该替代栅极叠层上填充该凹槽来形成。各向异性蚀刻去除对介电栅极盖的材料有选择性的平坦化层的电介质材料，从而形成具有与栅极间隔物的侧壁的一部分重合的侧壁的至少一个通孔。通过填充至少一个通孔形成的每个扩散接触部分覆盖在栅极间隔物的一部分上并且突出到电介质栅极帽中。

2. 发明申请

US20110298017A1 REPLACEMENT GATE MOSFET WITH SELF-ALIGNED DIFFUSION CONTACT 有权
标题翻译：具有自对准扩散接触的更换栅极MOSFET
公开(公告)号：US20110298017A1
公开(公告)日：2011-12-08
申请号：US12795973
申请日：2010-06-08
申请人： Sameer H. Jain , Carl J. Radens , Shahab Siddiqui , Jay W. Strane
发明人： Sameer H. Jain , Carl J. Radens , Shahab Siddiqui , Jay W. Strane
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L29/7833 , H01L21/76834 , H01L21/76897 , H01L29/4966 , H01L29/517 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6659
摘要： A replacement gate field effect transistor includes at least one self-aligned contact that overlies a portion of a dielectric gate cap. A replacement gate stack is formed in a cavity formed by removal of a disposable gate stack. The replacement gate stack is subsequently recessed, and a dielectric gate cap having sidewalls that are vertically coincident with outer sidewalls of the gate spacer is formed by filling the recess over the replacement gate stack. An anisotropic etch removes the dielectric material of the planarization layer selective to the material of the dielectric gate cap, thereby forming at least one via cavity having sidewalls that coincide with a portion of the sidewalls of the gate spacer. A portion of each diffusion contact formed by filling the at least one via cavity overlies a portion of the gate spacer and protrudes into the dielectric gate cap.
摘要翻译：替代栅极场效应晶体管包括至少一个自对准接触，其覆盖在电介质栅极盖的一部分上。在通过去除一次性栅极堆叠而形成的空腔中形成替换栅极堆叠。替换栅极堆叠随后被凹入，并且具有与栅极间隔物的外侧壁垂直重合的侧壁的电介质栅极盖通过在该替代栅极叠层上填充该凹槽来形成。各向异性蚀刻去除对介电栅极盖的材料有选择性的平坦化层的电介质材料，从而形成具有与栅极间隔物的侧壁的一部分重合的侧壁的至少一个通孔。通过填充至少一个通孔形成的每个扩散接触部分覆盖在栅极间隔物的一部分上并且突出到电介质栅极帽中。

3. 发明授权

US08642424B2 Replacement metal gate structure and methods of manufacture 有权
标题翻译：替代金属门结构及其制造方法
公开(公告)号：US08642424B2
公开(公告)日：2014-02-04
申请号：US13180842
申请日：2011-07-12
申请人： Sameer H. Jain , Jeffrey B. Johnson , Ying Li , Hasan M. Nayfeh , Ravikumar Ramachandran
发明人： Sameer H. Jain , Jeffrey B. Johnson , Ying Li , Hasan M. Nayfeh , Ravikumar Ramachandran
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L21/28088 , H01L21/28167 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L21/823864 , H01L29/165 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/6659 , H01L29/66636 , H01L29/7843
摘要： A replacement metal gate structure and methods of manufacturing the same is provided. The method includes forming at least one trench structure and forming a liner of high-k dielectric material in the at least one trench structure. The method further includes adjusting a height of the liner of high-k dielectric material. The method further includes forming at least one workfunction metal over the liner, and forming a metal gate structure in the at least one trench structure, over the at least one workfunction metal and the liner of high-k dielectric material.
摘要翻译：提供替代的金属栅极结构及其制造方法。所述方法包括形成至少一个沟槽结构并在所述至少一个沟槽结构中形成高k电介质材料的衬垫。该方法还包括调整高k电介质材料的衬垫的高度。所述方法还包括在所述衬垫上形成至少一个功函数金属，以及在所述至少一个功函数金属和所述高k电介质材料的衬垫上，在所述至少一个沟槽结构中形成金属栅极结构。

4. 发明授权

US07538339B2 Scalable strained FET device and method of fabricating the same 有权
标题翻译：可扩展应变FET器件及其制造方法
公开(公告)号：US07538339B2
公开(公告)日：2009-05-26
申请号：US11615153
申请日：2006-12-22
申请人： Brian J. Greene , Sameer H. Jain , William K. Henson
发明人： Brian J. Greene , Sameer H. Jain , William K. Henson
IPC分类号： H01L29/94
CPC分类号： H01L29/7843 , H01L21/31641 , H01L21/31645 , H01L21/3185 , H01L21/823807 , H01L21/823828
摘要： An integrated circuit including pairs of strained complementary CMOS field-effect devices consisting of n-FET and p-FET transistors on a substrate. The n-FET is provided with a compressive dielectric stressor, while the p-FET is provided with a tensile stressed dielectric. Each dielectric stressor includes a discrete horizontal segment on a surface overlying and contacting the gate of the respective FET. The stress enhancement is insensitive to PC pitch, and by reducing the height of the polysilicon stack, the scalability which is achieved contributes to a performance improvement. The n-FET leverages higher stress values that are obtainable in the compressive liners are greater than 3 GPa compared to less than 1.5 GPa for tensile liners.
摘要翻译：一种集成电路，包括在衬底上由n-FET和p-FET晶体管组成的应变互补CMOS场效应器件对。 n-FET设置有压缩介电应力源，而p-FET设置有拉伸应力电介质。每个介电应力器包括覆盖并接触相应FET的栅极的表面上的离散水平段。应力增强对PC间距不敏感，并且通过降低多晶硅堆叠的高度，实现的可扩展性有助于性能改进。 n-FET利用在压缩衬里中可获得的较高应力值大于3GPa，而拉伸衬垫的应力值小于1.5GPa。

5. 发明申请

US20080150033A1 SCALABLE STRAINED FET DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：可扩展应变FET器件及其制造方法
公开(公告)号：US20080150033A1
公开(公告)日：2008-06-26
申请号：US11615153
申请日：2006-12-22
申请人： Brian J. Greene , Sameer H. Jain , William K. Henson
发明人： Brian J. Greene , Sameer H. Jain , William K. Henson
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L29/7843 , H01L21/31641 , H01L21/31645 , H01L21/3185 , H01L21/823807 , H01L21/823828
摘要： A CMOS FET device having an enhanced performance is described by taking advantage of known dual-stress-liner effects and by making use of compressive nitride in an appropriate geometric configuration to induce compressive stress in the n-FET channel, and a tensile stress in the p-FET. The stress enhancement is designed to be insensitive to PC pitch, and to increase by reducing the height of the polysilicon stack, such that scalability contributes to the stated performance improvement. The n-FET leverages higher stress values that are obtainable in the compressive liners to be greater than 3 GPa, compared to less than 1.5 GPa for tensile liners.
摘要翻译：通过利用已知的双重应力衬垫效应并且通过利用适当几何构型的压缩氮化物来诱导n-FET通道中的压应力来描述具有增强性能的CMOS FET器件，并且在 p-FET。应力增强被设计为对PC间距不敏感，并且通过降低多晶硅堆叠的高度来增加，使得可扩展性有助于所述的性能改进。 n-FET利用在压缩衬里中可获得的较高应力值大于3GPa，而拉伸衬垫的应力值小于1.5GPa。

6. 发明申请

US20090166770A1 METHOD OF FABRICATING GATE ELECTRODE FOR GATE OF MOSFET AND STRUCTURE THEREOF 审中-公开
标题翻译：制造MOSFET栅极电极的方法及其结构
公开(公告)号：US20090166770A1
公开(公告)日：2009-07-02
申请号：US11968396
申请日：2008-01-02
申请人： Oleg Gluschenkov , Sameer H. Jain , Yaocheng Liu
发明人： Oleg Gluschenkov , Sameer H. Jain , Yaocheng Liu
IPC分类号： H01L29/423 , H01L21/28
CPC分类号： H01L29/4983 , H01L21/268 , H01L21/2686 , H01L21/2807 , H01L21/823828 , H01L21/823842
摘要： A method of fabricating a gate electrode for a gate of a metal oxide semiconductor field effect transistor (MOSFET), where the transistor has a structure incorporating a gate disposed on a substrate. The substrate comprises a source-drain region. The gate includes a gate electrode disposed on a gate dielectric and surrounded by a spacer. The gate electrode includes a capping layer of polysilicon (poly-Si) and a thin polycrystalline intermixed silicon-germanium (SiGe) layer superposed on the gate dielectric. The thin polycrystalline intermixed silicon-germanium (SiGe) layer may be formed by a high-temperature ultrafast melt-crystalization annealing process. The melt-crystallization process of the intermixed silicon-germanium provides an active dopant concentration that reduces the width of a depletion region formed at an interface of the polycrystalline intermixed silicon-germanium (SiGe) layer and the gate dielectric.
摘要翻译：一种制造用于金属氧化物半导体场效应晶体管（MOSFET）的栅极的栅极的方法，其中晶体管具有结合设置在衬底上的栅极的结构。衬底包括源极 - 漏极区域。栅极包括设置在栅极电介质上并被间隔物包围的栅电极。栅电极包括多晶硅（poly-Si）的覆盖层和叠加在栅极电介质上的薄的多晶混合的硅 - 锗（SiGe）层。薄多晶混合硅锗（SiGe）层可以通过高温超快熔融结晶退火工艺形成。混合硅 - 锗的熔融结晶过程提供了活性掺杂剂浓度，其减小了在多晶混合硅 - 锗（SiGe）层和栅极电介质的界面处形成的耗尽区的宽度。

7. 发明申请

US20090146223A1 PROCESS AND METHOD TO LOWER CONTACT RESISTANCE 审中-公开
标题翻译：降低接触电阻的方法和方法
公开(公告)号：US20090146223A1
公开(公告)日：2009-06-11
申请号：US11950574
申请日：2007-12-05
申请人： Sameer H. Jain , Shreesh Narasimha , Karen A. Nummy , Katsunori Onishi , Viorel C. Ontalus , Jang H. Sim
发明人： Sameer H. Jain , Shreesh Narasimha , Karen A. Nummy , Katsunori Onishi , Viorel C. Ontalus , Jang H. Sim
IPC分类号： H01L29/94 , H01L21/8236
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/268 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/7833 , H01L29/808 , H01L29/812
摘要： A method removes the spacers from the sides of a transistor gate stack, and after the spacers are removed, the method implants an additional impurity into surface regions of the substrate not protected by the gate conductor (or alternatively just amorphizes these surface regions, without adding more impurity). The method then performs a laser anneal on the additional impurity (to activate the additional impurity) or amorphized regions (to recrystallize the amorphized regions). After this, permanent spacers are formed on the sidewalls of the gate conductor. Then, the surface regions of the substrate not protected by the gate conductor and the permanent spacers are silicided, to create silicide source/drain regions. This forms the silicide regions in the additional impurity or in the recrystallized amorphized regions to reduce the source/drain resistance by improving the active dopant concentration at the silicon-silicide interface.
摘要翻译：一种方法从晶体管栅极堆叠的侧面去除间隔物，并且在间隔物被去除之后，该方法将不附加栅极导体保护的衬底的另外的杂质注入到衬底的表面区域中（或者只是将这些表面区域非晶化，而不添加更多的杂质）。然后，该方法对另外的杂质（以激活附加杂质）或非晶化区域（使非晶化区域重结晶）进行激光退火。之后，在栅极导体的侧壁上形成永久的间隔物。然后，将不被栅极导体和永久性间隔物保护的衬底的表面区域硅化，以产生硅化物源极/漏极区域。这会在附加杂质或再结晶非晶化区域中形成硅化物区域，以通过改善硅硅化物界面处的活性掺杂剂浓度来降低源/漏电阻。

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