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1. 发明授权

US08555124B2 Apparatus and method for detecting an approaching error condition 有权
标题翻译：用于检测接近错误状况的装置和方法
公开(公告)号：US08555124B2
公开(公告)日：2013-10-08
申请号：US12801402
申请日：2010-06-07
申请人： Sachin Satish Idgunji , Shidhartha Das , David Michael Bull , Robert Campbell Aitken
发明人： Sachin Satish Idgunji , Shidhartha Das , David Michael Bull , Robert Campbell Aitken
IPC分类号： G01R31/28
CPC分类号： G01R31/3016
摘要： An apparatus and method are provided for detecting an approaching error condition within a data processing apparatus and includes a sequential storage structure arranged to latch an output signal generated by combinatorial circuitry dependent on a second clock signal. The sequential storage structure has a main storage element to latch a value of the output signal for provision to subsequent combinatorial circuitry. The sequential storage structure can be operated in either first or second modes of operation where, in the first mode, the predetermined timing window is ahead of a time at which the main storage element latches said value of the output signal enabling an approaching setup timing error to be detected. In the second mode, the predetermined timing window is after the time at which the main storage element latches said value of the output signal where an approaching hold timing error is detected.
摘要翻译：提供了一种用于检测数据处理装置内接近的错误状况的装置和方法，并且包括顺序存储结构，其被布置为根据第二时钟信号锁存由组合电路产生的输出信号。顺序存储结构具有主存储元件以锁存输出信号的值以供给后续的组合电路。顺序存储结构可以在第一或第二操作模式中操作，其中在第一模式中，预定定时窗口在主存储元件锁存输出信号的所述值以使得能够接近建立定时误差的时间之前被检测。在第二模式中，预定定时窗口在主存储元件锁存检测到接近保持定时误差的输出信号的值之后。

2. 发明授权

US07605644B2 Integrated circuit power-on control and programmable comparator 有权
标题翻译：集成电路开机控制和可编程比较器
公开(公告)号：US07605644B2
公开(公告)日：2009-10-20
申请号：US11797498
申请日：2007-05-03
申请人： Sachin Satish Idgunji , David Walter Flynn , David William Howard , Robert Campbell Aitken
发明人： Sachin Satish Idgunji , David Walter Flynn , David William Howard , Robert Campbell Aitken
IPC分类号： G05F1/10
CPC分类号： H03K19/0016
摘要： An integrated circuit is provided with a main supply rail and a virtual supply rail connected by strong and weak header transistors. A power-on controller controls the switching on of the strong transistors after the virtual supply rail voltage has already been driven up to close to its operating level by the weak transistor. The power-on controller comprises a comparator monitoring a single reference voltage level with its output being latched within a latch and used to switch on the strong transistor. The comparator may be programmable to detect multiple different trigger voltage levels by using opposing charging and discharging transistors with one set of these operating in a saturated regime and the other in a regime in which the current therethrough varies in dependence upon the voltage being sensed. These opposing transistors can be used to charge or discharge a node with the state of that node being taken to generate the sensed output.
摘要翻译：集成电路设置有主供电轨和通过强和弱标头晶体管连接的虚拟电源轨。在虚拟电源电压已经被弱晶体管驱动到接近其工作电平之后，上电控制器控制强晶体管的导通。上电控制器包括监视单个参考电压电平的比较器，其输出被锁存在锁存器内并用于接通强晶体管。比较器可以被编程为通过使用相反的充电和放电晶体管来检测多个不同的触发电压电平，其中一组在饱和状态下工作，另一组在其中电流根据感测电压而变化。这些相对的晶体管可以用于对具有该节点的状态的节点进行充电或放电以产生感测的输出。

3. 发明申请

US20080272809A1 Integrated circuit power-on control and programmable comparator 有权
标题翻译：集成电路开机控制和可编程比较器
公开(公告)号：US20080272809A1
公开(公告)日：2008-11-06
申请号：US11797498
申请日：2007-05-03
申请人： Sachin Satish Idgunji , David Walter Flynn , David William Howard , Robert Campbell Aitken
发明人： Sachin Satish Idgunji , David Walter Flynn , David William Howard , Robert Campbell Aitken
IPC分类号： H03K5/24
CPC分类号： H03K19/0016
摘要： An integrated circuit is provided with a main supply rail and a virtual supply rail connected by strong and weak header transistors. A power-on controller controls the switching on of the strong transistors after the virtual supply rail voltage has already been driven up to close to its operating level by the weak transistor. The power-on controller comprises a comparator monitoring a single reference voltage level with its output being latched within a latch and used to switch on the strong transistor. The comparator may be programmable to detect multiple different trigger voltage levels by using opposing charging and discharging transistors with one set of these operating in a saturated regime and the other in a regime in which the current therethrough varies in dependence upon the voltage being sensed. These opposing transistors can be used to charge or discharge a node with the state of that node being taken to generate the sensed output.
摘要翻译：集成电路设置有主供电轨和通过强和弱标头晶体管连接的虚拟电源轨。在虚拟电源电压已经被弱晶体管驱动到接近其工作电平之后，上电控制器控制强晶体管的导通。上电控制器包括监视单个参考电压电平的比较器，其输出被锁存在锁存器内并用于接通强晶体管。比较器可以被编程为通过使用相反的充电和放电晶体管来检测多个不同的触发电压电平，其中一组在饱和状态下工作，另一组在其中电流根据感测电压而变化。这些相对的晶体管可以用于对具有该节点的状态的节点进行充电或放电以产生感测的输出。

4. 发明申请

US20080272652A1 Virtual power rail modulation within an integrated circuit 有权
标题翻译：集成电路内的虚拟电源轨调制
公开(公告)号：US20080272652A1
公开(公告)日：2008-11-06
申请号：US11797497
申请日：2007-05-03
申请人： Sachin Satish Idgunji , David Walter Flynn , Robert Campbell Aitken
发明人： Sachin Satish Idgunji , David Walter Flynn , Robert Campbell Aitken
IPC分类号： H02J1/00
CPC分类号： H03K19/0016 , H03K19/096 , Y10T307/461
摘要： An integrated circuit 2 is provided with logic blocks 16 which draw their power from virtual supply rails 8, 10. These virtual supply rails 8, 10 are connected by switch blocks 12, 14 to main supply rails 4, 6. The switch blocks 12, 14 are subject to modulation to maintain the virtual supply rails 8, 10 at an intermediate voltage level such that a reduced voltage difference is applied across the logic block 16. This intermediate voltage level is used in a state retention mode in which the clock signal clk to the logic block 16 is stopped and state signal values are maintained therein using this reduced virtual power rail derived voltage difference. When it is desired to resume processing then the full virtual rail voltages are restored by rendering the switch blocks 12, 14 fully conductive and then the clock is restarted. The switch blocks 12, 14 which are modulated by controllers 18 which use feedback control based upon the sensed virtual rail voltages (VVdd and VVgnd) while drawing their own power from the normal supply rails (VVdd and gnd).
摘要翻译：集成电路2设置有从虚拟电源轨8,10吸取电力的逻辑块16.这些虚拟电源轨8,10由开关块12,14连接到主电源轨4,6。 14进行调制以将虚拟电源轨8,10保持在中间电压电平，使得在逻辑块16上施加减小的电压差。该中间电压电平用于状态保持模式，其中时钟信号clk 停止逻辑块16，并且使用该减小的虚拟功率轨导出电压差来维持状态信号值。当希望恢复处理时，通过使开关块12,14完全导通然后再启动时钟来恢复完整的虚拟轨电压。开关块12,14由控制器18调制，控制器18使用基于感测的虚拟轨电压（VV）和反馈控制电压（VV）的反馈控制，同时从正常的电源轨（VV＆lt; dd＆gt;和＆lt; SUB＆gt;＆gt;）。

5. 发明授权

US08717078B2 Sequential latching device with elements to increase hold times on the diagnostic data path 有权
标题翻译：具有元件的顺序锁定装置，以增加诊断数据路径上的保持时间
公开(公告)号：US08717078B2
公开(公告)日：2014-05-06
申请号：US13495362
申请日：2012-06-13
申请人： Sachin Satish Idgunji , Robert Campbell Aitken , Imran Iqbal
发明人： Sachin Satish Idgunji , Robert Campbell Aitken , Imran Iqbal
IPC分类号： H03K3/289
CPC分类号： H03K3/0375
摘要： A latching device includes input and output latching elements to receive and output data values wherein the input and output elements are configured to receive a first and second clocks, respectively. The clocks have the same frequency but are inverted. The elements are transparent and transmit data between an input and an output in response to the first value of a received clock and are opaque and hold the data value in response to a second value of the received clock, such that in response to the first and second clocks the input data value is clocked through the input and output elements to the output. The device includes a device for selecting an operational data value or a diagnostic data value for input to the input element in response to a value of a diagnostic enable signal indicating a functional mode or a diagnostic mode.
摘要翻译：锁存装置包括用于接收和输出数据值的输入和输出锁存元件，其中输入和输出元件分别被配置为接收第一和第二时钟。时钟频率相同但反相。这些元件是透明的，并且响应于接收时钟的第一值在输入和输出之间传输数据，并且是不透明的，并且响应于所接收的时钟的第二值保持数据值，使得响应于第一和第二个时钟，输入数据值通过输入和输出元件输出到输出。该装置包括用于响应于指示功能模式或诊断模式的诊断使能信号的值来选择用于输入到输入元件的操作数据值或诊断数据值的装置。

6. 发明授权

US08103990B2 Characterising circuit cell performance variability in response to perturbations in manufacturing process parameters 有权
标题翻译：表征响应于制造工艺参数中扰动的电路单元性能变化
公开(公告)号：US08103990B2
公开(公告)日：2012-01-24
申请号：US12073050
申请日：2008-02-28
申请人： Sachin Satish Idgunji , Robert Campbell Aitken
发明人： Sachin Satish Idgunji , Robert Campbell Aitken
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/12 , G06F2217/66 , Y02P90/265
摘要： A technique for characterising variation in a performance parameter(s) of circuit cells within a circuit cell library with perturbations in manufacturing process parameters uses a statistical approach whereby the statistical distribution of performance parameter(s) resulting from a joint distribution across manufacturing process parameter space is determined. The perturbation in manufacturing process parameter which results in a characteristic amount of variation is then identified and common sets of such perturbations used to group families of circuit cells together. Families of circuit cells have a correlation in their response to manufacturing process parameter perturbation and this is represented by a correlation matrix. Variation characterising data generated in accordance with the above technique is used to drive electronic design automation tools in integrated circuit design and manufacture.
摘要翻译：用于表征制造工艺参数中的扰动的电路单元库内的电路单元的性能参数的变化的技术使用统计方法，其中通过制造过程参数空间的联合分布产生的性能参数的统计分布决心，决意，决定。然后识别导致特征变化量的制造过程参数中的扰动，并且将用于将电路单元的族分组在一起的这种扰动的常见集合。电路单元族在其对制造工艺参数扰动的响应中具有相关性，并且由相关矩阵表示。根据上述技术生成的变化特征数据用于驱动集成电路设计和制造中的电子设计自动化工具。

7. 发明申请

US20110302460A1 Apparatus and method for detecting an approaching error condition 有权
标题翻译：用于检测接近错误状况的装置和方法
公开(公告)号：US20110302460A1
公开(公告)日：2011-12-08
申请号：US12801402
申请日：2010-06-07
申请人： Sachin Satish Idgunji , Shidhartha Das , David Michael Bull , Robert Campbell Aitken
发明人： Sachin Satish Idgunji , Shidhartha Das , David Michael Bull , Robert Campbell Aitken
IPC分类号： G06F11/07
CPC分类号： G01R31/3016
摘要： An apparatus and method are provided for detecting an approaching error condition within a data processing apparatus. The data processing apparatus includes a second sequential storage structure which is arranged to latch the output signal generated by combinatorial circuitry dependent on a second clock signal. The second sequential storage structure has a main storage element to latch a value of the output signal for provision to subsequent combinatorial circuitry, and transition detection circuitry for detecting a change of the value of the output signal latched by the main storage element during a predetermined timing window, said change indicating an approaching error condition whilst the value stored in the main storage element is still correct. The second sequential storage structure can be operated in either a first mode of operation or a second mode of operation. In the first mode of operation, the predetermined timing window is a timing window ahead of a time at which the main storage element latches said value of the output signal, to thereby enable an approaching setup timing error due to a propagation delay within the combinatorial circuitry to be detected. In the second mode of operation, the predetermined timing window is a timing window after the time at which the main storage element latches said value of the output signal such that an approaching hold timing error due to an increase in skew between the first and second clock signals is detected. Such a technique provides a simple and efficient mechanism for detecting a variety of approaching error conditions whilst the second sequence storage structure continues to operate correctly.
摘要翻译：提供了一种用于检测数据处理装置内接近的错误状况的装置和方法。数据处理装置包括第二顺序存储结构，其被配置为根据第二时钟信号锁存由组合电路产生的输出信号。第二顺序存储结构具有主存储元件，用于锁存输出信号的值以提供给后续组合电路;以及转换检测电路，用于检测由主存储元件在预定定时期间锁存的输出信号的值的变化窗口，所述改变指示接近的错误状态，而存储在主存储元件中的值仍然是正确的。第二顺序存储结构可以在第一操作模式或第二操作模式中操作。在第一操作模式中，预定定时窗口是在主存储元件锁存输出信号的值的时间之前的定时窗口，从而使由于组合电路内的传播延迟引起的接近建立定时误差被检测。在第二操作模式中，预定定时窗口是在主存储元件锁存输出信号的值的时间之后的定时窗口，使得由于第一和第二时钟之间的偏斜增加而接近的保持定时误差检测到信号。这种技术提供了一种用于检测各种接近错误状况的简单有效的机制，同时第二序列存储结构继续正确地操作。

8. 发明授权

US07737720B2 Virtual power rail modulation within an integrated circuit 有权
标题翻译：集成电路内的虚拟电源轨调制
公开(公告)号：US07737720B2
公开(公告)日：2010-06-15
申请号：US11797497
申请日：2007-05-03
申请人： Sachin Satish Idgunji , David Walter Flynn , Robert Campbell Aitken
发明人： Sachin Satish Idgunji , David Walter Flynn , Robert Campbell Aitken
IPC分类号： H03K19/003
CPC分类号： H03K19/0016 , H03K19/096 , Y10T307/461
摘要： An integrated circuit is provided with logic blocks which draw their power from virtual supply rails. These virtual supply rails are connected by switch blocks to main supply rails. The switch blocks are subject to modulation to maintain the virtual supply rails at an intermediate voltage level such that a reduced voltage difference is applied across the logic block. This intermediate voltage level is used in a state retention mode in which the clock signal clk to the logic block is stopped and state signal values are maintained therein using this reduced virtual power rail derived voltage difference. When it is desired to resume processing then the full virtual rail voltages are restored by rendering the switch blocks fully conductive and then the clock is restarted. The switch blocks which are modulated by controllers which use feedback control based upon the sensed virtual rail voltages (VVdd and Vgnd) while drawing their own power from the normal supply rails (Vdd and gnd).
摘要翻译：集成电路提供有从虚拟电源轨道吸取功率的逻辑块。这些虚拟电源轨由开关块连接到主电源轨。开关块经受调制以将虚拟电源轨保持在中间电压电平，使得在逻辑块上施加减小的电压差。该中间电压电平用于停止逻辑块的时钟信号clk的状态保持模式，并且使用该减小的虚拟电力轨道导出的电压差来保持状态信号值。当希望恢复处理时，通过使开关块完全导通然后重新启动时钟来恢复完整的虚拟轨电压。所述开关块由控制器调制，所述控制器使用基于感测的虚拟轨电压（VVdd和Vgnd）的反馈控制，同时从正常供电轨（Vdd和gnd）吸取其自身功率。

9. 发明申请

US20090222775A1 Characterising circuit cell performance variability in response to pertibations in manufacturing process parameters 有权
标题翻译：表征响应于制造工艺参数中的扰动的电路单元性能变化
公开(公告)号：US20090222775A1
公开(公告)日：2009-09-03
申请号：US12073050
申请日：2008-02-28
申请人： Sachin Satish Idgunji , Robert Campbell Aitken
发明人： Sachin Satish Idgunji , Robert Campbell Aitken
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/12 , G06F2217/66 , Y02P90/265
摘要： A technique for characterising variation in a performance parameter(s) of circuit cells within a circuit cell library with perturbations in manufacturing process parameters uses a statistical approach whereby the statistical distribution of performance parameter(s) resulting from a joint distribution across manufacturing process parameter space is determined. The perturbation in manufacturing process parameter which results in a characteristic amount of variation is then identified and common sets of such perturbations used to group families of circuit cells together. Families of circuit cells have a correlation in their response to manufacturing process parameter perturbation and this is represented by a correlation matrix. Variation characterising data generated in accordance with the above technique is used to drive electronic design automation tools in integrated circuit design and manufacture.
摘要翻译：用于表征制造工艺参数中的扰动的电路单元库内的电路单元的性能参数的变化的技术使用统计方法，其中通过制造过程参数空间的联合分布产生的性能参数的统计分布决心，决意，决定。然后识别导致特征变化量的制造过程参数中的扰动，并且将用于将电路单元的族分组在一起的这种扰动的常见集合。电路单元族在其对制造工艺参数扰动的响应中具有相关性，并且由相关矩阵表示。根据上述技术生成的变化特征数据用于驱动集成电路设计和制造中的电子设计自动化工具。

10. 发明授权

US09269418B2 Apparatus and method for controlling refreshing of data in a DRAM 有权
标题翻译：用于控制DRAM中数据刷新的装置和方法
公开(公告)号：US09269418B2
公开(公告)日：2016-02-23
申请号：US13366660
申请日：2012-02-06
申请人： Donald Felton , Emre Özer , Sachin Satish Idgunji
发明人： Donald Felton , Emre Özer , Sachin Satish Idgunji
IPC分类号： G06F12/14 , G11C11/406 , G06F21/75 , G06F21/79 , G11C11/408
CPC分类号： G11C11/40622 , G06F21/75 , G06F21/79 , G11C11/408 , G11C2211/4065
摘要： An apparatus comprises a dynamic random-access memory (DRAM) for storing data. Refresh control circuitry is provided to control the DRAM to periodically perform a refresh cycle for refreshing the data stored in each memory location of the DRAM. A refresh address sequence generator generates a refresh address sequence of addresses identifying the order in which memory locations of the DRAM are refreshed during the refresh cycle. To deter differential power analysis attacks on secure data stored in the DRAM, the refresh address sequence is generated with the addresses of at least a portion of the memory locations in a random order which varies from refresh cycle to refresh cycle.
摘要翻译：一种装置包括用于存储数据的动态随机存取存储器（DRAM）。提供刷新控制电路以控制DRAM周期性地执行用于刷新存储在DRAM的每个存储器位置中的数据的刷新周期。刷新地址序列发生器产生识别在刷新周期期间刷新DRAM的存储器位置的顺序的地址的刷新地址序列。为了阻止对存储在DRAM中的安全数据的差分功率分析攻击，刷新地址序列以从刷新周期到刷新周期的随机顺序的至少一部分存储器位置的地址生成。

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