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1. 发明授权

US09269418B2 Apparatus and method for controlling refreshing of data in a DRAM 有权
标题翻译：用于控制DRAM中数据刷新的装置和方法
公开(公告)号：US09269418B2
公开(公告)日：2016-02-23
申请号：US13366660
申请日：2012-02-06
申请人： Donald Felton , Emre Özer , Sachin Satish Idgunji
发明人： Donald Felton , Emre Özer , Sachin Satish Idgunji
IPC分类号： G06F12/14 , G11C11/406 , G06F21/75 , G06F21/79 , G11C11/408
CPC分类号： G11C11/40622 , G06F21/75 , G06F21/79 , G11C11/408 , G11C2211/4065
摘要： An apparatus comprises a dynamic random-access memory (DRAM) for storing data. Refresh control circuitry is provided to control the DRAM to periodically perform a refresh cycle for refreshing the data stored in each memory location of the DRAM. A refresh address sequence generator generates a refresh address sequence of addresses identifying the order in which memory locations of the DRAM are refreshed during the refresh cycle. To deter differential power analysis attacks on secure data stored in the DRAM, the refresh address sequence is generated with the addresses of at least a portion of the memory locations in a random order which varies from refresh cycle to refresh cycle.
摘要翻译：一种装置包括用于存储数据的动态随机存取存储器（DRAM）。提供刷新控制电路以控制DRAM周期性地执行用于刷新存储在DRAM的每个存储器位置中的数据的刷新周期。刷新地址序列发生器产生识别在刷新周期期间刷新DRAM的存储器位置的顺序的地址的刷新地址序列。为了阻止对存储在DRAM中的安全数据的差分功率分析攻击，刷新地址序列以从刷新周期到刷新周期的随机顺序的至少一部分存储器位置的地址生成。

2. 发明申请

US20120254698A1 Memory scrubbing 有权
标题翻译：记忆擦洗
公开(公告)号：US20120254698A1
公开(公告)日：2012-10-04
申请号：US13064554
申请日：2011-03-30
申请人： Emre Özer , Sachin Satish Idgunji
发明人： Emre Özer , Sachin Satish Idgunji
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/106 , H03M13/05
摘要： A data processing apparatus is provided which comprises a processor unit configured to perform data processing operations in response to a sequence of instructions and a storage unit configured to store data values for access by the processor unit when performing its data processing operations. Redundant error control data is stored in association with the data values, the redundant error control data enabling identification of an error in the data values. The data processing apparatus also comprises a data scrubbing unit configured to perform a data scrubbing process on at least a subset of the data values, the data scrubbing process comprising determining with reference to the redundant error control data if an error is present in that subset of data values and, where possible, correcting that error with reference to the redundant error control data. The data scrubbing unit is configured to receive a scrub transaction issued within said data processing apparatus, and to perform the data scrubbing process upon receipt of the scrub transaction.
摘要翻译：提供了一种数据处理装置，其包括处理器单元，其被配置为响应于指令序列执行数据处理操作;以及存储单元，被配置为存储用于在执行其数据处理操作时由处理器单元访问的数据值。与数据值相关联地存储冗余错误控制数据，冗余错误控制数据使得能够识别数据值中的错误。数据处理装置还包括数据擦除单元，被配置为对数据值的至少一个子集执行数据擦除处理，数据擦除处理包括参考冗余错误控制数据确定如果在该子集中存在错误数据值，并且在可能的情况下，参考冗余错误控制数据来校正该错误。数据擦除单元被配置为接收在所述数据处理设备内发出的擦除事务，并且在接收到擦除事务时执行数据擦除处理。

3. 发明授权

US08826097B2 Memory scrubbing 有权
标题翻译：记忆擦洗
公开(公告)号：US08826097B2
公开(公告)日：2014-09-02
申请号：US13064554
申请日：2011-03-30
申请人： Emre Özer , Sachin Satish Idgunji
发明人： Emre Özer , Sachin Satish Idgunji
IPC分类号： G11C29/00 , G06F11/10 , H03M13/05
CPC分类号： G06F11/106 , H03M13/05
摘要： A data processing apparatus is provided which comprises a processor unit configured to perform data processing operations in response to a sequence of instructions and a storage unit configured to store data values for access by the processor unit when performing its data processing operations. Redundant error control data is stored in association with the data values, the redundant error control data enabling identification of an error in the data values. The data processing apparatus also comprises a data scrubbing unit configured to perform a data scrubbing process on at least a subset of the data values, the data scrubbing process comprising determining with reference to the redundant error control data if an error is present in that subset of data values and, where possible, correcting that error with reference to the redundant error control data. The data scrubbing unit is configured to receive a scrub transaction issued within said data processing apparatus, and to perform the data scrubbing process upon receipt of the scrub transaction.
摘要翻译：提供了一种数据处理装置，其包括处理器单元，其被配置为响应于指令序列执行数据处理操作;以及存储单元，被配置为存储用于在执行其数据处理操作时由处理器单元访问的数据值。与数据值相关联地存储冗余错误控制数据，冗余错误控制数据使得能够识别数据值中的错误。数据处理装置还包括数据擦除单元，被配置为对数据值的至少一个子集执行数据擦除处理，数据擦除处理包括参考冗余错误控制数据确定如果在该子集中存在错误数据值，并且在可能的情况下，参考冗余错误控制数据来校正该错误。数据擦除单元被配置为接收在所述数据处理设备内发出的擦除事务，并且在接收到擦除事务时执行数据擦除处理。

4. 发明授权

US08205206B2 Data processing apparatus and method for managing multiple program threads executed by processing circuitry 有权
标题翻译：用于管理由处理电路执行的多个程序线程的数据处理装置和方法
公开(公告)号：US08205206B2
公开(公告)日：2012-06-19
申请号：US12149772
申请日：2008-05-08
申请人： Emre Özer , Stuart David Biles
发明人： Emre Özer , Stuart David Biles
IPC分类号： G06F9/46 , G06F13/00
CPC分类号： G06F9/3851 , G06F9/5011 , G06F2209/5021 , G06F2209/507
摘要： A data processing apparatus and method are provided for managing multiple program threads executed by processing circuitry. The multiple program threads include at least one high priority program thread and at least one lower priority program thread. At least one storage unit is shared between the multiple program threads and has multiple entries for storing information for reference by the processing circuitry when executing the program threads. Thread control circuitry is used to detect a condition indicating an adverse effect caused by a lower priority program thread being executed by the processing circuitry and resulting from sharing of the at least one storage unit between the multiple program threads. On detection of such a condition, the thread control circuitry issues an alert signal, and a scheduler is then responsive to the alert signal to cause execution of the lower priority program thread causing the adverse effect to be temporarily halted, for example by causing that lower priority program thread to be de-allocated and an alternative lower priority program thread allocated in its place. This has been found to provide a particularly efficient mechanism for allowing any high priority program thread to progress as much as possible, while at the same time improving the overall processor throughput by seeking to find co-operative lower priority program threads.
摘要翻译：提供了一种用于管理由处理电路执行的多个程序线程的数据处理装置和方法。多个程序线程包括至少一个高优先级程序线程和至少一个较低优先级的程序线程。在多个程序线程之间共享至少一个存储单元，并且具有用于存储信息的多个条目，供执行程序线程时由处理电路参考。线程控制电路用于检测指示由处理电路执行的较低优先级程序线程引起的不利影响的状况，并且由多个程序线程之间的至少一个存储单元的共享产生。在检测到这种情况时，线程控制电路发出报警信号，并且调度器然后对报警信号作出响应，从而导致低优先级程序线程的执行，从而导致不利影响被暂时停止，例如通过使得较低要重新分配的优先级程序线程和分配给其的替代低优先级程序线程。已经发现，这提供了一种特别有效的机制，用于允许任何高优先级的程序线程尽可能地进行，同时通过寻求找到合作的较低优先级的程序线程来提高整体处理器的吞吐量。

5. 发明授权

US09032188B2 Issue policy control within a multi-threaded in-order superscalar processor 有权
标题翻译：在多线程按顺序超标量处理器中发布策略控制
公开(公告)号：US09032188B2
公开(公告)日：2015-05-12
申请号：US12078100
申请日：2008-03-27
申请人： Emre Özer , Stuart David Biles
发明人： Emre Özer , Stuart David Biles
IPC分类号： G06F15/00 , G06F9/30 , G06F9/40 , G06F9/38 , G06F9/48
CPC分类号： G06F9/3851 , G06F9/4881
摘要： A multi-threaded in-order superscalar processor 2 includes an issue stage 12 including issue circuitry 22, 24 for selecting instructions to be issued to execution units 14, 16 in dependence upon a currently selected issue policy. A plurality of different issue policies are provided by associated different policy circuitry 28, 30, 32 and a selection between which of these instances of the policy circuitry 28, 30, 32 is active is made by policy selecting circuitry 34 in dependence upon detected dynamic behavior of the processor 2.
摘要翻译：多线程顺序超标量处理器2包括发行阶段12，其包括发行电路22,24，用于根据当前选择的发行策略来选择要发布到执行单元14,16的指令。多个不同的问题策略由相关联的不同策略电路28,30,32提供，并且策略电路28,30,32的这些实例中的哪一个被选择是由策略选择电路34根据检测到的动态行为的处理器2。

6. 发明授权

US08732523B2 Data processing apparatus and method for analysing transient faults occurring within storage elements of the data processing apparatus 有权
标题翻译：用于分析数据处理装置的存储元件内发生的瞬态故障的数据处理装置和方法
公开(公告)号：US08732523B2
公开(公告)日：2014-05-20
申请号：US13317593
申请日：2011-10-24
申请人： Emre Özer , Yiannakis Sazeides , Daniel Kershaw , Stuart David Biles
发明人： Emre Özer , Yiannakis Sazeides , Daniel Kershaw , Stuart David Biles
IPC分类号： G06F11/00
CPC分类号： G06F11/1415 , G06F11/0727 , G06F11/076 , G06F11/0787 , G06F2201/86
摘要： A data processing apparatus has a plurality of storage elements residing at different physical locations within the apparatus, and fault history circuitry for detecting local transient faults occurring in each storage element, and for maintaining global transient fault history data based on the detected local transient faults. Analysis circuitry monitors the global transient fault history data to determine, based on predetermined criteria, whether the global transient fault history data is indicative of random transient faults occurring within the data processing apparatus, or is indicative of a coordinated transient fault attack. The analysis circuitry is then configured to initiate a countermeasure action on determination of a coordinated transient fault attack. This provides a simple and effective mechanism for distinguishing between random transient faults that may naturally occur, and a coordinated transient fault attack that may be initiated in an attempt to circumvent the security of the data processing apparatus.
摘要翻译：数据处理装置具有驻留在装置内的不同物理位置的多个存储元件，以及故障历史电路，用于检测每个存储元件中发生的局部瞬态故障，并且用于基于检测到的局部瞬态故障来维护全局瞬态故障历史数据。分析电路监视全局瞬态故障历史数据，以基于预定标准确定全局瞬态故障历史数据是否表示在数据处理装置内发生的随机瞬态故障，或指示协调的瞬时故障攻击。分析电路然后被配置为启动对协调的瞬态故障攻击的确定的对策动作。这提供了一种用于区分可能自然发生的随机瞬态故障的简单和有效的机制，以及可以在试图绕过数据处理设备的安全性时发起的协调的瞬态故障攻击。

7. 发明授权

US08099556B2 Cache miss detection in a data processing apparatus 有权
标题翻译：数据处理装置中的缓存未命中检测
公开(公告)号：US08099556B2
公开(公告)日：2012-01-17
申请号：US11990394
申请日：2005-09-13
申请人： Mrinmoy Ghosh , Emre Özer , Stuart David Biles
发明人： Mrinmoy Ghosh , Emre Özer , Stuart David Biles
IPC分类号： G06F12/08
CPC分类号： G06F9/3851 , G06F9/383 , G06F12/0802 , G06F12/0897
摘要： A data processing apparatus and method are provided for detecting cache misses. The data processing apparatus has processing logic for executing a plurality of program threads, and a cache for storing data values for access by the processing logic. When access to a data value is required while executing a first program thread, the processing logic issues an access request specifying an address in memory associated with that data value, and the cache is responsive to the address to perform a lookup procedure to determine whether the data value is stored in the cache. Indication logic is provided which in response to an address portion of the address provides an indication as to whether the data value is stored in the cache, this indication being produced before a result of the lookup procedure is available, and the indication logic only issuing an indication that the data value is not stored in the cache if that indication is guaranteed to be correct. Control logic is then provided which, if the indication indicates that the data value is not stored in the cache, uses that indication to control a process having an effect on a program thread other than the first program thread.
摘要翻译：提供了一种用于检测高速缓存未命中的数据处理装置和方法。数据处理装置具有用于执行多个程序线程的处理逻辑，以及用于存储由处理逻辑进行访问的数据值的高速缓存。当执行第一程序线程时需要访问数据值时，处理逻辑发出指定与该数据值相关联的存储器中的地址的访问请求，并且高速缓冲存储器响应于该地址执行查找过程以确定是否数据值存储在缓存中。指示逻辑被提供，其响应于地址的地址部分提供关于数据值是否存储在高速缓存中的指示，该指示在查找过程的结果可用之前产生，并且指示逻辑仅发出指示如果该指示保证正确，则数据值不存储在高速缓存中。然后提供控制逻辑，如果该指示指示数据值未被存储在高速缓存中，则使用该指示来控制对除第一程序线程之外的程序线程有影响的进程。

8. 发明授权

US08195886B2 Data processing apparatus and method for implementing a replacement scheme for entries of a storage unit 有权
标题翻译：一种用于实现用于存储单元的条目的替换方案的数据处理装置和方法
公开(公告)号：US08195886B2
公开(公告)日：2012-06-05
申请号：US11723189
申请日：2007-03-16
申请人： Emre Özer , Stuart David Biles
发明人： Emre Özer , Stuart David Biles
IPC分类号： G06F12/12
CPC分类号： G06F12/126
摘要： A data processing apparatus and method are provided for implementing a replacement scheme for entries of a storage unit. The data processing apparatus has processing circuitry for executing multiple program threads including at least one high priority program thread and at least one lower priority program thread. A storage unit is then shared between the multiple program threads and has multiple entries for storing information for reference by the processing circuitry when executing the program threads. A record is maintained identifying for each entry whether the information stored in that entry is associated with a high priority program thread or a lower priority program thread. Replacement circuitry is then responsive to a predetermined event in order to select a victim entry whose stored information is to be replaced. To achieve this, the replacement circuitry performs a candidate generation operation to identify a plurality of randomly selected candidate entries, and then references the record in order to preferentially select as the victim entry a candidate entry whose stored information is associated with a lower priority program thread. This improves the performance of the high priority program thread(s) by preferentially evicting from the storage unit entries associated with lower priority program threads.
摘要翻译：提供了一种数据处理装置和方法，用于实现用于存储单元的条目的替换方案。数据处理装置具有用于执行包括至少一个高优先级程序线程和至少一个较低优先级程序线程的多个程序线程的处理电路。然后，存储单元在多个程序线程之间共享，并且具有用于存储用于在执行程序线程时由处理电路参考的信息的多个条目。维护记录以识别每个条目，存储在该条目中的信息是否与高优先级程序线程或较低优先级的程序线程相关联。然后，替换电路响应于预定事件，以便选择其存储的信息将被替换的受害者条目。为了实现这一点，替换电路执行候选生成操作以识别多个随机选择的候选条目，然后引用该记录，以优先选择其存储的信息与较低优先级的程序线程相关联的候选条目作为受害者条目。这通过优先从与优先级较低的程序线程相关联的存储单元条目中逐出来来提高高优先级程序线程的性能。

9. 发明授权

US07979642B2 Managing the storage of high-priority storage items in storage units in multi-core and multi-threaded systems using history storage and control circuitry 有权
标题翻译：在使用历史存储和控制电路的多核和多线程系统中管理存储单元中高优先级存储项目的存储
公开(公告)号：US07979642B2
公开(公告)日：2011-07-12
申请号：US12232188
申请日：2008-09-11
申请人： David Michael Bull , Emre Özer
发明人： David Michael Bull , Emre Özer
IPC分类号： G06F13/00
CPC分类号： G06F12/126 , G06F9/3806 , G06F9/3851
摘要： A data processing apparatus is provided comprising processing circuitry for executing multiple program threads. At least one storage unit is shared between the multiple program threads and comprises multiple entries, each entry for storing a storage item either associated with a high priority program thread or a lower priority program thread. A history storage for retaining a history field for each of a plurality of blocks of the storage unit is also provided. On detection of a high priority storage item being evicted from the storage unit as a result of allocation to that entry of a lower priority storage item, the history field for the block containing that entry is populated with an indication of the evicted high priority storage item. When later a high priority storage item is allocated to a selected entry of the storage unit, a comparison operation between the allocated high priority storage item and the indication in the history field for the block containing the selected entry is carried out, and on detection of a match condition a lock indication associated with that entry is set to inhibit further eviction of that high priority storage item.
摘要翻译：提供了一种数据处理装置，包括用于执行多个程序线程的处理电路。至少一个存储单元在多个程序线程之间共享并且包括多个条目，每个条目用于存储与高优先级程序线程或较低优先级程序线程相关联的存储项目。还提供了用于保存存储单元的多个块中的每一个的历史字段的历史存储器。在检测到作为对较低优先级存储项目的该条目的分配的结果被从存储单元驱逐的高优先级存储项目时，包含该条目的块的历史字段填充有被驱逐的高优先级存储项目的指示。当稍后将高优先级存储项目分配给存储单元的所选条目时，执行所分配的高优先级存储项目与包含所选择的条目的块的历史字段中的指示之间的比较操作，并且在检测到匹配条件与该条目相关联的锁定指示被设置为禁止进一步驱逐该高优先级存储项目。

10. 发明授权

US07937535B2 Managing cache coherency in a data processing apparatus 有权
标题翻译：在数据处理设备中管理高速缓存一致性
公开(公告)号：US07937535B2
公开(公告)日：2011-05-03
申请号：US11709279
申请日：2007-02-22
申请人： Emre Özer , Stuart David Biles , Simon Andrew Ford
发明人： Emre Özer , Stuart David Biles , Simon Andrew Ford
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0831 , G06F12/0822 , Y02D10/13
摘要： Each of plural processing units has a cache, and each cache has indication circuitry containing segment filtering data. The indication circuitry responds to an address specified by an access request from an associated processing unit to reference the segment filtering data to indicate whether the data is either definitely not stored or is potentially stored in that segment. Cache coherency circuitry ensures that data accessed by each processing unit is up-to-date and has snoop indication circuitry whose content is derived from the already-provided segment filtering data. For certain access requests, the cache coherency circuitry initiates a coherency operation during which the snoop indication circuitry determines whether any of the caches requires a snoop operation. For each cache that does, the cache coherency circuitry issues a notification to that cache identifying the snoop operation to be performed.
摘要翻译：多个处理单元中的每一个具有高速缓存，并且每个高速缓存具有包含段过滤数据的指示电路。指示电路响应来自相关联的处理单元的访问请求指定的地址以引用段过滤数据，以指示数据是否被明确地不存储或潜在地存储在该段中。高速缓存一致性电路确保每个处理单元访问的数据是最新的，并且具有其内容源自已经提供的段过滤数据的窥探指示电路。对于某些访问请求，高速缓存一致性电路发起一致性操作，在此期间，窥探指示电路确定是否有任何缓存需要窥探操作。对于每个缓存，高速缓存一致性电路向该缓存发出一个通知，用于标识要执行的侦听操作。

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