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1. 发明授权

US08519775B2 Voltage regulation of a virtual power rail 有权
标题翻译：虚拟电源轨的电压调节
公开(公告)号：US08519775B2
公开(公告)日：2013-08-27
申请号：US13137224
申请日：2011-07-28
申请人： Sachin Satish Idgunji , Bal S Sandhu
发明人： Sachin Satish Idgunji , Bal S Sandhu
IPC分类号： H03K3/01
CPC分类号： H03K19/0016 , H03K19/0013
摘要： A voltage regulator for regulating a voltage level of a virtual power rail supplying power to logic circuitry in a low power data retention mode is disclosed. The voltage regulator comprises: switching circuitry having a transistor for coupling said virtual power rail to a power supply having a supply voltage level; control circuitry responsive to a signal indicating the logic circuitry is to enter the low data power retention mode to control the switching circuitry to switch to a conductive state in which the transistor is operating in a saturation region of operation and supplying a saturation current from the power supply via the virtual power rail to the logic circuitry; and a leakage power controller for adjusting a voltage level of the virtual power rail to control leakage power. The leakage power controller is configured to supply a bias voltage to the well in which the switching circuitry is formed, the saturation current of the switching circuitry being dependent on a value of the well bias voltage. The leakage power controller is configured to adjust the well bias voltage of the switching circuitry thereby varying the saturation current and the voltage level of the virtual power rail.
摘要翻译：公开了一种用于调节在低功率数据保持模式下向逻辑电路供电的虚拟电源轨的电压电平的电压调节器。电压调节器包括：具有用于将所述虚拟电力轨耦合到具有电源电压电平的电源的晶体管的开关电路; 响应于指示逻辑电路的信号的控制电路是进入低数据功率保持模式以控制开关电路切换到导通状态，其中晶体管在饱和运行区域中工作，并从功率提供饱和电流通过虚拟电源轨供电到逻辑电路; 以及泄漏功率控制器，用于调节虚拟电源轨的电压电平以控制泄漏电力。泄漏功率控制器被配置为向其中形成开关电路的阱提供偏置电压，开关电路的饱和电流取决于阱偏置电压的值。泄漏功率控制器被配置为调节开关电路的阱偏置电压，从而改变虚拟电源轨的饱和电流和电压电平。

2. 发明申请

US20110122712A1 Controlling voltage levels applied to access devices when accessing storage cells in a memory 有权
标题翻译：控制访问存储器中的存储单元时访问设备的电压电平
公开(公告)号：US20110122712A1
公开(公告)日：2011-05-26
申请号：US12591511
申请日：2009-11-20
申请人： Sachin Satish Idgunji , Hemangi Umakant Gajjewar , Gus Yeung
发明人： Sachin Satish Idgunji , Hemangi Umakant Gajjewar , Gus Yeung
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C11/413
摘要： A semiconductor memory storage device is disclosed. This memory device has a plurality of storage cells for storing data; a plurality of access devices for allowing access to the corresponding plurality of storage cells, the plurality of access devices being arranged in at least two groups, each of the at least two groups being controlled by an access control line; access control circuitry for controlling a voltage level supplied to a selected one of at least two of the access control lines during access to the storage cell, the access control circuitry comprising a capacitor and switching circuitry; and control circuitry responsive to a data access request to access a selected storage cell to: connect a selected one of the access control lines to a voltage level to allow access via one of the access devices to the selected storage cell; and to control the switching circuitry of the access control circuitry to connect the capacitor of the access control circuitry to the selected access control line and thereby change the voltage level supplied to the selected access control line.
摘要翻译：公开了一种半导体存储器存储装置。该存储装置具有用于存储数据的多个存储单元; 用于允许访问对应的多个存储单元的多个访问设备，所述多个访问设备被布置成至少两组，所述至少两个组中的每一个由访问控制线控制; 访问控制电路，用于在访问存储单元期间控制提供给至少两个访问控制线路中的所选择的一个的电压电平，所述访问控制电路包括电容器和开关电路; 以及响应于数据访问请求以访问所选存储单元的控制电路，以将所述访问控制线中的所选择的一个连接到电压电平，以允许经由所述访问设备之一访问所选择的存储单元; 并且控制访问控制电路的切换电路以将访问控制电路的电容器连接到所选择的访问控制线，从而改变提供给所选择的访问控制线路的电压电平。

3. 发明授权

US09269418B2 Apparatus and method for controlling refreshing of data in a DRAM 有权
标题翻译：用于控制DRAM中数据刷新的装置和方法
公开(公告)号：US09269418B2
公开(公告)日：2016-02-23
申请号：US13366660
申请日：2012-02-06
申请人： Donald Felton , Emre Özer , Sachin Satish Idgunji
发明人： Donald Felton , Emre Özer , Sachin Satish Idgunji
IPC分类号： G06F12/14 , G11C11/406 , G06F21/75 , G06F21/79 , G11C11/408
CPC分类号： G11C11/40622 , G06F21/75 , G06F21/79 , G11C11/408 , G11C2211/4065
摘要： An apparatus comprises a dynamic random-access memory (DRAM) for storing data. Refresh control circuitry is provided to control the DRAM to periodically perform a refresh cycle for refreshing the data stored in each memory location of the DRAM. A refresh address sequence generator generates a refresh address sequence of addresses identifying the order in which memory locations of the DRAM are refreshed during the refresh cycle. To deter differential power analysis attacks on secure data stored in the DRAM, the refresh address sequence is generated with the addresses of at least a portion of the memory locations in a random order which varies from refresh cycle to refresh cycle.
摘要翻译：一种装置包括用于存储数据的动态随机存取存储器（DRAM）。提供刷新控制电路以控制DRAM周期性地执行用于刷新存储在DRAM的每个存储器位置中的数据的刷新周期。刷新地址序列发生器产生识别在刷新周期期间刷新DRAM的存储器位置的顺序的地址的刷新地址序列。为了阻止对存储在DRAM中的安全数据的差分功率分析攻击，刷新地址序列以从刷新周期到刷新周期的随机顺序的至少一部分存储器位置的地址生成。

4. 发明申请

US20130328533A1 LEAKAGE CURRENT REDUCTION IN AN INTEGRATED CIRCUIT 有权
标题翻译：集成电路中的漏电流减少
公开(公告)号：US20130328533A1
公开(公告)日：2013-12-12
申请号：US13493236
申请日：2012-06-11
申请人： Sachin Satish IDGUNJI , Bal S. Sandhu
发明人： Sachin Satish IDGUNJI , Bal S. Sandhu
IPC分类号： G05F1/10
CPC分类号： G06F1/26 , H03K19/0008 , H03K19/00369 , H03K2017/066 , H03K2217/0018
摘要： An integrated circuit is provided with operational mode header transistors which connect a virtual power rail to a VDD power supply. A controller circuit, responsive to a sensed voltage signal from a voltage sensor which reads the virtual rail voltage VVDD, generates a control signal which controls the operational mode transistors. The control signal is derived from an interface voltage power supply that provides higher voltage VDD IO than the VDD power supply and thus able to overdrive the operational mode transistors via either a gate bias voltage or a bulk bias voltage. The amount of leakage through the operational mode transistors is controlled in a closed loop feedback arrangement so as to maintain a predetermined target value or range for the virtual rail voltage. The operational mode transistor may also be controlled to support dynamic voltage and frequency scaling.
摘要翻译：集成电路设置有将虚拟电源轨连接到VDD电源的操作模式头部晶体管。响应于来自读取虚拟轨电压VVDD的电压传感器的感测电压信号的控制器电路产生控制操作模式晶体管的控制信号。该控制信号来源于提供比VDD电源更高电压VDD IO的接口电压电源，从而能够通过栅极偏置电压或体偏置电压来过载驱动工作模式晶体管。通过操作模式晶体管的泄漏量被控制在闭环反馈装置中，以便维持虚拟轨道电压的预定目标值或范围。还可以控制操作模式晶体管以支持动态电压和频率缩放。

5. 发明授权

US08555124B2 Apparatus and method for detecting an approaching error condition 有权
标题翻译：用于检测接近错误状况的装置和方法
公开(公告)号：US08555124B2
公开(公告)日：2013-10-08
申请号：US12801402
申请日：2010-06-07
申请人： Sachin Satish Idgunji , Shidhartha Das , David Michael Bull , Robert Campbell Aitken
发明人： Sachin Satish Idgunji , Shidhartha Das , David Michael Bull , Robert Campbell Aitken
IPC分类号： G01R31/28
CPC分类号： G01R31/3016
摘要： An apparatus and method are provided for detecting an approaching error condition within a data processing apparatus and includes a sequential storage structure arranged to latch an output signal generated by combinatorial circuitry dependent on a second clock signal. The sequential storage structure has a main storage element to latch a value of the output signal for provision to subsequent combinatorial circuitry. The sequential storage structure can be operated in either first or second modes of operation where, in the first mode, the predetermined timing window is ahead of a time at which the main storage element latches said value of the output signal enabling an approaching setup timing error to be detected. In the second mode, the predetermined timing window is after the time at which the main storage element latches said value of the output signal where an approaching hold timing error is detected.
摘要翻译：提供了一种用于检测数据处理装置内接近的错误状况的装置和方法，并且包括顺序存储结构，其被布置为根据第二时钟信号锁存由组合电路产生的输出信号。顺序存储结构具有主存储元件以锁存输出信号的值以供给后续的组合电路。顺序存储结构可以在第一或第二操作模式中操作，其中在第一模式中，预定定时窗口在主存储元件锁存输出信号的所述值以使得能够接近建立定时误差的时间之前被检测。在第二模式中，预定定时窗口在主存储元件锁存检测到接近保持定时误差的输出信号的值之后。

6. 发明申请

US20130205080A1 APPARATUS AND METHOD FOR CONTROLLING REFRESHING OF DATA IN A DRAM 有权
标题翻译：用于控制DRAM中数据刷新的装置和方法
公开(公告)号：US20130205080A1
公开(公告)日：2013-08-08
申请号：US13366660
申请日：2012-02-06
申请人： Donald FELTON , Emre ÖZER , Sachin Satish IDGUNJI
发明人： Donald FELTON , Emre ÖZER , Sachin Satish IDGUNJI
IPC分类号： G06F12/02
CPC分类号： G11C11/40622 , G06F21/75 , G06F21/79 , G11C11/408 , G11C2211/4065
摘要： An apparatus comprises a dynamic random-access memory (DRAM) for storing data. Refresh control circuitry is provided to control the DRAM to periodically perform a refresh cycle for refreshing the data stored in each memory location of the DRAM. A refresh address sequence generator generates a refresh address sequence of addresses identifying the order in which memory locations of the DRAM are refreshed during the refresh cycle. To deter differential power analysis attacks on secure data stored in the DRAM, the refresh address sequence is generated with the addresses of at least a portion of the memory locations in a random order which varies from refresh cycle to refresh cycle.
摘要翻译：一种装置包括用于存储数据的动态随机存取存储器（DRAM）。提供刷新控制电路以控制DRAM周期性地执行用于刷新存储在DRAM的每个存储器位置中的数据的刷新周期。刷新地址序列发生器产生识别在刷新周期期间刷新DRAM的存储器位置的顺序的地址的刷新地址序列。为了阻止对存储在DRAM中的安全数据的差分功率分析攻击，刷新地址序列以从刷新周期到刷新周期的随机顺序的至少一部分存储器位置的地址生成。

7. 发明授权

US08355276B2 Controlling voltage levels applied to access devices when accessing storage cells in a memory 有权
标题翻译：控制访问存储器中的存储单元时访问设备的电压电平
公开(公告)号：US08355276B2
公开(公告)日：2013-01-15
申请号：US12591511
申请日：2009-11-20
申请人： Sachin Satish Idgunji , Hemangi Umakant Gajjewar , Gus Yeung
发明人： Sachin Satish Idgunji , Hemangi Umakant Gajjewar , Gus Yeung
IPC分类号： G11C11/00 , G11C11/34
CPC分类号： G11C11/413
摘要： A semiconductor memory storage device is disclosed. This memory device has a plurality of storage cells for storing data; a plurality of access devices for allowing access to the corresponding plurality of storage cells, the plurality of access devices being arranged in at least two groups, each of the at least two groups being controlled by an access control line; access control circuitry for controlling a voltage level supplied to a selected one of at least two of the access control lines during access to the storage cell, the access control circuitry comprising a capacitor and switching circuitry; and control circuitry responsive to a data access request to access a selected storage cell to: connect a selected one of the access control lines to a voltage level to allow access via one of the access devices to the selected storage cell; and to control the switching circuitry of the access control circuitry to connect the capacitor of the access control circuitry to the selected access control line and thereby change the voltage level supplied to the selected access control line.
摘要翻译：公开了一种半导体存储器存储装置。该存储装置具有用于存储数据的多个存储单元; 用于允许访问对应的多个存储单元的多个访问设备，所述多个访问设备被布置成至少两组，所述至少两个组中的每一个由访问控制线控制; 访问控制电路，用于在访问存储单元期间控制提供给至少两个访问控制线路中的所选择的一个的电压电平，所述访问控制电路包括电容器和开关电路; 以及响应于数据访问请求以访问所选存储单元的控制电路，以将所述访问控制线中的所选择的一个连接到电压电平，以允许经由所述访问设备之一访问所选择的存储单元; 并且控制访问控制电路的切换电路以将访问控制电路的电容器连接到所选择的访问控制线，从而改变提供给所选择的访问控制线路的电压电平。

8. 发明授权

US08826097B2 Memory scrubbing 有权
标题翻译：记忆擦洗
公开(公告)号：US08826097B2
公开(公告)日：2014-09-02
申请号：US13064554
申请日：2011-03-30
申请人： Emre Özer , Sachin Satish Idgunji
发明人： Emre Özer , Sachin Satish Idgunji
IPC分类号： G11C29/00 , G06F11/10 , H03M13/05
CPC分类号： G06F11/106 , H03M13/05
摘要： A data processing apparatus is provided which comprises a processor unit configured to perform data processing operations in response to a sequence of instructions and a storage unit configured to store data values for access by the processor unit when performing its data processing operations. Redundant error control data is stored in association with the data values, the redundant error control data enabling identification of an error in the data values. The data processing apparatus also comprises a data scrubbing unit configured to perform a data scrubbing process on at least a subset of the data values, the data scrubbing process comprising determining with reference to the redundant error control data if an error is present in that subset of data values and, where possible, correcting that error with reference to the redundant error control data. The data scrubbing unit is configured to receive a scrub transaction issued within said data processing apparatus, and to perform the data scrubbing process upon receipt of the scrub transaction.
摘要翻译：提供了一种数据处理装置，其包括处理器单元，其被配置为响应于指令序列执行数据处理操作;以及存储单元，被配置为存储用于在执行其数据处理操作时由处理器单元访问的数据值。与数据值相关联地存储冗余错误控制数据，冗余错误控制数据使得能够识别数据值中的错误。数据处理装置还包括数据擦除单元，被配置为对数据值的至少一个子集执行数据擦除处理，数据擦除处理包括参考冗余错误控制数据确定如果在该子集中存在错误数据值，并且在可能的情况下，参考冗余错误控制数据来校正该错误。数据擦除单元被配置为接收在所述数据处理设备内发出的擦除事务，并且在接收到擦除事务时执行数据擦除处理。

9. 发明申请

US20130335128A1 SEQUENTIAL LATCHING DEVICE WITH ELEMENTS TO INCREASE HOLD TIMES ON THE DIAGNOSTIC DATA PATH 有权
标题翻译：带有元素的连续锁定装置可增加诊断数据路径上的持续时间
公开(公告)号：US20130335128A1
公开(公告)日：2013-12-19
申请号：US13495362
申请日：2012-06-13
申请人： Sachin Satish IDGUNJI , Robert Campbell AITKEN , Imran IQBAL
发明人： Sachin Satish IDGUNJI , Robert Campbell AITKEN , Imran IQBAL
IPC分类号： H03K3/286 , H03K3/289
CPC分类号： H03K3/0375
摘要： A latching device includes input and output latching elements to receive and output data values wherein the input and output elements are configured to receive a first and second clocks, respectively. The clocks have the same frequency but are inverted. The elements are transparent and transmit data between an input and an output in response to the first value of a received clock and are opaque and hold the data value in response to a second value of the received clock, such that in response to the first and second clocks the input data value is clocked through the input and output elements to the output. The device includes a device for selecting an operational data value or a diagnostic data value for input to the input element in response to a value of a diagnostic enable signal indicating a functional mode or a diagnostic mode.
摘要翻译：锁存装置包括用于接收和输出数据值的输入和输出锁存元件，其中输入和输出元件分别被配置为接收第一和第二时钟。时钟频率相同但反相。这些元件是透明的，并且响应于接收时钟的第一值在输入和输出之间传输数据，并且是不透明的，并且响应于所接收的时钟的第二值保持数据值，使得响应于第一和第二个时钟，输入数据值通过输入和输出元件输出到输出。该装置包括用于响应于指示功能模式或诊断模式的诊断使能信号的值来选择用于输入到输入元件的操作数据值或诊断数据值的装置。

10. 发明申请

US20120320694A1 Write assist in a dual write line semiconductor memory 有权
标题翻译：在双写入半导体存储器中写入辅助
公开(公告)号：US20120320694A1
公开(公告)日：2012-12-20
申请号：US13067629
申请日：2011-06-15
申请人： Hemangi Umakant Gajjewar , Sachin Satish Idgunji , Gus Yeung
发明人： Hemangi Umakant Gajjewar , Sachin Satish Idgunji , Gus Yeung
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C8/16 , G11C11/419
摘要： A semiconductor memory storage device is disclosed, the memory having a plurality of storage cells. Each storage cell comprises two access control devices, each of the access control devices providing the storage cell with access to or isolation from a respective one of two data lines in response to an access control signal, the two data lines being connected to one data port; access control circuitry for applying the access control signal via one of two access control lines to control a plurality of the access control devices; wherein one of the two access control devices of each storage cell is controlled by the access control signal received from a first of the two access control lines to provide the storage cell with access to or isolation from a first of the two data lines, and one further of the two access control devices is controlled by the access control signal received from a second of the two access control lines to provide the storage cell with access to or isolation from a second of the two data lines. The access control circuitry is responsive to a data access request, the data access request being a write request, to apply a data value to be written to both of the first and second data lines and to apply the access control signal to both of the first and second access control lines. In some cases the access control signal is applied to the second of the two access control lines a predetermined time after it is applied to the first of the two access control lines.
摘要翻译：公开了一种半导体存储器存储装置，该存储器具有多个存储单元。每个存储单元包括两个访问控制设备，每个访问控制设备响应于访问控制信号向存储单元提供对两个数据线中的相应一个的访问或隔离，两个数据线连接到一个数据端口 ; 访问控制电路，用于经由两个访问控制线之一来施加访问控制信号，以控制多个访问控制设备; 其中每个存储单元的两个访问控制设备中的一个由从两个访问控制线路中的第一个接收的访问控制信号控制，以向存储单元提供对两条数据线中的第一条线路的访问或者与该两条数据线路中的第一条线路隔离，两个访问控制设备中的另外两个访问控制设备由从两个访问控制线路中的第二个访问控制线路接收的访问控制信号进行控制，以向存储单元提供对这两条数据线路中的第二条路线的隔离。访问控制电路响应于数据访问请求，数据访问请求是写请求，以将要写入的数据值应用于第一和第二数据线，并将访问控制信号应用于第一和第二存取控制线。在一些情况下，将访问控制信号施加到两个访问控制线路中的第一个访问控制线路之后的预定时间内被施加到两个访问控制线路中的第二个。

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