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1. 发明授权

US07605644B2 Integrated circuit power-on control and programmable comparator 有权
标题翻译：集成电路开机控制和可编程比较器
公开(公告)号：US07605644B2
公开(公告)日：2009-10-20
申请号：US11797498
申请日：2007-05-03
申请人： Sachin Satish Idgunji , David Walter Flynn , David William Howard , Robert Campbell Aitken
发明人： Sachin Satish Idgunji , David Walter Flynn , David William Howard , Robert Campbell Aitken
IPC分类号： G05F1/10
CPC分类号： H03K19/0016
摘要： An integrated circuit is provided with a main supply rail and a virtual supply rail connected by strong and weak header transistors. A power-on controller controls the switching on of the strong transistors after the virtual supply rail voltage has already been driven up to close to its operating level by the weak transistor. The power-on controller comprises a comparator monitoring a single reference voltage level with its output being latched within a latch and used to switch on the strong transistor. The comparator may be programmable to detect multiple different trigger voltage levels by using opposing charging and discharging transistors with one set of these operating in a saturated regime and the other in a regime in which the current therethrough varies in dependence upon the voltage being sensed. These opposing transistors can be used to charge or discharge a node with the state of that node being taken to generate the sensed output.
摘要翻译：集成电路设置有主供电轨和通过强和弱标头晶体管连接的虚拟电源轨。在虚拟电源电压已经被弱晶体管驱动到接近其工作电平之后，上电控制器控制强晶体管的导通。上电控制器包括监视单个参考电压电平的比较器，其输出被锁存在锁存器内并用于接通强晶体管。比较器可以被编程为通过使用相反的充电和放电晶体管来检测多个不同的触发电压电平，其中一组在饱和状态下工作，另一组在其中电流根据感测电压而变化。这些相对的晶体管可以用于对具有该节点的状态的节点进行充电或放电以产生感测的输出。

2. 发明申请

US20080272809A1 Integrated circuit power-on control and programmable comparator 有权
标题翻译：集成电路开机控制和可编程比较器
公开(公告)号：US20080272809A1
公开(公告)日：2008-11-06
申请号：US11797498
申请日：2007-05-03
申请人： Sachin Satish Idgunji , David Walter Flynn , David William Howard , Robert Campbell Aitken
发明人： Sachin Satish Idgunji , David Walter Flynn , David William Howard , Robert Campbell Aitken
IPC分类号： H03K5/24
CPC分类号： H03K19/0016
摘要： An integrated circuit is provided with a main supply rail and a virtual supply rail connected by strong and weak header transistors. A power-on controller controls the switching on of the strong transistors after the virtual supply rail voltage has already been driven up to close to its operating level by the weak transistor. The power-on controller comprises a comparator monitoring a single reference voltage level with its output being latched within a latch and used to switch on the strong transistor. The comparator may be programmable to detect multiple different trigger voltage levels by using opposing charging and discharging transistors with one set of these operating in a saturated regime and the other in a regime in which the current therethrough varies in dependence upon the voltage being sensed. These opposing transistors can be used to charge or discharge a node with the state of that node being taken to generate the sensed output.
摘要翻译：集成电路设置有主供电轨和通过强和弱标头晶体管连接的虚拟电源轨。在虚拟电源电压已经被弱晶体管驱动到接近其工作电平之后，上电控制器控制强晶体管的导通。上电控制器包括监视单个参考电压电平的比较器，其输出被锁存在锁存器内并用于接通强晶体管。比较器可以被编程为通过使用相反的充电和放电晶体管来检测多个不同的触发电压电平，其中一组在饱和状态下工作，另一组在其中电流根据感测电压而变化。这些相对的晶体管可以用于对具有该节点的状态的节点进行充电或放电以产生感测的输出。

3. 发明申请

US20080272652A1 Virtual power rail modulation within an integrated circuit 有权
标题翻译：集成电路内的虚拟电源轨调制
公开(公告)号：US20080272652A1
公开(公告)日：2008-11-06
申请号：US11797497
申请日：2007-05-03
申请人： Sachin Satish Idgunji , David Walter Flynn , Robert Campbell Aitken
发明人： Sachin Satish Idgunji , David Walter Flynn , Robert Campbell Aitken
IPC分类号： H02J1/00
CPC分类号： H03K19/0016 , H03K19/096 , Y10T307/461
摘要： An integrated circuit 2 is provided with logic blocks 16 which draw their power from virtual supply rails 8, 10. These virtual supply rails 8, 10 are connected by switch blocks 12, 14 to main supply rails 4, 6. The switch blocks 12, 14 are subject to modulation to maintain the virtual supply rails 8, 10 at an intermediate voltage level such that a reduced voltage difference is applied across the logic block 16. This intermediate voltage level is used in a state retention mode in which the clock signal clk to the logic block 16 is stopped and state signal values are maintained therein using this reduced virtual power rail derived voltage difference. When it is desired to resume processing then the full virtual rail voltages are restored by rendering the switch blocks 12, 14 fully conductive and then the clock is restarted. The switch blocks 12, 14 which are modulated by controllers 18 which use feedback control based upon the sensed virtual rail voltages (VVdd and VVgnd) while drawing their own power from the normal supply rails (VVdd and gnd).
摘要翻译：集成电路2设置有从虚拟电源轨8,10吸取电力的逻辑块16.这些虚拟电源轨8,10由开关块12,14连接到主电源轨4,6。 14进行调制以将虚拟电源轨8,10保持在中间电压电平，使得在逻辑块16上施加减小的电压差。该中间电压电平用于状态保持模式，其中时钟信号clk 停止逻辑块16，并且使用该减小的虚拟功率轨导出电压差来维持状态信号值。当希望恢复处理时，通过使开关块12,14完全导通然后再启动时钟来恢复完整的虚拟轨电压。开关块12,14由控制器18调制，控制器18使用基于感测的虚拟轨电压（VV）和反馈控制电压（VV）的反馈控制，同时从正常的电源轨（VV＆lt; dd＆gt;和＆lt; SUB＆gt;＆gt;）。

4. 发明授权

US07737720B2 Virtual power rail modulation within an integrated circuit 有权
标题翻译：集成电路内的虚拟电源轨调制
公开(公告)号：US07737720B2
公开(公告)日：2010-06-15
申请号：US11797497
申请日：2007-05-03
申请人： Sachin Satish Idgunji , David Walter Flynn , Robert Campbell Aitken
发明人： Sachin Satish Idgunji , David Walter Flynn , Robert Campbell Aitken
IPC分类号： H03K19/003
CPC分类号： H03K19/0016 , H03K19/096 , Y10T307/461
摘要： An integrated circuit is provided with logic blocks which draw their power from virtual supply rails. These virtual supply rails are connected by switch blocks to main supply rails. The switch blocks are subject to modulation to maintain the virtual supply rails at an intermediate voltage level such that a reduced voltage difference is applied across the logic block. This intermediate voltage level is used in a state retention mode in which the clock signal clk to the logic block is stopped and state signal values are maintained therein using this reduced virtual power rail derived voltage difference. When it is desired to resume processing then the full virtual rail voltages are restored by rendering the switch blocks fully conductive and then the clock is restarted. The switch blocks which are modulated by controllers which use feedback control based upon the sensed virtual rail voltages (VVdd and Vgnd) while drawing their own power from the normal supply rails (Vdd and gnd).
摘要翻译：集成电路提供有从虚拟电源轨道吸取功率的逻辑块。这些虚拟电源轨由开关块连接到主电源轨。开关块经受调制以将虚拟电源轨保持在中间电压电平，使得在逻辑块上施加减小的电压差。该中间电压电平用于停止逻辑块的时钟信号clk的状态保持模式，并且使用该减小的虚拟电力轨道导出的电压差来保持状态信号值。当希望恢复处理时，通过使开关块完全导通然后重新启动时钟来恢复完整的虚拟轨电压。所述开关块由控制器调制，所述控制器使用基于感测的虚拟轨电压（VVdd和Vgnd）的反馈控制，同时从正常供电轨（Vdd和gnd）吸取其自身功率。

5. 发明授权

US08330478B2 Operating parameter monitoring circuit and method 有权
标题翻译：操作参数监控电路及方法
公开(公告)号：US08330478B2
公开(公告)日：2012-12-11
申请号：US12588963
申请日：2009-11-03
申请人： James Edward Myers , David Walter Flynn , Sachin Satish Idgunji , Gregory Munson Yeric
发明人： James Edward Myers , David Walter Flynn , Sachin Satish Idgunji , Gregory Munson Yeric
IPC分类号： G01R31/3187 , G01R31/26
CPC分类号： H03K3/0315 , G01R31/2621
摘要： A monitoring circuit 14, 16, 18, 20, 22 for monitoring an operating parameter of an integrated circuit 2 comprises a ring oscillator circuit 80 comprising a plurality of serially connected inverting stages 82-1, 82-2, 82-3. At least one of the inverting stages 82-1, 82-2 comprises at least one leakage transistor 64-1, 64-2 which is configured to operate in a leakage mode in which substantially all current through the at least one leakage transistor is a leakage current, and a capacitive element 70-1 arranged to be charged or discharged in dependence on the leakage current. The ring oscillator circuit 80 thus generates an oscillating signal with an oscillation period dependent on a rate at which the capacitive element 70-1 is charged or discharged. The operating parameter controls a magnitude of the leakage current so that the oscillation period indicates the operating parameter.
摘要翻译：用于监视集成电路2的工作参数的监视电路14,16,18,20,22包括环形振荡器电路80，其包括多个串联的反相级82-1,82-2,82-3。反相级82-1,82-2中的至少一个包括至少一个泄漏晶体管64-1,64-2，泄漏晶体管64-1,64-2被配置为在泄漏模式下工作，其中基本上通过至少一个泄漏晶体管的电流为泄漏电流以及根据泄漏电流被布置成被充电或放电的电容元件70-1。因此，环形振荡器电路80产生具有取决于电容元件70-1被充电或放电的速率的振荡周期的振荡信号。操作参数控制漏电流的大小，使振荡周期表示运行参数。

6. 发明授权

US07977822B2 Dynamically changing control of sequenced power gating 有权
标题翻译：动态变化控制顺序电源门控
公开(公告)号：US07977822B2
公开(公告)日：2011-07-12
申请号：US11979542
申请日：2007-11-05
申请人： David Walter Flynn , Sachin Satish Idgunji
发明人： David Walter Flynn , Sachin Satish Idgunji
IPC分类号： H01H31/00 , H01H33/59 , H01H47/00 , H01H85/46 , H01H19/14
CPC分类号： H03K19/0016 , Y10T307/484 , Y10T307/702 , Y10T307/76 , Y10T307/924 , Y10T307/931
摘要： Power control circuitry for controlling connection of a voltage source to a switched power rail powering an associated circuit is provided. A plurality of switch blocks are connected in parallel between the switched power rail and the voltage source, each switch block being controlled by an enable signal provided by a switch controller. The switch controller performs a turn-on sequence providing a series of enable signal patterns to the switch blocks. The switch controller applies a time varying generation operation to at least one sequence stage of a predetermined turn-on sequence to produce a corresponding enable signal pattern for that sequence stage. When the turn-on sequence is later repeated, the enable signal pattern produced for at least one of the sequence stages differs from the enable signal pattern previously produced for that sequence stage.
摘要翻译：提供了用于控制电压源连接到为相关电路供电的开关电源轨的电源控制电路。多个开关块并联连接在开关电源轨和电压源之间，每个开关块由开关控制器提供的使能信号控制。开关控制器执行向开关块提供一系列使能信号模式的导通序列。开关控制器将时变生成操作应用于预定导通序列的至少一个序列级，以产生用于该序列级的对应的使能信号模式。当稍后重复接通序列时，针对至少一个序列级产生的使能信号模式与先前为该序列级产生的使能信号模式不同。

7. 发明申请

US20110101998A1 Operating parameter monitoring circuit and method 有权
标题翻译：操作参数监控电路及方法
公开(公告)号：US20110101998A1
公开(公告)日：2011-05-05
申请号：US12588963
申请日：2009-11-03
申请人： James Edward Myers , David Walter Flynn , Sachin Satish Idgunji , Gregory Munson Yeric
发明人： James Edward Myers , David Walter Flynn , Sachin Satish Idgunji , Gregory Munson Yeric
IPC分类号： G01R27/26
CPC分类号： H03K3/0315 , G01R31/2621
摘要： A monitoring circuit 14, 16, 18, 20, 22 for monitoring an operating parameter of an integrated circuit 2 comprises a ring oscillator circuit 80 comprising a plurality of serially connected inverting stages 82-1, 82-2, 82-3.At least one of the inverting stages 82-1, 82-2 comprises at least one leakage transistor 64-1, 64-2 which is configured to operate in a leakage mode in which substantially all current through the at least one leakage transistor is a leakage current, and a capacitive element 70-1 arranged to be charged or discharged in dependence on the leakage current. The ring oscillator circuit 80 thus generates an oscillating signal with an oscillation period dependent on a rate at which the capacitive element 70-1 is charged or discharged. The operating parameter controls a magnitude of the leakage current so that the oscillation period indicates the operating parameter.
摘要翻译：用于监视集成电路2的工作参数的监视电路14,16,18,20,22包括环形振荡器电路80，其包括多个串联的反相级82-1,82-2,82,33。至少反相级82-1,82-2中的一个包括至少一个泄漏晶体管64-1,64-2，漏泄晶体管64-1,64-2被配置为在泄漏模式下工作，其中基本上通过至少一个泄漏晶体管的所有电流为泄漏电流以及电容元件70-1，其被配置成根据漏电流进行充放电。因此，环形振荡器电路80产生具有取决于电容元件70-1被充电或放电的速率的振荡周期的振荡信号。操作参数控制漏电流的大小，使振荡周期表示运行参数。

8. 发明申请

US20090115258A1 Power control circuitry, circuitry for analysing a switched power rail, and method of controlling connection of a power source to a switched power rail 有权
标题翻译：功率控制电路，用于分析开关电源轨的电路以及控制电源与切换的电源轨的连接的方法
公开(公告)号：US20090115258A1
公开(公告)日：2009-05-07
申请号：US11979541
申请日：2007-11-05
申请人： David Walter Flynn , Leah Elizabeth Schuth , Sachin Satish Idgunji
发明人： David Walter Flynn , Leah Elizabeth Schuth , Sachin Satish Idgunji
IPC分类号： H01H47/20
CPC分类号： H02M3/156 , H03K3/0315 , H03K19/0016 , Y10T307/852
摘要： Power control circuitry is provided for controlling connection of a power source having a source voltage level to a switched power rail to provide power to an associated circuit block. The power control circuitry comprises a switch block for selectively connecting the switched power rail to the power source, and a switch controller for controlling operation of the switch block. A ring oscillator circuit is powered from the switched power rail and produces an oscillating output signal, and analysis circuitry is then used to analyse change in frequency of the oscillating output signal produced by the ring oscillator circuit during a period of time when the switched power rail is not at the source voltage level. The switch controller is then arranged to control at least one aspect of the operation of the switch block in dependence on the analysis. This technique provides a simple and effective digital technique for observing voltage changes on the switched power rail.
摘要翻译：提供功率控制电路用于控制具有源电压电平的电源与切换的电源轨的连接，以向相关的电路块提供电力。功率控制电路包括用于选择性地将切换的电源轨连接到电源的开关块和用于控制开关块的操作的开关控制器。环形振荡器电路由切换的电源轨供电并产生振荡输出信号，然后分析电路用于分析由环形振荡器电路产生的振荡输出信号的频率在切换的电源轨不在源电压电平。开关控制器然后被布置成根据分析来控制开关块的操作的至少一个方面。该技术提供了一种简单有效的数字技术，用于观察开关式电源轨上的电压变化。

9. 发明授权

US08615687B2 Data processing system and method for regulating a voltage supply to functional circuitry of the data processing system 有权
标题翻译：用于调节对数据处理系统的功能电路的电压供应的数据处理系统和方法
公开(公告)号：US08615687B2
公开(公告)日：2013-12-24
申请号：US12929237
申请日：2011-01-10
申请人： Bal S Sandhu , Sachin Satish Idgunji , David Walter Flynn
发明人： Bal S Sandhu , Sachin Satish Idgunji , David Walter Flynn
IPC分类号： G06F11/00 , G01R31/28
CPC分类号： G06F1/3296 , G06F1/324 , Y02D10/126 , Y02D10/172
摘要： A data processing system and method for regulating a voltage supply to functional circuitry configured to operate from a variable voltage supply, the functional circuitry having at least one error correction circuit configured to detect and repair errors in operation of the functional circuitry. Voltage regulator circuitry provides the voltage supply to the functional circuitry, and modifies the voltage level of the voltage supply based on a feedback control signal. Error rate history circuitry receives error indications from the error correction circuit during operation of the functional circuitry and generates error rate history information therefrom. An adaptive controller then generates the feedback control signal in dependence on the error rate history information such that the adaptive controller adjusts the feedback control signal over time having regard to the error rate history information in order to obtain a predetermined target non-zero error rate within the functional circuitry.
摘要翻译：一种数据处理系统和方法，用于调节被配置为从可变电压源操作的功能电路的电压供应，所述功能电路具有被配置为检测和修复功能电路操作中的错误的至少一个误差校正电路。电压调节器电路为功能电路提供电压，并且基于反馈控制信号修改电压源的电压电平。误差率历史电路在功能电路的操作期间从错误校正电路接收错误指示，并从中产生错误率历史信息。然后，自适应控制器根据错误率历史信息产生反馈控制信号，使得自适应控制器在考虑到错误率历史信息后随时间调整反馈控制信号，以便在内部获得预定的目标非零错误率功能电路。

10. 发明申请

US20120303986A1 Verifying state integrity in state retention circuits 有权
标题翻译：验证状态保持电路中的状态完整性
公开(公告)号：US20120303986A1
公开(公告)日：2012-11-29
申请号：US13067396
申请日：2011-05-27
申请人： David Walter Flynn , Sachin Satish Idgunji
发明人： David Walter Flynn , Sachin Satish Idgunji
IPC分类号： G06F12/16 , G06F1/32
CPC分类号： G01R31/318541 , G01R31/318544 , G06F11/10
摘要： A data processing apparatus is provided comprising data processing circuitry configured to perform data processing operations. A plurality of state retention circuits forms part of the data processing circuitry and these circuits are configured to hold respective state values at respective nodes of the data processing circuitry it enters a low power mode. One or more scan paths connect the plurality of state retention circuits together in series, such that the state values may be scanned into and out of the respective nodes. A plurality of parity information generation elements are coupled to the scan path(s) and configured to generate parity information indicative of the respective state values held at those respective nodes by the state retention circuits. The plurality of parity information generation elements are arranged to provide one or more parity path(s), such that an output parity value generated at an output of the parity path will invert if one of said respective state values changes, providing an external indication of the integrity of the state values held by the state retention circuits.
摘要翻译：提供了一种数据处理装置，包括被配置为执行数据处理操作的数据处理电路。多个状态保持电路形成数据处理电路的一部分，并且这些电路被配置为保持其进入低功率模式的数据处理电路的各个节点处的各自的状态值。一个或多个扫描路径将多个状态保持电路串联在一起，使得可以将状态值扫描进出各个节点。多个奇偶校验信息生成元件耦合到扫描路径，并被配置为通过状态保持电路产生指示保持在那些相应节点处的各个状态值的奇偶校验信息。多个奇偶信息产生元件被布置成提供一个或多个奇偶校验路径，使得如果所述各个状态值之一改变，则在奇偶校验路径的输出处产生的输出奇偶校验值将反转，提供外部指示国家保留电路所持有的状态值的完整性。

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