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1. 发明授权

US10540277B2 Method and apparatus for supporting the use of interleaved memory regions 有权
公开(公告)号：US10540277B2
公开(公告)日：2020-01-21
申请号：US15026586
申请日：2014-10-15
申请人： STMICROELECTRONICS (GRENOBLE 2) SAS , STMICROELECTRONICS S.R.L.
发明人： Michael Soulie , Riccardo Locatelli , Valerio Catalano , Giuseppe Maruccia , Giuseppe Guarnaccia , Raffaele Guarrasi
IPC分类号： G06F12/06 , G06F15/78 , G06F17/50
摘要： A method comprising: receiving a transaction associated with an address and having a transaction destination, said address being in an interleaved region of a memory; determining one of a plurality of destinations for said transaction, different parts of said interleaved memory region being respectively accessible by said plurality of destinations; and associating routing information to said transaction, said routing information associated with the determined destination.

2. 发明申请

US20160226878A1 METHOD AND APPARATUS FOR USE WITH DIFFERENT MEMORY MAPS 审中-公开
标题翻译：使用不同存储器的方法和装置
公开(公告)号：US20160226878A1
公开(公告)日：2016-08-04
申请号：US15026588
申请日：2014-10-17
申请人： STMicroelectronics SA , STMicroelectronics (Grenoble2) SAS , STMicroelectronics S.r.l.
发明人： Michael Soulie , Riccardo Locatelli , Valerio Catalano , Hajer Ferjani , Giuseppe Maruccia , Raffaele Guarrasi , Giuseppe Guarnaccia
IPC分类号： H04L29/06
摘要： An apparatus has a data store configured to store access activity information. The access activity information indicates which one or more of a plurality of different access parameter sets is active. The data store is also configured to store access defining information, which defines, at least for each active access parameter set, a number of channels, location information of said channels, and interleaving information associated with said channels.
摘要翻译：一种装置具有被配置为存储访问活动信息的数据存储。访问活动信息指示多个不同访问参数集中的哪一个或多个是活动的。数据存储还被配置为存储访问定义信息，其至少为每个活动的访问参数集定义多个信道，所述信道的位置信息和与所述信道相关联的交织信息。

3. 发明授权

US11456857B2 Cryptography method and circuit, corresponding device 有权
公开(公告)号：US11456857B2
公开(公告)日：2022-09-27
申请号：US16433847
申请日：2019-06-06
申请人： STMicroelectronics S.r.l.
发明人： Rosalino Critelli , Giuseppe Guarnaccia
IPC分类号： H04L9/06 , G06F13/16 , G06F21/60 , H04L9/14
摘要： A cryptographic method includes providing memory locations for storing encrypted data. The memory locations have respective addresses and are accessible via a communication bus. The method includes receiving over the communication bus access requests to the memory locations, wherein the access requests include burst requests for access to respective sets of the memory locations starting from respective start addresses, and calculating as a function of the start addresses encryption/decryption cryptographic masks based on cryptographic keys. Plain text data is received for encryption and the method includes applying the cryptographic masks to the plain text data to obtain therefrom encrypted data, and including the encrypted data into output data for transmission over the communication bus.

4. 发明授权

US11042655B2 Decryption method and circuit, corresponding device 有权
公开(公告)号：US11042655B2
公开(公告)日：2021-06-22
申请号：US16296009
申请日：2019-03-07
申请人： STMICROELECTRONICS S.R.L.
发明人： Giuseppe Guarnaccia , Rosalino Critelli
IPC分类号： G06F21/00 , G06F21/60 , G06F21/62 , G06F21/85 , H04L9/06 , G06F21/74
摘要： A method for data decryption comprises receiving, over an AXI bus operating in burst mode, data access requests for data units stored in a memory, subdividing the requests received into requests for encrypted data units and requests for non-encrypted data units, forwarding both requests for encrypted data units and requests for non-encrypted data units towards the memory, retrieving the respective sets of data units over the AXI bus, and applying Advanced Encryption Standard, AES, processing to the requests for encrypted data units by calculating decryption masks for the encrypted data units and applying the decryption masks calculated to the encrypted data units retrieved. Subdividing the requests into requests for encrypted data units and requests for non-encrypted data units is performed depending on data start addresses and security information conveyed by the requests.

5. 发明授权

US10635394B2 Binary-to-gray conversion circuit, related FIFO memory, integrated circuit and method 有权
公开(公告)号：US10635394B2
公开(公告)日：2020-04-28
申请号：US16256449
申请日：2019-01-24
申请人： STMicroelectronics S.r.l.
发明人： Salvatore Marco Rosselli , Giuseppe Guarnaccia
IPC分类号： G06F5/14 , G06F13/42 , G06F5/06 , G11C7/22 , H03M7/16 , G11C7/10
CPC分类号： G06F5/14 , G06F5/06 , G06F13/4243 , G11C7/222 , H03M7/16 , G06F2205/102 , G06F2205/106 , G11C7/1018
摘要： A circuit and method for performing a Binary-to-Gray conversion are disclosed. A first binary signal represents a target value and a second binary signal is stored in a register. A set of binary candidate values are determined where the respective Gray equivalent of each binary candidate value has a Hamming distance of one from the Gray equivalent of the second binary value. One of the binary candidate values is selected as a function of the first binary signal and the second binary signal. The selected binary candidate value is provided at input to the register. An encoded signal is generated by determining the Gray encoded equivalent of the selected binary candidate value.

6. 发明申请

US20150109916A1 METHOD AND APPARATUS FOR SUPPORTING REPROGRAMMING OR RECONFIGURING 有权
标题翻译：支持复制或重新配置的方法和装置
公开(公告)号：US20150109916A1
公开(公告)日：2015-04-23
申请号：US14516300
申请日：2014-10-16
申请人： STMicroelectronics (Grenoble 2) SAS , STMicroelectronics S.r.l.
发明人： Riccardo Locatelli , Michael Soulie , Francesco Giotta , Raffaele Guarrasi , Giuseppe Guarnaccia
IPC分类号： H04L12/24 , H04L12/933 , H04L12/851
CPC分类号： H04L49/109 , G06F15/17312 , H04L47/24
摘要： A method includes setting a first indicator to a first value, which causes an apparatus to stop receiving traffic from a traffic source. At least one register is accessed to read or write at least one new value, and a second indicator is set indicating that accessing of the at least one register has completed. The first indicator is set to a second value. When the first indicator has the second value and the second indicator is set, the apparatus is again allowed to receive traffic from the traffic source.
摘要翻译：一种方法包括将第一指示符设置为第一值，这使得设备停止从业务源接收业务。访问至少一个寄存器以读取或写入至少一个新值，并且设置指示至少一个寄存器的访问已经完成的第二指示符。第一个指示器被设置为第二个值。当第一指示符具有第二值并且第二指示符被设置时，再次允许该装置从业务源接收业务。

7. 发明公开

US20230409320A1 ONE-TIME PROGRAMMABLE MEMORY CONTROLLER, RELATED PROCESSING SYSTEM, INTEGRATED CIRCUIT AND METHOD 审中-公开
公开(公告)号：US20230409320A1
公开(公告)日：2023-12-21
申请号：US18325519
申请日：2023-05-30
申请人： STMicroelectronics S.r.l.
发明人： Antonino Giuseppe Fontana , Giuseppe Guarnaccia , Stefano Catalano
IPC分类号： G06F9/30
CPC分类号： G06F9/3004 , G06F9/30116 , G06F9/30189
摘要： In an embodiment a One-Time Programmable (OTP) memory controller includes a data register, a given number K of shadow-registers, wherein the number K is smaller than a given number N of memory slots of an OTP memory area, a communication interface configured to receive a read request requesting the data of a given memory slot and a control circuit configured to receive a preload start signal and a shadow-register preload enable signal, wherein the control circuit is configured to manage a preload phase and a data-read phase.

8. 发明申请

US20190386816A1 CRYPTOGRAPHY METHOD AND CIRCUIT, CORRESPONDING DEVICE 审中-公开
公开(公告)号：US20190386816A1
公开(公告)日：2019-12-19
申请号：US16433847
申请日：2019-06-06
申请人： STMicroelectronics S.r.l.
发明人： Rosalino Critelli , Giuseppe Guarnaccia
IPC分类号： H04L9/06 , G06F21/60 , H04L9/14 , G06F13/16
摘要： A cryptographic method includes providing memory locations for storing encrypted data. The memory locations have respective addresses and are accessible via a communication bus. The method includes receiving over the communication bus access requests to the memory locations, wherein the access requests include burst requests for access to respective sets of the memory locations starting from respective start addresses, and calculating as a function of the start addresses encryption/decryption cryptographic masks based on cryptographic keys. Plain text data is received for encryption and the method includes applying the cryptographic masks to the plain text data to obtain therefrom encrypted data, and including the encrypted data into output data for transmission over the communication bus.

9. 发明授权

US09727306B2 Bi-synchronous electronic device with burst indicator and related methods 有权
公开(公告)号：US09727306B2
公开(公告)日：2017-08-08
申请号：US14508126
申请日：2014-10-07
申请人： STMICROELECTRONICS S.r.l.
发明人： Giuseppe Guarnaccia , Salvatore Marco Rosselli
IPC分类号： G06F5/10
CPC分类号： G06F5/10 , G06F2205/102 , G06F2205/106
摘要： A bi-synchronous electronic device may include a FIFO memory circuit configured to store data, and a first digital circuit coupled to the FIFO memory circuit and configured to operate based upon a first clock signal and a write pointer, write a data burst to the FIFO memory circuit, thereby causing a jump in the write pointer to a new position, and write a burst indicator associated with the new position in the FIFO memory circuit. The bi-synchronous electronic device may include a second digital circuit coupled to the FIFO memory circuit and configured to operate based upon a second clock signal different from the first clock signal, read from the FIFO memory circuit based upon a read pointer, and synchronize the read pointer to the write pointer based upon the burst indicator.

10. 发明授权

US09311975B1 Bi-synchronous electronic device and FIFO memory circuit with jump candidates and related methods 有权
标题翻译：双同步电子设备和具有跳转候选和FIFO相关方法的FIFO存储器电路
公开(公告)号：US09311975B1
公开(公告)日：2016-04-12
申请号：US14508321
申请日：2014-10-07
申请人： STMICROELECTRONICS S.r.l.
发明人： Salvatore Marco Rosselli , Giuseppe Guarnaccia , Ugo Mari
IPC分类号： G11C7/22 , G06F5/06
CPC分类号： G11C7/222 , G06F5/06 , G06F5/10 , G06F2205/102
摘要： A bi-synchronous electronic device may include a FIFO memory circuit, and a first digital circuit coupled to the FIFO memory circuit and configured to operate based upon a first clock signal, and write to the FIFO memory circuit based upon a write pointer. The bi-synchronous electronic device may include second digital circuit coupled to the FIFO memory circuit and configured to operate based upon a second clock signal different from the first clock signal, and read from the FIFO memory circuit based upon a read pointer. The FIFO memory circuit may be configured to detect a jump in the write pointer to a new position, determine jump candidates for the read pointer from a current position, select a jump candidate, and synchronize the read pointer based upon the selected jump candidate.
摘要翻译：双同步电子设备可以包括FIFO存储器电路和耦合到FIFO存储器电路并被配置为基于第一时钟信号进行操作的第一数字电路，并且基于写指针写入FIFO存储器电路。双同步电子设备可以包括耦合到FIFO存储器电路并被配置为基于与第一时钟信号不同的第二时钟信号进行操作的第二数字电路，并且基于读指针从FIFO存储器电路读取。 FIFO存储器电路可以被配置为检测写指针中的跳转到新位置，从当前位置确定读指针的跳转候选，选择跳转候选，并且基于所选择的跳转候选来同步读指针。

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