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1. 发明申请

US20150109916A1 METHOD AND APPARATUS FOR SUPPORTING REPROGRAMMING OR RECONFIGURING 有权
标题翻译：支持复制或重新配置的方法和装置
公开(公告)号：US20150109916A1
公开(公告)日：2015-04-23
申请号：US14516300
申请日：2014-10-16
申请人： STMicroelectronics (Grenoble 2) SAS , STMicroelectronics S.r.l.
发明人： Riccardo Locatelli , Michael Soulie , Francesco Giotta , Raffaele Guarrasi , Giuseppe Guarnaccia
IPC分类号： H04L12/24 , H04L12/933 , H04L12/851
CPC分类号： H04L49/109 , G06F15/17312 , H04L47/24
摘要： A method includes setting a first indicator to a first value, which causes an apparatus to stop receiving traffic from a traffic source. At least one register is accessed to read or write at least one new value, and a second indicator is set indicating that accessing of the at least one register has completed. The first indicator is set to a second value. When the first indicator has the second value and the second indicator is set, the apparatus is again allowed to receive traffic from the traffic source.
摘要翻译：一种方法包括将第一指示符设置为第一值，这使得设备停止从业务源接收业务。访问至少一个寄存器以读取或写入至少一个新值，并且设置指示至少一个寄存器的访问已经完成的第二指示符。第一个指示器被设置为第二个值。当第一指示符具有第二值并且第二指示符被设置时，再次允许该装置从业务源接收业务。

2. 发明授权

US10540277B2 Method and apparatus for supporting the use of interleaved memory regions 有权
公开(公告)号：US10540277B2
公开(公告)日：2020-01-21
申请号：US15026586
申请日：2014-10-15
申请人： STMICROELECTRONICS (GRENOBLE 2) SAS , STMICROELECTRONICS S.R.L.
发明人： Michael Soulie , Riccardo Locatelli , Valerio Catalano , Giuseppe Maruccia , Giuseppe Guarnaccia , Raffaele Guarrasi
IPC分类号： G06F12/06 , G06F15/78 , G06F17/50
摘要： A method comprising: receiving a transaction associated with an address and having a transaction destination, said address being in an interleaved region of a memory; determining one of a plurality of destinations for said transaction, different parts of said interleaved memory region being respectively accessible by said plurality of destinations; and associating routing information to said transaction, said routing information associated with the determined destination.

3. 发明授权

US10419432B2 Method and apparatus for use with different memory maps 有权
公开(公告)号：US10419432B2
公开(公告)日：2019-09-17
申请号：US15026588
申请日：2014-10-17
申请人： STMICROELECTRONICS SA , STMICROELECTRONICS (GRENOBLE 2) SAS , STMICROELECTRONICS S.R.L.
发明人： Michael Soulie , Riccardo Locatelli , Valerio Catalano , Hajer Ferjani , Giuseppe Maruccia , Raffaele Guarrasi , Giuseppe Guarnaccia
IPC分类号： H04L29/06 , G06F12/08 , G06F12/06
摘要： An apparatus has a data store configured to store access activity information. The access activity information indicates which one or more of a plurality of different access parameter sets is active. The data store is also configured to store access defining information, which defines, at least for each active access parameter set, a number of channels, location information of said channels, and interleaving information associated with said channels.

4. 发明授权

US09660936B2 Method and apparatus for supporting reprogramming or reconfiguring 有权
公开(公告)号：US09660936B2
公开(公告)日：2017-05-23
申请号：US14516300
申请日：2014-10-16
申请人： STMicroelectronics (Grenoble 2) SAS , STMicroelectronics S.r.l.
发明人： Riccardo Locatelli , Michael Soulie , Francesco Giotta , Raffaele Guarrasi , Giuseppe Guarnaccia
IPC分类号： G06F17/30 , H04L12/933 , G06F15/173 , H04L12/851
CPC分类号： H04L49/109 , G06F15/17312 , H04L47/24
摘要： A method includes setting a first indicator to a first value, which causes an apparatus to stop receiving traffic from a traffic source. At least one register is accessed to read or write at least one new value, and a second indicator is set indicating that accessing of the at least one register has completed. The first indicator is set to a second value. When the first indicator has the second value and the second indicator is set, the apparatus is again allowed to receive traffic from the traffic source.

5. 发明申请

US20130136129A1 ZERO-CYCLE ROUTER FOR NETWORKS ON-CHIP 有权
标题翻译：用于网络芯片的零周期路由器
公开(公告)号：US20130136129A1
公开(公告)日：2013-05-30
申请号：US13673505
申请日：2012-11-09
申请人： STMicroelectronics (Grenoble 2) SAS
发明人： Riccardo Locatelli , Esa Petri , Antonio-Marcello Coppolla , Luca Fanucci , Sergio Saponara , Tony Bacchillone
IPC分类号： H04L12/56
CPC分类号： H04L45/74 , H04L45/34 , H04L45/58 , H04L45/60 , H04L49/109 , H04L49/70
摘要： A router includes a plurality of virtual networks, a plurality of output links, at least one decoder and arbitration circuitry. Each virtual network has a plurality of virtual network inputs and a plurality of virtual network outputs. Each virtual network output is associated with an output link. The decoder decodes a header of a data unit received on a virtual network of one of the virtual network inputs. The decoder generates a first request and a second request. The first request is for the allocation of a virtual network output of the virtual network to the virtual network input. The second request is for the allocation of an output link associated with the virtual network output to the virtual network output. The arbitration circuitry performs arbitration of the first request and arbitration of the second request in parallel.
摘要翻译：路由器包括多个虚拟网络，多个输出链路，至少一个解码器和仲裁电路。每个虚拟网络具有多个虚拟网络输入和多个虚拟网络输出。每个虚拟网络输出与输出链路相关联。解码器解码在虚拟网络输入之一的虚拟网络上接收的数据单元的报头。解码器产生第一请求和第二请求。第一个请求是将虚拟网络的虚拟网络输出分配给虚拟网络输入。第二个请求是将与虚拟网络输出相关联的输出链路分配给虚拟网络输出。仲裁电路并行执行第一请求的仲裁和第二请求的仲裁。

6. 发明授权

US09461913B2 Method of data transmission in a system on chip 有权
标题翻译：片上系统中的数据传输方法
公开(公告)号：US09461913B2
公开(公告)日：2016-10-04
申请号：US13894093
申请日：2013-05-14
申请人： STMicroelectronics (Grenoble 2) SAS
发明人： Michael Soulie , Riccardo Locatelli , Antonio-Marcello Coppola
IPC分类号： H04L12/28 , H04L12/721 , G06F13/40
CPC分类号： H04L45/72 , G06F13/4018
摘要： Embodiments relate to a method for transmitting a message in a data path of a network, the method includes transmitting a message onto an input bus of an input interface module, the message being received in flits of a size corresponding to the width of the input bus and generating a validity indicator for each elementary flit constituting each flit received. The message is transmitted onto an output bus of the input interface module towards a receiving interface module in flits of a size corresponding to the width of the output bus along with each validity indicator generated in association with the corresponding elementary flit. The receiving interface module receives flits constituting the message and the associated validity indicators and rejects a received flit if an elementary flit of the received flit is associated with a validity indicator in the invalid state.
摘要翻译：实施例涉及一种用于在网络的数据路径中发送消息的方法，所述方法包括将消息发送到输入接口模块的输入总线上，所述消息以与输入总线的宽度对应的大小的flits接收以及生成构成接收到的每个飞行的每个基本飞行的有效性指示符。该消息被传送到输入接口模块的输出总线上，朝向与输出总线的宽度对应的大小的接收接口模块以及与相应的基本单元相关联地生成的每个有效性指示符。接收接口模块接收构成消息的闪烁和相关联的有效性指示符，并且如果接收到的飞行的基本故障与无效状态中的有效性指示符相关联，则拒绝接收的飞行。

7. 发明授权

US09306844B2 Zero-cycle router for networks on-chip 有权
标题翻译：用于片上网络的零周期路由器
公开(公告)号：US09306844B2
公开(公告)日：2016-04-05
申请号：US13673505
申请日：2012-11-09
申请人： STMicroelectronics (Grenoble 2) SAS
发明人： Riccardo Locatelli , Esa Petri , Antonio-Marcello Coppolla , Luca Fanucci , Sergio Saponara , Tony Bacchillone
IPC分类号： H04L12/28 , H04L12/741 , H04L12/775 , H04L12/931 , H04L12/933 , H04L12/721 , H04L12/773
CPC分类号： H04L45/74 , H04L45/34 , H04L45/58 , H04L45/60 , H04L49/109 , H04L49/70
摘要： A router includes a plurality of virtual networks, a plurality of output links, at least one decoder and arbitration circuitry. Each virtual network has a plurality of virtual network inputs and a plurality of virtual network outputs. Each virtual network output is associated with an output link. The decoder decodes a header of a data unit received on a virtual network of one of the virtual network inputs. The decoder generates a first request and a second request. The first request is for the allocation of a virtual network output of the virtual network to the virtual network input. The second request is for the allocation of an output link associated with the virtual network output to the virtual network output. The arbitration circuitry performs arbitration of the first request and arbitration of the second request in parallel.
摘要翻译：路由器包括多个虚拟网络，多个输出链路，至少一个解码器和仲裁电路。每个虚拟网络具有多个虚拟网络输入和多个虚拟网络输出。每个虚拟网络输出与输出链路相关联。解码器解码在虚拟网络输入之一的虚拟网络上接收的数据单元的报头。解码器产生第一请求和第二请求。第一个请求是将虚拟网络的虚拟网络输出分配给虚拟网络输入。第二个请求是将与虚拟网络输出相关联的输出链路分配给虚拟网络输出。仲裁电路并行执行第一请求的仲裁和第二请求的仲裁。

8. 发明申请

US20160226878A1 METHOD AND APPARATUS FOR USE WITH DIFFERENT MEMORY MAPS 审中-公开
标题翻译：使用不同存储器的方法和装置
公开(公告)号：US20160226878A1
公开(公告)日：2016-08-04
申请号：US15026588
申请日：2014-10-17
申请人： STMicroelectronics SA , STMicroelectronics (Grenoble2) SAS , STMicroelectronics S.r.l.
发明人： Michael Soulie , Riccardo Locatelli , Valerio Catalano , Hajer Ferjani , Giuseppe Maruccia , Raffaele Guarrasi , Giuseppe Guarnaccia
IPC分类号： H04L29/06
摘要： An apparatus has a data store configured to store access activity information. The access activity information indicates which one or more of a plurality of different access parameter sets is active. The data store is also configured to store access defining information, which defines, at least for each active access parameter set, a number of channels, location information of said channels, and interleaving information associated with said channels.
摘要翻译：一种装置具有被配置为存储访问活动信息的数据存储。访问活动信息指示多个不同访问参数集中的哪一个或多个是活动的。数据存储还被配置为存储访问定义信息，其至少为每个活动的访问参数集定义多个信道，所述信道的位置信息和与所述信道相关联的交织信息。

9. 发明申请

US20160246714A1 METHOD AND APPARATUS FOR SUPPORTING THE USE OF INTERLEAVED MEMORY REGIONS 审中-公开
标题翻译：支持使用独立存储区域的方法和装置
公开(公告)号：US20160246714A1
公开(公告)日：2016-08-25
申请号：US15026586
申请日：2014-10-15
申请人： STMICROELECTRONICS (GRENOBLE2) SAS , STMICROELECTRONICS S.R.L.
发明人： Michael Soulie , Riccardo Locatelli , Valerio Catalano , Giuseppe Maruccia , Giuseppe Guarnaccia , Raffaele Guarrasi
IPC分类号： G06F12/06 , G06F17/50 , G06F15/78
CPC分类号： G06F12/0607 , G06F13/1647 , G06F15/7825 , G06F17/5077 , G06F2212/656
摘要： A method comprising: receiving a transaction associated with an address and having a transaction destination, said address being in an interleaved region of a memory; determining one of a plurality of destinations for said transaction, different parts of said interleaved memory region being respectively accessible by said plurality of destinations; and associating routing information to said transaction, said routing information associated with the determined destination.
摘要翻译：一种方法，包括：接收与地址相关联并具有交易目的地的交易，所述地址在存储器的交织区域中; 确定所述交易的多个目的地中的一个，所述交织的存储器区域的不同部分可分别由所述多个目的地可访问; 以及将路由信息与所述事务相关联，所述路由信息与所确定的目的地相关联。

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