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1. 发明授权

US11742866B2 Method for up-converting clock signal, clock circuit and digital processing device 有权
公开(公告)号：US11742866B2
公开(公告)日：2023-08-29
申请号：US17621138
申请日：2021-06-22
申请人： SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD.
发明人： Jianbo Liu , Weibin Ma , Lihong Huang , Zuoxing Yang , Haifeng Guo
IPC分类号： H03D3/24 , H03L7/099 , H03L7/089 , H03L7/093
CPC分类号： H03L7/0992 , H03L7/089 , H03L7/093
摘要： The present disclosure relates to a method for up-converting a clock signal, a clock circuit and a digital processing device. More specifically, provided is a method for up-converting a clock signal, comprising: employing a first clock sub-circuit to provide a clock signal having a first frequency to a chip; receiving an instruction to up-convert the clock signal having the first frequency to a clock signal having a second frequency; in response to receiving the instruction, causing a second clock sub-circuit to output the clock signal having the second frequency; and after the second clock sub-circuit outputs the clock signal having the second frequency, employing the second clock sub-circuit to provide the clock signal having the second frequency to the chip in place of the first clock sub-circuit.

2. 发明授权

US11493981B1 Rapid frequency searching method and apparatus for data processing device, and data processing device 有权
公开(公告)号：US11493981B1
公开(公告)日：2022-11-08
申请号：US17606939
申请日：2021-07-23
申请人： SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD.
发明人： Weibin Ma , Hong Zhang , Lihong Huang , Zuoxing Yang , Haifeng Guo
IPC分类号： G06F1/324
摘要： The present disclosure discloses a rapid frequency searching method and apparatus for a data processing device, and a data processing device. The method includes: gradually raising a frequency of a computing chip from an initial frequency point to a target frequency through at least one first frequency point at an initial output voltage of a power source of the data processing device, wherein the duration when the computing chip is located at each of the at least one first frequency point is shorter than the duration when the computing chip is located at each of the at least one first frequency point in a routine frequency searching process; and after the computing chip achieves the target frequency, adjusting the output voltage of the power source of the data processing device and the frequency of the computing chip according to at least one output voltage value and at least one second frequency point in combination with test tasks delivered to the computing chip and feedback results from the computing chip to obtain a limit frequency of the computing chip and an output voltage, corresponding to the limit frequency, of the power source of the data processing device.

3. 发明授权

US12140991B2 Method for providing clock frequencies for computing cores, chip and data processing device 有权
公开(公告)号：US12140991B2
公开(公告)日：2024-11-12
申请号：US17911604
申请日：2021-04-12
申请人： SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD.
发明人： Jianbo Liu , Weibin Ma , Lihong Huang , Zuoxing Yang , Haifeng Guo
IPC分类号： G06F1/00 , G06F1/08
CPC分类号： G06F1/08
摘要： The present disclosure relates to a method for providing clock frequencies for computing cores, a chip and a data processing device. The method includes: causing a main clock frequency unit to provide a first main clock frequency for computing cores; testing the computing cores operating at the first main clock frequency to determine whether a pass rate of the computing cores is greater than an upper threshold or less than a lower threshold; when the pass rate is less than the lower threshold, causing an auxiliary clock frequency unit to provide a lower first auxiliary clock frequency for computing cores abnormally operating, causing the main clock frequency unit to providing the first main clock frequency for the remaining computing cores; when the pass rate is greater than the upper threshold, causing the main clock frequency unit to provide a higher second main clock frequency for the computing cores.

4. 发明授权

US12113537B1 Pipeline clock driving circuit, computing chip, hashboard, and computing device 有权
公开(公告)号：US12113537B1
公开(公告)日：2024-10-08
申请号：US18704562
申请日：2024-01-12
申请人： SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD.
发明人： Nan Li , Haifeng Guo , Zhijun Fan , Lianhua Duan
IPC分类号： H03K5/00 , H03K3/027 , H03K5/13 , H03K5/15
CPC分类号： H03K5/1508 , H03K3/027 , H03K5/13 , H03K5/15
摘要： The present disclosure relates to a pipeline clock driving circuit, a computing chip, a hashboard, and a computing device. Disclosed is a pipeline clock driving circuit, configured to provide a pulse clock signal to a pipeline, including: a plurality of stages of clock driving circuits, each stage being configured to provide the pulse clock signal to a corresponding operation stage of the pipeline; a clock source, coupled to an input of a first-stage clock driving circuit, each stage of the clock driving circuits including: a trigger, coupled to an input of a current-stage clock driving circuit; a delay module, including a first delay sub-module, the first delay sub-module delaying a pulse signal output by the trigger and feeding a delayed pulse signal back to the trigger as a feedback pulse signal; and a combinational logic module, performing a combinational logic operation on the pulse signal and the feedback pulse signal to generate the pulse clock signal to be provided to a corresponding operation stage, where the delay module further includes a second delay sub-module, and the second delay sub-module delays the pulse signal and outputs the delayed pulse signal to a next-stage clock driving circuit.

5. 发明授权

US12124855B2 Training method for parameter configuration model, parameter configuration method, and parameter configuration device 有权
公开(公告)号：US12124855B2
公开(公告)日：2024-10-22
申请号：US18692643
申请日：2022-09-15
申请人： SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD.
发明人： Guo Ai , Haifeng Guo , Zuoxing Yang
IPC分类号： G06F1/24 , G06F9/4401 , G06F8/65
CPC分类号： G06F9/4401 , G06F8/65
摘要： The present disclosure relates to a training method for a parameter configuration model, a parameter configuration method, and a parameter configuration device. The training method includes: obtaining a training sample set of a data processing device, wherein the training sample set includes operation parameters and benefit parameters in one-to-one correspondence with the operation parameters, the operation parameter includes at least one of a global operation parameter or a local operation parameter associated with position distribution, the benefit parameter is configured to reflect a ratio of power consumption to computing power of the data processing device; training the parameter configuration model based on the training sample set, wherein the operation parameter is configured as an input of the parameter configuration model, and the benefit parameter is configured as an output of the parameter configuration model; and in a case that a training accuracy of the parameter configuration model is greater than or equal to a first preset accuracy, ending the training and obtaining a trained parameter configuration model.

6. 发明授权

US12093099B2 Method and apparatus for controlling voltage of power supply of data processing device, data processing device, and storage medium 有权
公开(公告)号：US12093099B2
公开(公告)日：2024-09-17
申请号：US17997316
申请日：2021-05-19
申请人： SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD.
发明人： Weibin Ma , Lihong Huang , Yuefeng Wu , Haifeng Guo , Zuoxing Yang
IPC分类号： G06F1/26
CPC分类号： G06F1/266
摘要： Implementations of this application provide a method and an apparatus for controlling a voltage of a power supply of a data processing device and a data processing device. The method includes: determining a computing power ratio of the data processing device based on an actual computing power and a theoretical computing power of the data processing device; generating a power supply control instruction based on a result of comparison between the computing power ratio and a predetermined threshold; and controlling an output voltage of the power supply of the data processing device based on the power supply control instruction. According to the implementations of this application, the output voltage of the power supply is controlled according to the computing power ratio, and a good compromise can be obtained between the power consumption loss and the computing power of the data processing device.

7. 发明授权

US11340646B1 Mining machine power adjustment method 有权
公开(公告)号：US11340646B1
公开(公告)日：2022-05-24
申请号：US17434376
申请日：2021-05-07
申请人： Shenzhen MicroBT Electronics Technology Co., Ltd.
发明人： Lihong Huang , Weibin Ma , Zuoxing Yang , Yuefeng Wu , Haifeng Guo
IPC分类号： G06F1/00 , G05F1/67 , G06F1/3296 , G06F1/324
摘要： Disclosed is a mining machine power adjusting method, including: when a mining machine is in a working stage, collecting an input voltage of the mining machine; adjusting a maximum working power of the mining machine to a first power value by controlling a working frequency and an output voltage of the mining machine when the input voltage is lower than a pre-determined voltage threshold; and adjusting the maximum working power to a second power value by controlling the working frequency and the output voltage of the mining machine when the input voltage is higher than or equal to the voltage threshold, where the first power value is the product of the input voltage multiplied by a rated current of the mining machine, and the second power value is the product of the voltage threshold multiplied by the rated current. According to the disclosure, the power of the mining machine is adjusted according to changes in the input voltage by fully utilizing a voltage range slightly higher than a standard input voltage, so that the calculation power of the mining machine can be greatly increased to achieve better mining revenues without significantly increasing the power consumption ratio of the mining machine while ensuring the stable and safe running of the mining machine.

8. 发明授权

US12141002B2 Hashboard, power supply system of digital processing device, and digital processing device 有权
公开(公告)号：US12141002B2
公开(公告)日：2024-11-12
申请号：US18043843
申请日：2021-06-11
申请人： SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD.
发明人： Yuefeng Wu , Zuoxing Yang , Yang Gao , Haifeng Guo , Hongyan Ning
IPC分类号： G06F1/18
CPC分类号： G06F1/188
摘要： A hashboard, a power supply system of a digital processing device and the digital processing device. The digital processing device comprises: a housing; N (≥2) hashboards and a control board both located inside the housing. Each hashboard comprises: a substrate; power positive and power negative terminals respectively mounted on the substrate and adapted to be connected to another hashboard in series; a communication interface mounted on the substrate; and computing chips mounted on the substrate. A signal transfer path of the computing chips has a chain configuration. The N hashboards are connected in series to form a series power supply configuration, a power positive terminal of a first hashboard in the series power supply configuration is connected to a positive terminal of a power supply, and a power negative terminal of a last hashboard in the series power supply configuration is connected to a negative terminal of the power supply.

9. 发明申请

US20220374063A1 RAPID FREQUENCY SEARCHING METHOD AND APPARATUS FOR DATA PROCESSING DEVICE, AND DATA PROCESSING DEVICE 有权
公开(公告)号：US20220374063A1
公开(公告)日：2022-11-24
申请号：US17606939
申请日：2021-07-23
申请人： SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD.
发明人： Weibin Ma , Hong Zhang , Lihong Huang , Zuoxing Yang , Haifeng Guo
IPC分类号： G06F1/324
摘要： The present disclosure discloses a rapid frequency searching method and apparatus for a data processing device, and a data processing device. The method includes: gradually raising a frequency of a computing chip from an initial frequency point to a target frequency through at least one first frequency point at an initial output voltage of a power source of the data processing device, wherein the duration when the computing chip is located at each of the at least one first frequency point is shorter than the duration when the computing chip is located at each of the at least one first frequency point in a routine frequency searching process; and after the computing chip achieves the target frequency, adjusting the output voltage of the power source of the data processing device and the frequency of the computing chip according to at least one output voltage value and at least one second frequency point in combination with test tasks delivered to the computing chip and feedback results from the computing chip to obtain a limit frequency of the computing chip and an output voltage, corresponding to the limit frequency, of the power source of the data processing device.

10. 发明授权

US12124402B2 Computing device and computing system for digital currency 有权
公开(公告)号：US12124402B2
公开(公告)日：2024-10-22
申请号：US18044830
申请日：2021-08-20
申请人： SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD.
发明人： Zhijun Fan , Haifeng Guo , Jianbo Liu , Zuoxing Yang
IPC分类号： G06F15/16 , G06Q20/06
CPC分类号： G06F15/16 , G06Q20/065 , G06Q2220/00
摘要： A computing device and a computing system for digital currency are disclosed. The computing system comprises: computing devices (comprising first and second computing devices) each comprising two ports; and a signal transmission path connecting the computing devices in series. Each computing device is connected to the signal transmission path via the two ports. The first computing device is configured to receive, from the signal transmission path through one of the two ports, a signal specific to an address of the first computing device to a local storage device thereof. The second computing device is configured to receive, from the signal transmission path through one of the two ports, a signal to a local storage device thereof, and forward the signal, which is not specific to an address of the second computing device, or an adjusted version of the signal to the signal transmission path through one of the ports.

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