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1. 发明授权

US12113537B1 Pipeline clock driving circuit, computing chip, hashboard, and computing device 有权
公开(公告)号：US12113537B1
公开(公告)日：2024-10-08
申请号：US18704562
申请日：2024-01-12
申请人： SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD.
发明人： Nan Li , Haifeng Guo , Zhijun Fan , Lianhua Duan
IPC分类号： H03K5/00 , H03K3/027 , H03K5/13 , H03K5/15
CPC分类号： H03K5/1508 , H03K3/027 , H03K5/13 , H03K5/15
摘要： The present disclosure relates to a pipeline clock driving circuit, a computing chip, a hashboard, and a computing device. Disclosed is a pipeline clock driving circuit, configured to provide a pulse clock signal to a pipeline, including: a plurality of stages of clock driving circuits, each stage being configured to provide the pulse clock signal to a corresponding operation stage of the pipeline; a clock source, coupled to an input of a first-stage clock driving circuit, each stage of the clock driving circuits including: a trigger, coupled to an input of a current-stage clock driving circuit; a delay module, including a first delay sub-module, the first delay sub-module delaying a pulse signal output by the trigger and feeding a delayed pulse signal back to the trigger as a feedback pulse signal; and a combinational logic module, performing a combinational logic operation on the pulse signal and the feedback pulse signal to generate the pulse clock signal to be provided to a corresponding operation stage, where the delay module further includes a second delay sub-module, and the second delay sub-module delays the pulse signal and outputs the delayed pulse signal to a next-stage clock driving circuit.

2. 发明授权

US11791807B2 Multi-level pulser circuit and method of operating a multi-level pulser circuit 有权
公开(公告)号：US11791807B2
公开(公告)日：2023-10-17
申请号：US17676005
申请日：2022-02-18
申请人： STMICROELECTRONICS S.R.L.
发明人： Marco Viti
IPC分类号： H03K3/00 , H03K3/027 , H03K19/20
CPC分类号： H03K3/027 , H03K19/20
摘要： A multi-level pulser circuit comprises a set of first input pins for receiving respective positive voltage signals at different voltage levels, a set of second input pins for receiving respective negative voltage signals at different voltage levels, and a reference input pin configured to receive a reference voltage signal intermediate the positive voltage signals and the negative voltage signals. The circuit comprises an output pin configured to supply a pulsed output signal. The circuit further comprises control circuitry configured to selectively couple the output pin to one of the first input pins, the second input pins and the reference input pin to generate the pulsed output signal at the output pin. The control circuitry is further configured to selectively couple at least one of the second input pins and the reference input pin to the output pin during falling transitions of the pulsed output signal between two positive voltage levels, and selectively couple at least one of the first input pins and the reference input pin to the output pin during rising transitions of the pulsed output signal between two negative voltage levels.

3. 发明授权

US10615781B2 Semiconductor apparatus 有权
公开(公告)号：US10615781B2
公开(公告)日：2020-04-07
申请号：US16517188
申请日：2019-07-19
申请人： SK hynix Inc.
发明人： Young Hoon Kim
IPC分类号： H03K25/00 , H03K3/027 , H03K5/151 , H03K5/1252 , H03K3/012 , H03K3/356 , H03K19/0175
CPC分类号： H03K3/027 , H03K3/012 , H03K3/356043 , H03K5/1252 , H03K5/151 , H03K19/0175
摘要： A semiconductor apparatus includes a pulse generation circuit which generates a pulse signal in response to a clock, and an amplification circuit which generates an output signal in response to an input signal, the clock, and the pulse signal, wherein the amplification circuit voltage is configured to amplify a voltage level difference between a pair of latch input nodes.

4. 发明授权

US09977453B2 Temperature sensing apparatus 有权
公开(公告)号：US09977453B2
公开(公告)日：2018-05-22
申请号：US15143120
申请日：2016-04-29
申请人： SK hynix Inc.
发明人： Jenn-Gang Chern
IPC分类号： H03L7/00 , G05F3/24 , H03B5/12 , H03L1/02 , H03K3/027 , H03K3/03
CPC分类号： G05F3/245 , H03B5/1209 , H03K3/027 , H03K3/0315 , H03K3/0322 , H03L1/02 , H03L1/022
摘要： An apparatus for temperature sensing may include: a bias generator suitable for generating a complementary-to-absolute-temperature (CTAT) bias voltage; a regulator suitable for regulating a bias voltage by using CTAT bias voltage and outputting a regulated bias voltage; and a ring oscillator suitable for receiving the regulated bias voltage and generating an oscillation signal based on the regulated bias voltage.

5. 发明授权

US09838029B1 Adaptively controlled duty cycle clock generation circuit 有权
公开(公告)号：US09838029B1
公开(公告)日：2017-12-05
申请号：US15369087
申请日：2016-12-05
申请人： Analog Devices Global
发明人： Ting Gao
IPC分类号： H03M1/12 , H03K3/017 , H03K3/027 , H03K3/023 , H03K5/151 , H03K5/156 , H03K7/08 , H03M1/00 , H03L7/089
CPC分类号： H03M1/1245 , H03K3/017 , H03K3/023 , H03K3/027 , H03K5/1515 , H03K5/1565 , H03K7/08 , H03L7/0891 , H03M1/00 , H03M1/12
摘要： A clock generation circuit coupled to an integrator circuit uses a variable resistance that is adjusted in a transconductance bias feedback circuit. This resistance is calibrated to the reciprocal of the transconductance of the input amplifier. The product of the adjusted resistance and a capacitance in the clock generation circuit provides a time constant for the settling time of the integrator and controls a pulse width of an adaptively controlled duty cycle output clock.

6. 发明授权

US08363431B2 Oscillator having time-variant frequency deviation and related power supply 有权
标题翻译：振荡器具有时变频率偏差和相关电源
公开(公告)号：US08363431B2
公开(公告)日：2013-01-29
申请号：US12883187
申请日：2010-09-16
申请人： Chin-Yen Lin , Min-Chu Chien
发明人： Chin-Yen Lin , Min-Chu Chien
IPC分类号： H02M3/335
CPC分类号： H02M1/44 , G06F1/04 , H02M3/33523 , H03K3/027 , H03K4/502
摘要： An oscillator with time-variant frequency deviation for a power supply includes a signal generator for generating a first signal according to a clock signal and a comparing unit for adding an offset to at least one of the first signal and a threshold voltage corresponding to the first signal and for comparing the first signal and the threshold voltage after completion of the offset adding, to generate the clock signal whose frequency deviates with variation of the added offset.
摘要翻译：电源具有时变频率偏差的振荡器包括：信号发生器，用于根据时钟信号产生第一信号;以及比较单元，用于将偏移量与第一信号和对应于第一信号的阈值电压中的至少一个相加信号，并且用于在完成偏移相加之后比较第一信号和阈值电压，以产生频率随着附加偏移的变化而偏移的时钟信号。

7. 发明授权

US4019519A Nerve stimulating device 失效
标题翻译：神经刺激装置
公开(公告)号：US4019519A
公开(公告)日：1977-04-26
申请号：US594024
申请日：1975-07-08
申请人： Leonardus Johannes Geerling
发明人： Leonardus Johannes Geerling
IPC分类号： A61N1/36 , H02M3/338 , H02M5/44 , H03K3/027 , H03K17/66
CPC分类号： A61N1/36014 , H02M3/3381 , H02M5/44 , H03K17/661 , H03K17/667 , H03K3/027
摘要： A pulse generator for providing timed pulses of adjustable amplitude and constant width for nerve stimulation at selected portions of a body. The timed pulses of positive and negative amplitude are generated alternatinely and the period can be precisely set.
摘要翻译：脉冲发生器，用于提供可调幅度和恒定宽度的定时脉冲，用于在身体的选定部分进行神经刺激。正，负幅度的定时脉冲交替产生，周期可以精确设定。

8. 发明授权

US3941925A Digital soft edge video transition system 失效
标题翻译：数字软边缘视频转换系统
公开(公告)号：US3941925A
公开(公告)日：1976-03-02
申请号：US557067
申请日：1975-03-10
申请人： Albert E. Busch , John R. Hotsenpiller
发明人： Albert E. Busch , John R. Hotsenpiller
IPC分类号： H03K3/027 , H04N5/262 , H04N5/275 , H04N5/22
CPC分类号： H03K3/027 , H04N5/262 , H04N5/2622 , H04N5/275
摘要： A digital soft edge transition system for use in a video special effects generator utilizes digital circuitry responsive to a transition signal for switching either a first video input signal or a second video input signal into a composite video output signal. An analog video switch is utilized to provide a gradual transition between the video input signals. The gradient of the transition is determined by a counter and a variable speed clock, driving a digital-to-analog converter, or by a data selector interposed between the counter and the digital-to-analog converter. A "mirror image" circuit is utilized to generate symmetrical effects such as circles, diamonds and other effects requiring more than one transition between the video input signals. The "mirror image" circuit serves to store the location of the completion of the first transition and to begin the second transition at a location on the displayed image determined by the value of the stored location. In the preferred embodiment, the locations of the completion of the first transition and the beginning of the second transition are symmetrically disposed about a center line of the displayed image so that the desired effect is symmetrically displayed on the viewing screen.
摘要翻译：用于视频特效发生器的数字软边缘转换系统利用响应于转换信号的数字电路，用于将第一视频输入信号或第二视频输入信号切换为复合视频输出信号。模拟视频开关用于提供视频输入信号之间的逐渐转换。转换的梯度由计数器和可变速度时钟，驱动数模转换器或插入在计数器和数模转换器之间的数据选择器确定。利用“镜像”电路来产生对称的效果，如圆形，菱形和其他影响，需要视频输入信号之间的多个转换。 “镜像”电路用于存储第一转换完成的位置，并且在由存储的位置的值确定的显示图像上的位置处开始第二转换。在优选实施例中，第一转变的完成位置和第二转换开始的位置围绕所显示的图像的中心线对称设置，使得期望的效果对称地显示在观看屏幕上。

9. 发明授权

US3764920A Apparatus for sampling an asynchronous signal by a synchronous signal 失效
标题翻译：用同步信号采集异常信号的装置
公开(公告)号：US3764920A
公开(公告)日：1973-10-09
申请号：US3764920D
申请日：1972-06-15
申请人： HONEYWELL INF SYSTEMS
发明人： GALCIK A , LANGE R
IPC分类号： G06F13/42 , G06F3/05 , H03K3/027 , H03K5/135 , H03K19/00 , H03K19/0175 , H03K5/20
CPC分类号： H03K5/135 , H03K3/027
摘要： The asynchronous signal is complemented and directed to a latching logic circuit as the data input and the synchronous signal are directed to the clock input of the latching circuit. The latching circuit has built-in delays to reliably latch if the low or active portion of the asynchronous pulse occurs during the ''''window'''' or high portion of the synchronous signal. The latching circuit also includes a jamming circuit connected to its clock input whereby a low or disabled window time of the synchronous signal prevents a change in state by the latching circuit. A pulse delay circuit generates a sampling pulse a period of time after the window time to sample the output of the latching circuit.
摘要翻译：当数据输入和同步信号被引导到锁存电路的时钟输入时，异步信号被补充并被引导到锁存逻辑电路。如果异步脉冲的低或有效部分在同步信号的“窗口”或高部分期间发生，则锁存电路具有内部延迟以可靠地锁存。锁存电路还包括连接到其时钟输入的干扰电路，由此同步信号的低或禁止的窗口时间防止锁存电路的状态改变。脉冲延迟电路在窗口时间之后的一段时间内产生采样脉冲，以采样锁存电路的输出。

10. 发明授权

US3757231A Asynchronous circuit and system 失效
标题翻译：异步电路与系统
公开(公告)号：US3757231A
公开(公告)日：1973-09-04
申请号：US3757231D
申请日：1970-03-26
申请人： DYAD SYSTEMS INC
发明人： FAUSTINI C
IPC分类号： G06F7/00 , G06F5/06 , G06F5/08 , G06F7/50 , G06F7/501 , G06F7/503 , G06F7/52 , G06F7/525 , G11C11/56 , G11C19/00 , G11C19/28 , H03K3/02 , H03K3/027 , H03K3/037 , H03K19/0175
CPC分类号： G06F7/504 , G06F5/06 , G06F5/08 , G06F7/525 , G11C11/412 , G11C11/5621 , G11C19/00 , G11C19/28 , G11C19/282 , G11C2211/5642 , H03K3/027 , H03K3/037 , H03K19/017545
摘要： An asynchronous logic circuit is provided having three stable states, namely two information states and a neutral state. Information is transferred between cacaded such circuits wholly under the control of such circuits and at a rate determined by the delay times through various gates. Feedback is employed between each circuit so that for any two given circuits the transfer logic is IN -> NI, I representing an information state and N representing the neutral state. Reversible cascaded chains are discussed as well as parallel feed-in and feed-out of information, and fan-in, fan-out and recirculating loops of information. The cascaded circuits (nets) employ interface circuits comprising in most instances a specified part of the basic net circuit.

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