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1. 发明授权

US12140991B2 Method for providing clock frequencies for computing cores, chip and data processing device 有权
公开(公告)号：US12140991B2
公开(公告)日：2024-11-12
申请号：US17911604
申请日：2021-04-12
申请人： SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD.
发明人： Jianbo Liu , Weibin Ma , Lihong Huang , Zuoxing Yang , Haifeng Guo
IPC分类号： G06F1/00 , G06F1/08
CPC分类号： G06F1/08
摘要： The present disclosure relates to a method for providing clock frequencies for computing cores, a chip and a data processing device. The method includes: causing a main clock frequency unit to provide a first main clock frequency for computing cores; testing the computing cores operating at the first main clock frequency to determine whether a pass rate of the computing cores is greater than an upper threshold or less than a lower threshold; when the pass rate is less than the lower threshold, causing an auxiliary clock frequency unit to provide a lower first auxiliary clock frequency for computing cores abnormally operating, causing the main clock frequency unit to providing the first main clock frequency for the remaining computing cores; when the pass rate is greater than the upper threshold, causing the main clock frequency unit to provide a higher second main clock frequency for the computing cores.

2. 发明授权

US11579875B2 Computing chip, hashrate board and data processing apparatus 有权
公开(公告)号：US11579875B2
公开(公告)日：2023-02-14
申请号：US17633084
申请日：2021-06-08
申请人： SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD.
发明人： Chao Xu , Zhijun Fan , Ke Xue , Zuoxing Yang
IPC分类号： G06F9/30 , G06F7/57
摘要： This disclosure relates to a computing chip, a hashrate board, and a data processing apparatus. The computing chip includes a plurality of operation stages arranged in a pipeline configuration. Each operation stage includes: a first combinational logic circuit occupying a plurality of first cell points adjacent to each other, at least a portion of the first cell points being located in a first incomplete column; one or more second combinational logic circuits each occupying one or more second cell points, at least a portion of the second cell points being located in a second incomplete column; and a plurality of registers each occupying a plurality of third cell points, at least a portion of the third cell points being located in the first incomplete column or the second incomplete column. The first cell points, the second cell points, and third cell points occupy equal areas on the computing chip.

3. 发明授权

US12124855B2 Training method for parameter configuration model, parameter configuration method, and parameter configuration device 有权
公开(公告)号：US12124855B2
公开(公告)日：2024-10-22
申请号：US18692643
申请日：2022-09-15
申请人： SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD.
发明人： Guo Ai , Haifeng Guo , Zuoxing Yang
IPC分类号： G06F1/24 , G06F9/4401 , G06F8/65
CPC分类号： G06F9/4401 , G06F8/65
摘要： The present disclosure relates to a training method for a parameter configuration model, a parameter configuration method, and a parameter configuration device. The training method includes: obtaining a training sample set of a data processing device, wherein the training sample set includes operation parameters and benefit parameters in one-to-one correspondence with the operation parameters, the operation parameter includes at least one of a global operation parameter or a local operation parameter associated with position distribution, the benefit parameter is configured to reflect a ratio of power consumption to computing power of the data processing device; training the parameter configuration model based on the training sample set, wherein the operation parameter is configured as an input of the parameter configuration model, and the benefit parameter is configured as an output of the parameter configuration model; and in a case that a training accuracy of the parameter configuration model is greater than or equal to a first preset accuracy, ending the training and obtaining a trained parameter configuration model.

4. 发明授权

US12093099B2 Method and apparatus for controlling voltage of power supply of data processing device, data processing device, and storage medium 有权
公开(公告)号：US12093099B2
公开(公告)日：2024-09-17
申请号：US17997316
申请日：2021-05-19
申请人： SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD.
发明人： Weibin Ma , Lihong Huang , Yuefeng Wu , Haifeng Guo , Zuoxing Yang
IPC分类号： G06F1/26
CPC分类号： G06F1/266
摘要： Implementations of this application provide a method and an apparatus for controlling a voltage of a power supply of a data processing device and a data processing device. The method includes: determining a computing power ratio of the data processing device based on an actual computing power and a theoretical computing power of the data processing device; generating a power supply control instruction based on a result of comparison between the computing power ratio and a predetermined threshold; and controlling an output voltage of the power supply of the data processing device based on the power supply control instruction. According to the implementations of this application, the output voltage of the power supply is controlled according to the computing power ratio, and a good compromise can be obtained between the power consumption loss and the computing power of the data processing device.

5. 发明授权

US11581894B2 Alternative data selector, full adder and ripple carry adder 有权
公开(公告)号：US11581894B2
公开(公告)日：2023-02-14
申请号：US17629153
申请日：2021-05-24
申请人： SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD.
发明人： Zhijun Fan , Weixin Kong , Dong Yu , Zuoxing Yang
IPC分类号： H03K19/20 , G06F7/503
摘要： Alternative data selector, a full adder, and a ripple carry adder are disclosed. The alternative data selector includes: a NOR logic circuit configured to receive a selection signal and an inverted first input and generate an intermediate result; and an AND-OR-NOT logic circuit configured to receive the selection signal, a second input, and the intermediate result of the NOR logic circuit and generate an inverted output.

6. 发明授权

US11340646B1 Mining machine power adjustment method 有权
公开(公告)号：US11340646B1
公开(公告)日：2022-05-24
申请号：US17434376
申请日：2021-05-07
申请人： Shenzhen MicroBT Electronics Technology Co., Ltd.
发明人： Lihong Huang , Weibin Ma , Zuoxing Yang , Yuefeng Wu , Haifeng Guo
IPC分类号： G06F1/00 , G05F1/67 , G06F1/3296 , G06F1/324
摘要： Disclosed is a mining machine power adjusting method, including: when a mining machine is in a working stage, collecting an input voltage of the mining machine; adjusting a maximum working power of the mining machine to a first power value by controlling a working frequency and an output voltage of the mining machine when the input voltage is lower than a pre-determined voltage threshold; and adjusting the maximum working power to a second power value by controlling the working frequency and the output voltage of the mining machine when the input voltage is higher than or equal to the voltage threshold, where the first power value is the product of the input voltage multiplied by a rated current of the mining machine, and the second power value is the product of the voltage threshold multiplied by the rated current. According to the disclosure, the power of the mining machine is adjusted according to changes in the input voltage by fully utilizing a voltage range slightly higher than a standard input voltage, so that the calculation power of the mining machine can be greatly increased to achieve better mining revenues without significantly increasing the power consumption ratio of the mining machine while ensuring the stable and safe running of the mining machine.

7. 发明授权

US12141002B2 Hashboard, power supply system of digital processing device, and digital processing device 有权
公开(公告)号：US12141002B2
公开(公告)日：2024-11-12
申请号：US18043843
申请日：2021-06-11
申请人： SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD.
发明人： Yuefeng Wu , Zuoxing Yang , Yang Gao , Haifeng Guo , Hongyan Ning
IPC分类号： G06F1/18
CPC分类号： G06F1/188
摘要： A hashboard, a power supply system of a digital processing device and the digital processing device. The digital processing device comprises: a housing; N (≥2) hashboards and a control board both located inside the housing. Each hashboard comprises: a substrate; power positive and power negative terminals respectively mounted on the substrate and adapted to be connected to another hashboard in series; a communication interface mounted on the substrate; and computing chips mounted on the substrate. A signal transfer path of the computing chips has a chain configuration. The N hashboards are connected in series to form a series power supply configuration, a power positive terminal of a first hashboard in the series power supply configuration is connected to a positive terminal of a power supply, and a power negative terminal of a last hashboard in the series power supply configuration is connected to a negative terminal of the power supply.

8. 发明授权

US12007819B2 Method and apparatus for starting up digital currency data processing device, and digital currency data processing device 有权
公开(公告)号：US12007819B2
公开(公告)日：2024-06-11
申请号：US17798507
申请日：2021-03-30
申请人： SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD.
发明人： Weibin Ma , Lihong Huang , Yuefeng Wu , Zuoxing Yang
IPC分类号： G06F1/20 , G06F1/04 , G06F1/26
CPC分类号： G06F1/20 , G06F1/04 , G06F1/26
摘要： A method and apparatus for starting up a digital currency data processing device, and a digital currency data processing device. The digital currency data processing device includes a hash board including a plurality of hash chip groups. The method includes: transmitting a startup signal to a refrigerating part of a data processing device before turning on a power supply; turning on the power supply; and controlling respective hash chips in each hash chip group to gradually and synchronously turn on cores. The above arrangement improves voltage balance of a hash board, and also ensures the accuracy of a clock signal.

9. 发明申请

US20220374063A1 RAPID FREQUENCY SEARCHING METHOD AND APPARATUS FOR DATA PROCESSING DEVICE, AND DATA PROCESSING DEVICE 有权
公开(公告)号：US20220374063A1
公开(公告)日：2022-11-24
申请号：US17606939
申请日：2021-07-23
申请人： SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD.
发明人： Weibin Ma , Hong Zhang , Lihong Huang , Zuoxing Yang , Haifeng Guo
IPC分类号： G06F1/324
摘要： The present disclosure discloses a rapid frequency searching method and apparatus for a data processing device, and a data processing device. The method includes: gradually raising a frequency of a computing chip from an initial frequency point to a target frequency through at least one first frequency point at an initial output voltage of a power source of the data processing device, wherein the duration when the computing chip is located at each of the at least one first frequency point is shorter than the duration when the computing chip is located at each of the at least one first frequency point in a routine frequency searching process; and after the computing chip achieves the target frequency, adjusting the output voltage of the power source of the data processing device and the frequency of the computing chip according to at least one output voltage value and at least one second frequency point in combination with test tasks delivered to the computing chip and feedback results from the computing chip to obtain a limit frequency of the computing chip and an output voltage, corresponding to the limit frequency, of the power source of the data processing device.

10. 发明授权

US11742866B2 Method for up-converting clock signal, clock circuit and digital processing device 有权
公开(公告)号：US11742866B2
公开(公告)日：2023-08-29
申请号：US17621138
申请日：2021-06-22
申请人： SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD.
发明人： Jianbo Liu , Weibin Ma , Lihong Huang , Zuoxing Yang , Haifeng Guo
IPC分类号： H03D3/24 , H03L7/099 , H03L7/089 , H03L7/093
CPC分类号： H03L7/0992 , H03L7/089 , H03L7/093
摘要： The present disclosure relates to a method for up-converting a clock signal, a clock circuit and a digital processing device. More specifically, provided is a method for up-converting a clock signal, comprising: employing a first clock sub-circuit to provide a clock signal having a first frequency to a chip; receiving an instruction to up-convert the clock signal having the first frequency to a clock signal having a second frequency; in response to receiving the instruction, causing a second clock sub-circuit to output the clock signal having the second frequency; and after the second clock sub-circuit outputs the clock signal having the second frequency, employing the second clock sub-circuit to provide the clock signal having the second frequency to the chip in place of the first clock sub-circuit.

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