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1. 发明申请

US20050098800A1 Nonvolatile memory cell comprising a reduced height vertical diode 有权
标题翻译：非易失性存储单元包括减小的高度的垂直二极管
公开(公告)号：US20050098800A1
公开(公告)日：2005-05-12
申请号：US11015824
申请日：2004-12-17
申请人： S. Herner , Steven Radigan
发明人： S. Herner , Steven Radigan
IPC分类号： G11C7/00 , G11C11/39 , G11C17/06 , G11C17/16 , G11C29/00 , H01L21/336 , H01L21/82 , H01L27/24 , H01L29/73 , H01L45/00
CPC分类号： G11C5/02 , G11C11/39 , G11C17/06 , G11C17/16 , G11C2213/71 , G11C2213/77 , H01L27/1021 , H01L29/0649 , H01L29/66272 , H01L29/732 , H01L29/868
摘要： A nonvolatile memory cell according to the present invention comprises a bottom conductor, a semiconductor pillar, and a top conductor. The semiconductor pillar comprises a junction diode, including a bottom heavily doped region, a middle intrinsic or lightly doped region, and a top heavily doped region, wherein the conductivity types of the top and bottom heavily doped region are opposite. The junction diode is vertically oriented and is of reduced height, between about 500 angstroms and about 3500 angstroms. A monolithic three dimensional memory array of such cells can be formed comprising multiple memory levels, the levels monolithically formed above one another.
摘要翻译：根据本发明的非易失性存储单元包括底部导体，半导体柱和顶部导体。半导体柱包括结二极管，其包括底部重掺杂区域，中间固有或轻掺杂区域和顶部重掺杂区域，其中顶部和底部重掺杂区域的导电类型相反。结二极管是垂直取向的，并且具有降低的高度，在约500埃至约3500埃之间。可以形成这样的单元的单片三维存储器阵列，其包括多个存储器级，电平彼此整体地形成。

2. 发明授权

US07935553B2 Method for fabricating high density pillar structures by double patterning using positive photoresist 有权
标题翻译：通过使用正性光致抗蚀剂的双重图案制造高密度柱结构的方法
公开(公告)号：US07935553B2
公开(公告)日：2011-05-03
申请号：US12777046
申请日：2010-05-10
申请人： Roy E. Scheuerlein , Steven Radigan
发明人： Roy E. Scheuerlein , Steven Radigan
IPC分类号： H01L21/00
CPC分类号： H01L27/1021 , H01L27/101 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/14 , H01L45/146 , H01L45/147 , H01L45/149 , H01L45/16
摘要： A method of making a semiconductor device includes forming a first photoresist layer over an underlying layer, patterning the first photoresist layer into a first photoresist pattern, wherein the first photoresist pattern comprises a plurality of spaced apart first photoresist features located over the underlying layer, and etching the underlying layer using the first photoresist pattern as a mask to form a plurality of first spaced apart features. The method further includes removing the first photoresist pattern, forming a second photoresist layer over the plurality of first spaced apart features, and patterning the second photoresist layer into a second photoresist pattern, wherein the second photoresist pattern comprises a plurality of second photoresist features covering edge portions of the plurality of first spaced apart features. The method also includes etching exposed portions of the plurality of first spaced apart features using the second photoresist pattern as a mask, such that a plurality of spaced apart edge portions of the plurality of first spaced apart features remain, and removing the second photoresist pattern.
摘要翻译：制造半导体器件的方法包括在下层上形成第一光致抗蚀剂层，将第一光致抗蚀剂层图案化为第一光致抗蚀剂图案，其中第一光致抗蚀剂图案包括位于下层之上的多个间隔开的第一光致抗蚀剂特征，以及使用第一光致抗蚀剂图案作为掩模蚀刻下层，以形成多个第一间隔的特征。该方法还包括去除第一光致抗蚀剂图案，在多个第一间隔开的特征上形成第二光致抗蚀剂层，以及将第二光致抗蚀剂层图案化为第二光致抗蚀剂图案，其中第二光致抗蚀剂图案包括覆盖边缘多个第一间隔开的特征部分。该方法还包括使用第二光致抗蚀剂图案作为掩模蚀刻多个第一间隔开的特征的暴露部分，使得多个第一间隔开的特征中的多个间隔开的边缘部分保留，并且去除第二光致抗蚀剂图案。

3. 发明申请

US20060222962A1 Masking of repeated overlay and alignment marks to allow reuse of photomasks in a vertical structure 有权
公开(公告)号：US20060222962A1
公开(公告)日：2006-10-05
申请号：US11097496
申请日：2005-03-31
申请人： Yung-Tin Chen , Christopher Petti , Steven Radigan , Tanmay Kumar
发明人： Yung-Tin Chen , Christopher Petti , Steven Radigan , Tanmay Kumar
IPC分类号： G03C5/00 , G03F9/00 , G03F1/00
CPC分类号： H01L27/0688 , G03F7/70633 , G03F9/7084 , H01L23/544 , H01L2223/5442 , H01L2223/54426 , H01L2223/5446
摘要： In formation of monolithic three dimensional memory arrays, a photomask may be used more than once. Reuse of a photomask creates second, third or more instances of reference marks used by the stepper to achieve alignment (alignment marks) and to measure alignment achieved (overlay marks) directly above prior instances of the same reference mark. The prior instances of the same reference mark may cause interference with the present instance of the reference mark, complicating alignment and measurement. Using the methods of the present invention, blocking structure is created vertically interposed between subsequent instances of the same reference mark, preventing interference.

4. 发明申请

US20100219510A1 METHOD FOR FABRICATING HIGH DENSITY PILLAR STRUCTURES BY DOUBLE PATTERNING USING POSITIVE PHOTORESIST 有权
标题翻译：使用正电子照相机双重方式制作高密度立柱结构的方法
公开(公告)号：US20100219510A1
公开(公告)日：2010-09-02
申请号：US12777046
申请日：2010-05-10
申请人： Roy E. Scheuerlein , Steven Radigan
发明人： Roy E. Scheuerlein , Steven Radigan
IPC分类号： H01L29/06 , H01L21/308
CPC分类号： H01L27/1021 , H01L27/101 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/14 , H01L45/146 , H01L45/147 , H01L45/149 , H01L45/16
摘要： A method of making a semiconductor device includes forming a first photoresist layer over an underlying layer, patterning the first photoresist layer into a first photoresist pattern, wherein the first photoresist pattern comprises a plurality of spaced apart first photoresist features located over the underlying layer, and etching the underlying layer using the first photoresist pattern as a mask to form a plurality of first spaced apart features. The method further includes removing the first photoresist pattern, forming a second photoresist layer over the plurality of first spaced apart features, and patterning the second photoresist layer into a second photoresist pattern, wherein the second photoresist pattern comprises a plurality of second photoresist features covering edge portions of the plurality of first spaced apart features. The method also includes etching exposed portions of the plurality of first spaced apart features using the second photoresist pattern as a mask, such that a plurality of spaced apart edge portions of the plurality of first spaced apart features remain, and removing the second photoresist pattern.
摘要翻译：制造半导体器件的方法包括在下层上形成第一光致抗蚀剂层，将第一光致抗蚀剂层图案化为第一光致抗蚀剂图案，其中第一光致抗蚀剂图案包括位于下层之上的多个间隔开的第一光致抗蚀剂特征，以及使用第一光致抗蚀剂图案作为掩模蚀刻下层，以形成多个第一间隔的特征。该方法还包括去除第一光致抗蚀剂图案，在多个第一间隔开的特征上形成第二光致抗蚀剂层，以及将第二光致抗蚀剂层图案化为第二光致抗蚀剂图案，其中第二光致抗蚀剂图案包括覆盖边缘多个第一间隔开的特征部分。该方法还包括使用第二光致抗蚀剂图案作为掩模蚀刻多个第一间隔开的特征的暴露部分，使得多个第一间隔开的特征中的多个间隔开的边缘部分保留，并且去除第二光致抗蚀剂图案。

5. 发明申请

US20090323385A1 Method for fabricating high density pillar structures by double patterning using positive photoresist 有权
标题翻译：通过使用正性光致抗蚀剂的双重图案制造高密度柱结构的方法
公开(公告)号：US20090323385A1
公开(公告)日：2009-12-31
申请号：US12216108
申请日：2008-06-30
申请人： Roy E. Scheuerlein , Steven Radigan
发明人： Roy E. Scheuerlein , Steven Radigan
IPC分类号： H01L21/311 , G11C5/02
CPC分类号： H01L27/1021 , H01L27/101 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/14 , H01L45/146 , H01L45/147 , H01L45/149 , H01L45/16
摘要： A method of making a semiconductor device includes forming a first photoresist layer over an underlying layer, patterning the first photoresist layer into a first photoresist pattern, wherein the first photoresist pattern comprises a plurality of spaced apart first photoresist features located over the underlying layer, and etching the underlying layer using the first photoresist pattern as a mask to form a plurality of first spaced apart features. The method further includes removing the first photoresist pattern, forming a second photoresist layer over the plurality of first spaced apart features, and patterning the second photoresist layer into a second photoresist pattern, wherein the second photoresist pattern comprises a plurality of second photoresist features covering edge portions of the plurality of first spaced apart features. The method also includes etching exposed portions of the plurality of first spaced apart features using the second photoresist pattern as a mask, such that a plurality of spaced apart edge portions of the plurality of first spaced apart features remain, and removing the second photoresist pattern.
摘要翻译：制造半导体器件的方法包括在下层上形成第一光致抗蚀剂层，将第一光致抗蚀剂层图案化为第一光致抗蚀剂图案，其中第一光致抗蚀剂图案包括位于下层之上的多个间隔开的第一光致抗蚀剂特征，以及使用第一光致抗蚀剂图案作为掩模蚀刻下层，以形成多个第一间隔的特征。该方法还包括去除第一光致抗蚀剂图案，在多个第一间隔开的特征上形成第二光致抗蚀剂层，以及将第二光致抗蚀剂层图案化为第二光致抗蚀剂图案，其中第二光致抗蚀剂图案包括多个第二光致抗蚀剂特征，多个第一间隔开的特征部分。该方法还包括使用第二光致抗蚀剂图案作为掩模蚀刻多个第一间隔开的特征的暴露部分，使得多个第一间隔开的特征中的多个间隔开的边缘部分保留，并且去除第二光致抗蚀剂图案。

6. 发明申请

US20060128153A1 Method for cleaning slurry particles from a surface polished by chemical mechanical polishing 失效
标题翻译：通过化学机械抛光抛光的表面清洗浆料颗粒的方法
公开(公告)号：US20060128153A1
公开(公告)日：2006-06-15
申请号：US11013067
申请日：2004-12-14
申请人： Samuel Dunton , Steven Radigan
发明人： Samuel Dunton , Steven Radigan
IPC分类号： H01L21/461 , H01L21/302 , H01L21/4763
CPC分类号： H01L21/76819 , H01L21/02065 , H01L21/31053 , H01L21/3212 , H01L21/7684 , H01L27/101 , H01L27/1021 , Y10S438/959
摘要： A method is provided to clean slurry particles from a surface in which tungsten and dielectric are coexposed after a dielectric CMP step. Such a surface is formed when tungsten features are patterned and etched, the tungsten features are covered with dielectric, and the dielectric is planarized to expose tops of the tungsten features. The surface to be cleaned is subjected to mechanical action in an acid environment. Suitable mechanical action includes performing a brief tungsten CMP step on the tungsten features or scrubbing the surface using, for example, a commercial post-CMP scrubber.
摘要翻译：提供了一种方法，用于在电介质CMP步骤之后从其中钨和电介质共面的表面清洗浆料颗粒。当钨特征被图案化和蚀刻时，形成这样的表面，钨特征被电介质覆盖，并且电介质被平坦化以暴露钨特征的顶部。待清洁的表面在酸性环境中受到机械作用。合适的机械作用包括使用例如商业后CMP洗涤器在钨特征上进行简单的钨CMP步骤或擦洗表面。

7. 发明授权

US08138010B2 Method for fabricating high density pillar structures by double patterning using positive photoresist 有权
标题翻译：通过使用正性光致抗蚀剂的双重图案制造高密度柱结构的方法
公开(公告)号：US08138010B2
公开(公告)日：2012-03-20
申请号：US13070825
申请日：2011-03-24
申请人： Roy E. Scheuerlein , Steven Radigan
发明人： Roy E. Scheuerlein , Steven Radigan
IPC分类号： H01L21/00
CPC分类号： H01L27/1021 , H01L27/101 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/14 , H01L45/146 , H01L45/147 , H01L45/149 , H01L45/16
摘要： A method of making a semiconductor device includes forming a first photoresist layer over an underlying layer, patterning the first photoresist layer into a first photoresist pattern, wherein the first photoresist pattern comprises a plurality of spaced apart first photoresist features located over the underlying layer, and etching the underlying layer using the first photoresist pattern as a mask to form a plurality of first spaced apart features. The method further includes removing the first photoresist pattern, forming a second photoresist layer over the plurality of first spaced apart features, and patterning the second photoresist layer into a second photoresist pattern, wherein the second photoresist pattern comprises a plurality of second photoresist features covering edge portions of the plurality of first spaced apart features. The method also includes etching exposed portions of the plurality of first spaced apart features using the second photoresist pattern as a mask, such that a plurality of spaced apart edge portions of the plurality of first spaced apart features remain, and removing the second photoresist pattern.
摘要翻译：制造半导体器件的方法包括在下层上形成第一光致抗蚀剂层，将第一光致抗蚀剂层图案化为第一光致抗蚀剂图案，其中第一光致抗蚀剂图案包括位于下层之上的多个间隔开的第一光致抗蚀剂特征，以及使用第一光致抗蚀剂图案作为掩模蚀刻下层，以形成多个第一间隔的特征。该方法还包括去除第一光致抗蚀剂图案，在多个第一间隔开的特征上形成第二光致抗蚀剂层，以及将第二光致抗蚀剂层图案化为第二光致抗蚀剂图案，其中第二光致抗蚀剂图案包括多个第二光致抗蚀剂特征，多个第一间隔开的特征部分。该方法还包括使用第二光致抗蚀剂图案作为掩模蚀刻多个第一间隔开的特征的暴露部分，使得多个第一间隔开的特征中的多个间隔开的边缘部分保留，并且去除第二光致抗蚀剂图案。

8. 发明申请

US20110171809A1 METHOD FOR FABRICATING HIGH DENSITY PILLAR STRUCTURES BY DOUBLE PATTERNING USING POSITIVE PHOTORESIST 有权
标题翻译：使用正电子照相机双重方式制作高密度立柱结构的方法
公开(公告)号：US20110171809A1
公开(公告)日：2011-07-14
申请号：US13070825
申请日：2011-03-24
申请人： Roy E. Scheuerlein , Steven Radigan
发明人： Roy E. Scheuerlein , Steven Radigan
IPC分类号： H01L45/00 , H01L21/302
CPC分类号： H01L27/1021 , H01L27/101 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/14 , H01L45/146 , H01L45/147 , H01L45/149 , H01L45/16
摘要： A method of making a semiconductor device includes forming a first photoresist layer over an underlying layer, patterning the first photoresist layer into a first photoresist pattern, wherein the first photoresist pattern comprises a plurality of spaced apart first photoresist features located over the underlying layer, and etching the underlying layer using the first photoresist pattern as a mask to form a plurality of first spaced apart features. The method further includes removing the first photoresist pattern, forming a second photoresist layer over the plurality of first spaced apart features, and patterning the second photoresist layer into a second photoresist pattern, wherein the second photoresist pattern comprises a plurality of second photoresist features covering edge portions of the plurality of first spaced apart features. The method also includes etching exposed portions of the plurality of first spaced apart features using the second photoresist pattern as a mask, such that a plurality of spaced apart edge portions of the plurality of first spaced apart features remain, and removing the second photoresist pattern.
摘要翻译：制造半导体器件的方法包括在下层上形成第一光致抗蚀剂层，将第一光致抗蚀剂层图案化为第一光致抗蚀剂图案，其中第一光致抗蚀剂图案包括位于下层之上的多个间隔开的第一光致抗蚀剂特征，以及使用第一光致抗蚀剂图案作为掩模蚀刻下层，以形成多个第一间隔的特征。该方法还包括去除第一光致抗蚀剂图案，在多个第一间隔开的特征上形成第二光致抗蚀剂层，以及将第二光致抗蚀剂层图案化为第二光致抗蚀剂图案，其中第二光致抗蚀剂图案包括覆盖边缘多个第一间隔开的特征部分。该方法还包括使用第二光致抗蚀剂图案作为掩模蚀刻多个第一间隔开的特征的暴露部分，使得多个第一间隔开的特征中的多个间隔开的边缘部分保留，并且去除第二光致抗蚀剂图案。

9. 发明授权

US07732235B2 Method for fabricating high density pillar structures by double patterning using positive photoresist 有权
标题翻译：通过使用正性光致抗蚀剂的双重图案制造高密度柱结构的方法
公开(公告)号：US07732235B2
公开(公告)日：2010-06-08
申请号：US12216108
申请日：2008-06-30
申请人： Roy E. Scheuerlein , Steven Radigan
发明人： Roy E. Scheuerlein , Steven Radigan
IPC分类号： H01L21/00
CPC分类号： H01L27/1021 , H01L27/101 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/14 , H01L45/146 , H01L45/147 , H01L45/149 , H01L45/16
摘要： A method of making a semiconductor device includes forming a first photoresist layer over an underlying layer, patterning the first photoresist layer into a first photoresist pattern, wherein the first photoresist pattern comprises a plurality of spaced apart first photoresist features located over the underlying layer, and etching the underlying layer using the first photoresist pattern as a mask to form a plurality of first spaced apart features. The method further includes removing the first photoresist pattern, forming a second photoresist layer over the plurality of first spaced apart features, and patterning the second photoresist layer into a second photoresist pattern, wherein the second photoresist pattern comprises a plurality of second photoresist features covering edge portions of the plurality of first spaced apart features. The method also includes etching exposed portions of the plurality of first spaced apart features using the second photoresist pattern as a mask, such that a plurality of spaced apart edge portions of the plurality of first spaced apart features remain, and removing the second photoresist pattern.
摘要翻译：制造半导体器件的方法包括在下层上形成第一光致抗蚀剂层，将第一光致抗蚀剂层图案化为第一光致抗蚀剂图案，其中第一光致抗蚀剂图案包括位于下层之上的多个间隔开的第一光致抗蚀剂特征，以及使用第一光致抗蚀剂图案作为掩模蚀刻下层，以形成多个第一间隔的特征。该方法还包括去除第一光致抗蚀剂图案，在多个第一间隔开的特征上形成第二光致抗蚀剂层，以及将第二光致抗蚀剂层图案化为第二光致抗蚀剂图案，其中第二光致抗蚀剂图案包括覆盖边缘多个第一间隔开的特征部分。该方法还包括使用第二光致抗蚀剂图案作为掩模蚀刻多个第一间隔开的特征的暴露部分，使得多个第一间隔开的特征中的多个间隔开的边缘部分保留，并且去除第二光致抗蚀剂图案。

10. 发明申请

US20080026510A1 NONVOLATILE MEMORY CELL COMPRISING A REDUCED HEIGHT VERTICAL DIODE 有权
标题翻译：包含降低高度垂直二极管的非易失性存储单元
公开(公告)号：US20080026510A1
公开(公告)日：2008-01-31
申请号：US11866403
申请日：2007-10-02
申请人： S. HERNER , Steven Radigan
发明人： S. HERNER , Steven Radigan
IPC分类号： H01L21/82
CPC分类号： G11C5/02 , G11C11/39 , G11C17/06 , G11C17/16 , G11C2213/71 , G11C2213/77 , H01L27/1021 , H01L29/0649 , H01L29/66272 , H01L29/732 , H01L29/868
摘要： A nonvolatile memory cell according to the present invention comprises a bottom conductor, a semiconductor pillar, and a top conductor. The semiconductor pillar comprises a junction diode, including a bottom heavily doped region, a middle intrinsic or lightly doped region, and a top heavily doped region, wherein the conductivity types of the top and bottom heavily doped region are opposite. The junction diode is vertically oriented and is of reduced height, between about 500 angstroms and about 3500 angstroms. A monolithic three dimensional memory array of such cells can be formed comprising multiple memory levels, the levels monolithically formed above one another.
摘要翻译：根据本发明的非易失性存储单元包括底部导体，半导体柱和顶部导体。半导体柱包括结二极管，其包括底部重掺杂区域，中间固有或轻掺杂区域和顶部重掺杂区域，其中顶部和底部重掺杂区域的导电类型相反。结二极管是垂直取向的，并且具有降低的高度，在约500埃至约3500埃之间。可以形成这样的单元的单片三维存储器阵列，其包括多个存储器级，电平彼此整体地形成。

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