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1. 发明授权

US08942050B2 Method of inspecting variable resistance nonvolatile memory device and variable resistance nonvolatile memory device 有权
标题翻译：检查可变电阻非易失性存储器件和可变电阻非易失性存储器件的方法
公开(公告)号：US08942050B2
公开(公告)日：2015-01-27
申请号：US13637428
申请日：2011-09-07
申请人： Hiroshi Tomotani , Kazuhiko Shimakawa , Ryotaro Azuma , Yoshikazu Katoh , Yuichiro Ikeda
发明人： Hiroshi Tomotani , Kazuhiko Shimakawa , Ryotaro Azuma , Yoshikazu Katoh , Yuichiro Ikeda
IPC分类号： G11C7/06 , G11C13/00 , G11C29/50
CPC分类号： G11C13/0007 , G11C13/00 , G11C13/003 , G11C29/50008 , G11C2213/15
摘要： A method of inspecting a variable resistance nonvolatile memory device detecting a faulty memory cell of a memory cell array employing a current steering element, and a variable resistance nonvolatile memory device are provided. The method of inspecting a variable resistance nonvolatile memory device having a memory cell array, a memory cell selection circuit, and a read circuit includes: determining that a current steering element has a short-circuit fault when a variable resistance element is in a low resistance state and a current higher than or equal to a predetermined current passes through the current steering element, when the resistance state of the memory cell is read using a second voltage; and determining whether the variable resistance element is in the low or high resistance state, when the resistance state of the memory cell is read using a first voltage.
摘要翻译：提供了检测使用电流导向元件的存储单元阵列的故障存储单元的可变电阻非易失性存储器件和可变电阻非易失性存储器件的方法。检查具有存储单元阵列的可变电阻非易失性存储器件，存储单元选择电路和读取电路的方法包括：当可变电阻元件处于低电阻时，确定当前的导向元件具有短路故障当使用第二电压读取存储单元的电阻状态时，高于或等于预定电流的电流通过电流导向元件; 以及当使用第一电压读取存储单元的电阻状态时，确定可变电阻元件是处于低电阻还是高电阻状态。

2. 发明申请

US20130021838A1 METHOD OF INSPECTING VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE AND VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE 有权
标题翻译：检测可变电阻非易失性存储器件和可变电阻非易失性存储器件的方法
公开(公告)号：US20130021838A1
公开(公告)日：2013-01-24
申请号：US13637428
申请日：2011-09-07
申请人： Hiroshi Tomotani , Kazuhiko Shimakawa , Ryotaro Azuma , Yoshikazu Katoh , Yuichiro Ikeda
发明人： Hiroshi Tomotani , Kazuhiko Shimakawa , Ryotaro Azuma , Yoshikazu Katoh , Yuichiro Ikeda
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/00 , G11C13/003 , G11C29/50008 , G11C2213/15
摘要： A method of inspecting a variable resistance nonvolatile memory device detecting a faulty memory cell of a memory cell array employing a current steering element, and a variable resistance nonvolatile memory device are provided. The method of inspecting a variable resistance nonvolatile memory device having a memory cell array, a memory cell selection circuit, and a read circuit includes: determining that a current steering element has a short-circuit fault when a variable resistance element is in a low resistance state and a current higher than or equal to a predetermined current passes through the current steering element, when the resistance state of the memory cell is read using a second voltage; and determining whether the variable resistance element is in the low or high resistance state, when the resistance state of the memory cell is read using a first voltage.
摘要翻译：提供了检测使用电流导向元件的存储单元阵列的故障存储单元的可变电阻非易失性存储器件和可变电阻非易失性存储器件的方法。检查具有存储单元阵列的可变电阻非易失性存储器件，存储单元选择电路和读取电路的方法包括：当可变电阻元件处于低电阻时，确定当前的导向元件具有短路故障当使用第二电压读取存储单元的电阻状态时，高于或等于预定电流的电流通过电流导向元件; 以及当使用第一电压读取存储单元的电阻状态时，确定可变电阻元件是处于低电阻还是高电阻状态。

3. 发明申请

US20130077384A1 CROSS POINT VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE AND METHOD OF READING THEREBY 有权
标题翻译：交叉点可变电阻非易失性存储器件及其读取方法
公开(公告)号：US20130077384A1
公开(公告)日：2013-03-28
申请号：US13636169
申请日：2012-04-27
申请人： Ryotaro Azuma , Kazuhiko Shimakawa , Yoshikazu Katoh
发明人： Ryotaro Azuma , Kazuhiko Shimakawa , Yoshikazu Katoh
IPC分类号： G11C11/21
CPC分类号： G11C11/21 , G11C8/08 , G11C13/00 , G11C13/0007 , G11C13/0023 , G11C13/0028 , G11C13/004 , G11C2213/15 , G11C2213/71
摘要： A cross point variable resistance nonvolatile memory device including: a cross point memory cell array having memory cells each of which is placed at a different one of cross points of bit lines and word lines; a word line decoder circuit that selects at least one of the memory cells from the memory cell array; a read circuit that reads data from the selected memory cell; an unselected word line current source that supplies a first constant current; and a control circuit that controls the reading of the data from the selected memory cell, wherein the control circuit controls the word line decoder circuit, the read circuit, and the unselected word line current source so that when the read circuit reads data, the first constant current is supplied to an unselected word line.
摘要翻译：一种交叉点可变电阻非易失性存储器件，包括：具有存储单元的交叉点存储单元阵列，每个存储单元位于位线和字线的交叉点的不同位置; 字线解码器电路，从存储单元阵列中选择至少一个存储单元; 从所选择的存储单元读取数据的读取电路; 提供第一恒定电流的未选字线电流源; 以及控制电路，其控制来自所选择的存储单元的数据的读取，其中所述控制电路控制所述字线解码器电路，所述读取电路和所述未选字线电流源，使得当所述读取电路读取数据时，所述第一恒定电流被提供给未选择的字线。

4. 发明授权

US08982603B2 Cross point variable resistance nonvolatile memory device and method of reading thereby 有权
标题翻译：交叉点可变电阻非易失性存储器件及其读取方法
公开(公告)号：US08982603B2
公开(公告)日：2015-03-17
申请号：US13636169
申请日：2012-04-27
申请人： Ryotaro Azuma , Kazuhiko Shimakawa , Yoshikazu Katoh
发明人： Ryotaro Azuma , Kazuhiko Shimakawa , Yoshikazu Katoh
IPC分类号： G11C11/00 , G11C11/21 , G11C13/00
CPC分类号： G11C11/21 , G11C8/08 , G11C13/00 , G11C13/0007 , G11C13/0023 , G11C13/0028 , G11C13/004 , G11C2213/15 , G11C2213/71
摘要： A cross point variable resistance nonvolatile memory device including: a cross point memory cell array having memory cells each of which is placed at a different one of cross points of bit lines and word lines; a word line decoder circuit that selects at least one of the memory cells from the memory cell array; a read circuit that reads data from the selected memory cell; an unselected word line current source that supplies a first constant current; and a control circuit that controls the reading of the data from the selected memory cell, wherein the control circuit controls the word line decoder circuit, the read circuit, and the unselected word line current source so that when the read circuit reads data, the first constant current is supplied to an unselected word line.
摘要翻译：一种交叉点可变电阻非易失性存储器件，包括：具有存储单元的交叉点存储单元阵列，每个存储单元位于位线和字线的交叉点的不同位置; 字线解码器电路，从存储单元阵列中选择至少一个存储单元; 从所选择的存储单元读取数据的读取电路; 提供第一恒定电流的未选字线电流源; 以及控制电路，其控制来自所选择的存储单元的数据的读取，其中所述控制电路控制所述字线解码器电路，所述读取电路和所述未选字线电流源，使得当所述读取电路读取数据时，所述第一恒定电流被提供给未选择的字线。

5. 发明申请

US20130223133A1 CROSS POINT VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE AND METHOD OF WRITING THEREBY 有权
标题翻译：交叉点可变电阻非易失性存储器件及其写入方法
公开(公告)号：US20130223133A1
公开(公告)日：2013-08-29
申请号：US13883785
申请日：2012-09-06
申请人： Ryotaro Azuma , Kazuhiko Shimakawa , Yoshikazu Katoh
发明人： Ryotaro Azuma , Kazuhiko Shimakawa , Yoshikazu Katoh
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C11/5685 , G11C13/0007 , G11C13/0023 , G11C2013/0073 , G11C2013/0088
摘要： A cross point variable nonvolatile memory device includes a memory cell array including: first memory cells (e.g., part of a memory cell array) having a common word line; and second memory cells (e.g., another part of the memory cell array or a compensation cell unit). When a predetermined memory cell among the first memory cells is written to by changing the predetermined memory cell to a first resistance state, a word line write circuit supplies a first voltage or a first current to a selected word line, a first bit line write circuit supplies a third voltage or a third current to one bit line of the first memory cells, and a second bit line write circuit supplies the third voltage or the third current to A bit line or lines of the second memory cells.
摘要翻译：交叉点可变非易失性存储器件包括存储单元阵列，其包括：具有公共字线的第一存储器单元（例如，存储单元阵列的一部分）; 和第二存储单元（例如，存储单元阵列的另一部分或补偿单元单元）。当通过将预定存储单元改变为第一电阻状态来将第一存储单元中的预定存储单元写入时，字线写入电路向所选字线提供第一电压或第一电流，第一位线写入电路向第一存储器单元的一个位线提供第三电压或第三电流，并且第二位线写入电路将第三电压或第三电流提供给第二存储器单元的A位线或第二行。

6. 发明授权

US08687409B2 Variable resistance nonvolatile memory device 有权
标题翻译：可变电阻非易失性存储器件
公开(公告)号：US08687409B2
公开(公告)日：2014-04-01
申请号：US13639120
申请日：2012-05-30
申请人： Yuichiro Ikeda , Kazuhiko Shimakawa , Ryotaro Azuma , Ken Kawai
发明人： Yuichiro Ikeda , Kazuhiko Shimakawa , Ryotaro Azuma , Ken Kawai
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0007 , G11C2013/0083 , G11C2213/32 , G11C2213/72
摘要： A variable resistance nonvolatile memory device including memory cells provided at cross-points of first signal lines and second signal lines, each memory cell including a variable resistance element and a current steering element connected to the variable resistance element in series, the variable resistance nonvolatile memory device including a write circuit, a row selection circuit, and a column selection circuit, wherein the write circuit: sequentially selects blocks in an order starting from a block farthest from at least one of the row selection circuit and the column selection circuit and finishing with a block closest to the at least one of the row selection circuit and the column selection circuit; and performs, for each of the selected blocks, initial breakdown on each memory cell included in the selected block.
摘要翻译：一种可变电阻非易失性存储器件，包括设置在第一信号线和第二信号线的交叉点处的存储单元，每个存储单元包括可变电阻元件和连接到可变电阻元件串联的电流操舵元件，可变电阻非易失性存储器包括写入电路，行选择电路和列选择电路的装置，其中写入电路：从与行选择电路和列选择电路中的至少一个最远的块开始的顺序顺序地选择块，并且以最靠近行选择电路和列选择电路中的至少一个的块; 并且对于每个所选择的块，对包括在所选择的块中的每个存储器单元执行初始故障。

7. 发明授权

US09087581B2 Cross point variable resistance nonvolatile memory device and method of writing thereby 有权
标题翻译：交叉点可变电阻非易失性存储器件及其写入方法
公开(公告)号：US09087581B2
公开(公告)日：2015-07-21
申请号：US13883785
申请日：2012-09-06
申请人： Ryotaro Azuma , Kazuhiko Shimakawa , Yoshikazu Katoh
发明人： Ryotaro Azuma , Kazuhiko Shimakawa , Yoshikazu Katoh
IPC分类号： G11C11/00 , G11C13/00 , G11C11/56
CPC分类号： G11C13/0069 , G11C11/5685 , G11C13/0007 , G11C13/0023 , G11C2013/0073 , G11C2013/0088
摘要： A cross point variable nonvolatile memory device includes a memory cell array including: first memory cells (e.g., part of a memory cell array) having a common word line; and second memory cells (e.g., another part of the memory cell array or a compensation cell unit). When a predetermined memory cell among the first memory cells is written to by changing the predetermined memory cell to a first resistance state, a word line write circuit supplies a first voltage or a first current to a selected word line, a first bit line write circuit supplies a third voltage or a third current to one bit line of the first memory cells, and a second bit line write circuit supplies the third voltage or the third current to A bit line or lines of the second memory cells.
摘要翻译：交叉点可变非易失性存储器件包括存储单元阵列，其包括：具有公共字线的第一存储器单元（例如，存储单元阵列的一部分）; 和第二存储单元（例如，存储单元阵列的另一部分或补偿单元单元）。当通过将预定存储单元改变为第一电阻状态来将第一存储单元中的预定存储单元写入时，字线写入电路向所选字线提供第一电压或第一电流，第一位线写入电路向第一存储器单元的一个位线提供第三电压或第三电流，并且第二位线写入电路将第三电压或第三电流提供给第二存储器单元的A位线或第二行。

8. 发明授权

US08467228B2 Variable resistance nonvolatile memory device 有权
标题翻译：可变电阻非易失性存储器件
公开(公告)号：US08467228B2
公开(公告)日：2013-06-18
申请号：US13496895
申请日：2011-08-10
申请人： Yuichiro Ikeda , Kazuhiko Shimakawa , Ryotaro Azuma
发明人： Yuichiro Ikeda , Kazuhiko Shimakawa , Ryotaro Azuma
IPC分类号： G11C11/00
CPC分类号： H01L27/101 , G11C13/004 , G11C2213/71 , G11C2213/72 , H01L27/0688 , H01L27/2409 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/146
摘要： Each of basic array planes has a first via group that interconnects only even-layer bit lines in the basic array plane, and a second via group that interconnects only odd-layer bit lines in the basic array plane, the first via group in a first basic array plane and the second via group in a second basic array plane adjacent to the first basic array in a Y direction are adjacent to each other in the Y direction, and the second via group in the first basic array plane and the first via group in the second basic array plane are adjacent to each other in the Y direction, and the second via group in the second basic array plane is disconnected from a second global line when connecting the first via group in the first basic array plane to a first global line.
摘要翻译：每个基本阵列平面具有仅在基本阵列平面中互连偶数位线的第一通孔组和仅在基本阵列平面中互连奇数位线的第二通孔组，第一通孔组在第一通孔组在Y方向上与第一基本阵列相邻的第二基本阵列平面中的基本阵列平面和第二通孔组在Y方向上彼此相邻，并且第一基本阵列平面中的第二通孔组和第一通孔组在第二基本阵列平面中在Y方向上彼此相邻，并且当将第一基本阵列平面中的第一通孔组连接到第一全局线阵列时，第二基本阵列平面中的第二通孔组与第二全局线断开连接线。

9. 发明申请

US20130114327A1 VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE 有权
标题翻译：可变电阻非易失性存储器件
公开(公告)号：US20130114327A1
公开(公告)日：2013-05-09
申请号：US13639120
申请日：2012-05-30
申请人： Yuichiro Ikeda , Kazuhiko Shimakawa , Ryotaro Azuma , Ken Kawai
发明人： Yuichiro Ikeda , Kazuhiko Shimakawa , Ryotaro Azuma , Ken Kawai
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0007 , G11C2013/0083 , G11C2213/32 , G11C2213/72
摘要： A variable resistance nonvolatile memory device including memory cells provided at cross-points of first signal lines and second signal lines, each memory cell including a variable resistance element and a current steering element connected to the variable resistance element in series, the variable resistance nonvolatile memory device including a write circuit, a row selection circuit, and a column selection circuit, wherein the write circuit: sequentially selects blocks in an order starting from a block farthest from at least one of the row selection circuit and the column selection circuit and finishing with a block closest to the at least one of the row selection circuit and the column selection circuit; and performs, for each of the selected blocks, initial breakdown on each memory cell included in the selected block.
摘要翻译：一种可变电阻非易失性存储器件，包括设置在第一信号线和第二信号线的交叉点处的存储单元，每个存储单元包括可变电阻元件和连接到可变电阻元件串联的电流操舵元件，可变电阻非易失性存储器包括写入电路，行选择电路和列选择电路的装置，其中写入电路：从与行选择电路和列选择电路中的至少一个最远的块开始的顺序顺序地选择块，并且用最靠近行选择电路和列选择电路中的至少一个的块; 并且对于每个所选择的块，对包括在所选择的块中的每个存储器单元执行初始故障。

10. 发明授权

US08467229B2 Variable resistance nonvolatile memory device 有权
标题翻译：可变电阻非易失性存储器件
公开(公告)号：US08467229B2
公开(公告)日：2013-06-18
申请号：US13511787
申请日：2011-11-24
申请人： Yuichiro Ikeda , Kazuhiko Shimakawa , Ryotaro Azuma
发明人： Yuichiro Ikeda , Kazuhiko Shimakawa , Ryotaro Azuma
IPC分类号： G11C11/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/0026 , G11C13/004 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2436 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/146
摘要： In a nonvolatile memory device, basic array planes (0 to 3) have respective first via groups (121 to 124) that interconnect only even-layer bit lines in the basic array planes, and respective second via groups (131 to 134) that interconnect only odd-layer bit lines in the basic array planes, the first via group in a first basic array plane and the second via group in a second basic array plane adjacent to the first basic array plane in a Y direction are adjacent to each other in the Y direction, and the first via group in the second basic array plane is connected to an unselected-bit-line dedicated global bit line (GBL_NS) having a fixed potential when the first via group in the first basic array plane is connected to a first global bit line related to the first basic array plane.
摘要翻译：在非易失性存储器件中，基本阵列平面（0至3）具有各自的第一通孔组（121至124），其仅互连基本阵列平面中的偶数位线，以及相互连接的相应的第二通孔组（131至134）在基本阵列平面中只有奇数位线，在第一基本阵列平面中的第一通孔组和与Y方向上与第一基本阵列平面相邻的第二基本阵列平面中的第二通孔组彼此相邻， Y方向和第二基本阵列平面中的第一通孔组连接到具有固定电位的未选择位线专用全局位线（GBL_NS），当第一基本阵列平面中的第一通孔组连接到与第一个基本阵列平面相关的第一个全局位线。

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