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    • 1. 发明申请
    • CODED SIGNAL REPRODUCTION APPARATUS
    • 编码信号再现装置
    • US20090257735A1
    • 2009-10-15
    • US12486279
    • 2009-06-17
    • Ryoji YAMAGUCHIEiji Miyagoshi
    • Ryoji YAMAGUCHIEiji Miyagoshi
    • H04N5/91
    • H04N21/4347H04J3/0608H04N19/70H04N21/236H04N21/4305H04N21/434
    • A formatter 2s13 is provided and, when a code sequence which matches a part (‘00’) of the head of a predetermined code sequence detected by a start code prefix detection unit 2s3, is detected, the start code prefix detection unit 2s3 detects the residual part (‘00’, ‘00’, ‘01’, ‘E0’) of the detected predetermined code sequence to detect a pattern of (‘00’, ‘00’, ‘00’), and the formatter 2s13 outputs one (‘00’). After the boundary of packets is defined, amongst data which are not transferred to a decoding buffer 2s9, data corresponding to code sequences other than the code sequence (‘00’, ‘00’, ‘01’, ‘E0’) indicating the packet boundary are output to the decoding buffer 2s9. Therefore, when separating a coded and multiplexed signal, control of an input buffer reading control circuit 2s4 is simplified, and thereby the hardware scale is reduced, resulting-in an inexpensive apparatus for reproducing a digital code sequence.
    • 提供格式化器2s13,并且当检测到与由起始码前缀检测单元2s3检测到的预定码序列的头部的部分('00')匹配的码序列时,起始码前缀检测单元2s3检测 检测到的预定码序列的残差部分('00','00','01','E0'),以检测('00','00','00')的模式,格式器2s13输出一个 ('00')。 在分组的边界被定义之后,在未传送到解码缓冲器2s9的数据中,对应于指示分组的代码序列('00','00','01','E0')之外的代码序列的数据 边界输出到解码缓冲器2s9。 因此,当分离编码和复用的信号时,简化了输入缓冲器读取控制电路2s4的控制,从而降低了硬件规模,从而导致用于再现数字代码序列的便宜的装置。
    • 2. 发明授权
    • Coded signal reproduction apparatus
    • 编码信号再生装置
    • US08649662B2
    • 2014-02-11
    • US12486279
    • 2009-06-17
    • Ryoji YamaguchiEiji Miyagoshi
    • Ryoji YamaguchiEiji Miyagoshi
    • H04N9/80H04N5/93
    • H04N21/4347H04J3/0608H04N19/70H04N21/236H04N21/4305H04N21/434
    • A formatter 2s13 is provided and, when a code sequence which matches a part (‘00’) of the head of a predetermined code sequence detected by a start code prefix detection unit 2s3, is detected, the start code prefix detection unit 2s3 detects the residual part (‘00’, ‘00’, ‘01’, ‘E0’) of the detected predetermined code sequence to detect a pattern of (‘00’, ‘00’, ‘00’), and the formatter 2s13 outputs one (‘00’). After the boundary of packets is defined, amongst data which are not transferred to a decoding buffer 2s9, data corresponding to code sequences other than the code sequence (‘00’, ‘00’, ‘01’, ‘E0’) indicating the packet boundary are output to the decoding buffer 2s9. Therefore, when separating a coded and multiplexed signal, control of an input buffer reading control circuit 2s4 is simplified, and thereby the hardware scale is reduced, resulting in an inexpensive apparatus for reproducing a digital code sequence.
    • 提供格式化器2s13,并且当检测到与由起始码前缀检测单元2s3检测到的预定码序列的头部的部分('00')匹配的码序列时,起始码前缀检测单元2s3检测 检测到的预定码序列的残差部分('00','00','01','E0'),以检测('00','00','00')的模式,格式器2s13输出一个 ('00')。 在分组的边界被定义之后,在未传送到解码缓冲器2s9的数据中,对应于指示分组的代码序列('00','00','01','E0')之外的代码序列的数据 边界输出到解码缓冲器2s9。 因此,当分离编码和复用的信号时,简化了输入缓冲器读取控制电路2s4的控制,从而降低了硬件规模,导致了用于再现数字代码序列的便宜的装置。
    • 3. 发明授权
    • Apparatus for reproduction of encoded signal
    • 用于再现编码信号的装置
    • US07809246B1
    • 2010-10-05
    • US09380187
    • 1998-12-28
    • Ryoji YamaguchiEiji Miyagoshi
    • Ryoji YamaguchiEiji Miyagoshi
    • H04N7/26
    • H04N21/4347H04J3/0608H04N19/70H04N21/236H04N21/4305H04N21/434
    • A formatter is provided and, when a code sequence which matches a part (‘00’) of the head of a predetermined code sequence detected by a start code prefix detection unit, is detected, the start code prefix detection unit detects the residual part (‘00’, ‘00’, ‘01’, ‘E0’) of the detected predetermined code sequence to detect a pattern of (‘00’, ‘00’, ‘00’), and the formatter outputs one (‘00’). After the boundary of packets is defined, amongst data which are not transferred to a decoding buffer, data corresponding to code sequences other than the code sequence (‘00’, ‘00’, ‘01’, ‘E0’) indicating that the packet boundary are output to the decoding buffer. Therefore, when separating a coded and multiplexed signal, control of an input buffer reading control circuit is simplified, and thereby the hardware scale is reduced, resulting in an inexpensive apparatus for reproducing a digital code sequence.
    • 提供格式化器,并且当检测到与由起始码前缀检测单元检测到的预定码序列的头部的部分('00')匹配的码序列时,起始码前缀检测单元检测残留部分 '00','00','00','01','E0'),以检测('00','00','00')的模式,并且格式化器输出一个('00' )。 在定义分组边界之后,在不传送到解码缓冲器的数据中,对应于代码序列('00','00','01','E0')之外的代码序列的数据指示分组 边界输出到解码缓冲器。 因此,当分离编码和复用的信号时,简化了输入缓冲器读取控制电路的控制,从而降低了硬件规模,导致了用于再现数字代码序列的廉价的装置。
    • 5. 发明授权
    • Video encoding apparatus and method
    • 视频编码装置及方法
    • US6137838A
    • 2000-10-24
    • US7069
    • 1998-01-14
    • Eiji MiyagoshiAkihiro Watabe
    • Eiji MiyagoshiAkihiro Watabe
    • H04N7/26H04N7/50
    • H04N19/423H04N19/124H04N19/152H04N19/176H04N19/61H04N19/91H04N19/149H04N19/15
    • The present invention provides a video encoding apparatus including a video processor for performing video processing on input video data, a variable length encoder for performing variable length encoding on the processed (quantized) video data and for supplying the encoded data and a generated bit quantity, a DRAM for storing the encoded data that is output as a bitstream, a bitstream output circuit for computing, based on a value found by subtracting the generated bit quantity from a set bit quantity predetermined in advance, a period taken to read from the DRAM the bitstream and for outputting the bitstream as output video data in the computed period, and an arbiter for controlling the operations of the video processor, the variable length encoder, the DRAM, and the bitstream output circuit.
    • 本发明提供一种包括用于对输入视频数据执行视频处理的视频处理器的视频编码装置,用于对经处理的(量化的)视频数据执行可变长度编码并提供编码数据和生成的比特量的可变长度编码器, 用于存储作为比特流输出的编码数据的DRAM,用于基于从预先预定的设定比特量中减去所生成的比特量而得到的值,计算从DRAM读取的周期的比特流输出电路 并且用于在计算的周期中输出比特流作为输出视频数据,以及用于控制视频处理器,可变长度编码器,DRAM和比特流输出电路的操作的仲裁器。
    • 7. 发明授权
    • Variable-length encoder
    • 可变长度编码器
    • US06741651B1
    • 2004-05-25
    • US09600573
    • 2000-07-19
    • Akihiro WatabeEiji Miyagoshi
    • Akihiro WatabeEiji Miyagoshi
    • H04N712
    • H03M7/40H04N19/13H04N19/132H04N19/15H04N19/577H04N19/587H04N19/61H04N19/91
    • A variable length encoding apparatus such as an encoding apparatus using the MPEG standard, wherein without degrading the precision of quantization step, the generated code bit amount is limited. Encoding is performed at the quantization step of required picture quality by an encoding part 106, and a bit stream 141 is written in an external memory 101. The generated encoded bit amount is measured from the increment of a write pointer 121 increased because of the writing in the external memory 101 by a control unit 107. If the amount is larger than a preset value, the data is replaced with data leading to the same decoding result as those of the preceding or following reference picture by using a replacement pattern in accordance with the picture type and the position on a times series, and the data is written in the external memory 101, thus outputting the data as an output bit stream 111 controlled to the generated code amount within an upper limit value.
    • 诸如使用MPEG标准的编码装置的可变长度编码装置,其中在不降低量化步长的精度的情况下,限制了所生成的码位数量。 通过编码部分106在所需图像质量的量化步骤进行编码,并且将比特流141写入外部存储器101.所生成的编码比特量由写入指针121的增量而被增加,因为写入 通过控制单元107在外部存储器101中。如果该量大于预设值,则数据被替换为导致与先前或后续参考图片相同的解码结果的数据,通过使用根据 图像类型和时间序列上的位置,并且将数据写入外部存储器101,从而将控制为生成代码量的输出比特流111作为上限值输出。
    • 8. 发明授权
    • Image information decoder with a reduced capacity frame memory
    • 具有减少容量帧存储器的图像信息解码器
    • US6064803A
    • 2000-05-16
    • US609020
    • 1996-02-29
    • Akihiro WatabeEiji MiyagoshiYoshiyuki GoiWilliam Brent Wilson
    • Akihiro WatabeEiji MiyagoshiYoshiyuki GoiWilliam Brent Wilson
    • G06T9/00G06F15/00G06K9/36
    • G06T9/007
    • The present invention discloses an MPEG decoder for reproducing moving picture data. A first frame memory (FM0) and a second frame memory (FM1), each of which is composed of 2N slots, are provided. A third frame memory (FM2) is provided which is composed of N+4 slots. Each slot is provided with a memory capacity of eight lines. FM0 and FM1 each have a 1-frame memory capacity for storing reference frames for motion compensation. FM2, on the other hand, has a memory capacity of half a frame+32 lines for B-PICTURE interlace conversion. A slot control memory (SM) is further provided which is composed of 2N+6 words each of which stores a respective slot number of FM2. For an output section to read the slots of FM2 in the correct order, the contents of SM are updated by an control section at the time of the writing of FM2 by a decoding section.
    • 本发明公开了一种用于再现运动图像数据的MPEG解码器。 提供由2N个时隙构成的第一帧存储器(FM0)和第二帧存储器(FM1)。 提供由N + 4个时隙组成的第三帧存储器(FM2)。 每个插槽提供八行的存储容量。 FM0和FM1每个都具有1帧存储器容量,用于存储用于运动补偿的参考帧。 另一方面,FM2对于B-PICTURE隔行转换具有半帧+ 32行的存储容量。 还提供了一个时隙控制存储器(SM),其由2N + 6个字组成,每个字存储FM2的相应时隙号。 对于以正确的顺序读取FM2的时隙的输出部分,在由解码部分写入FM2时,由控制部分更新SM的内容。