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1. 发明申请

US20060153290A1 Code conversion method and device thereof 有权
标题翻译：代码转换方法及其装置
公开(公告)号：US20060153290A1
公开(公告)日：2006-07-13
申请号：US10541221
申请日：2004-02-02
申请人： Akihiro Watabe , Noboru Mizuguchi , Eiji Miyagoshi , Takayuki Morishige
发明人： Akihiro Watabe , Noboru Mizuguchi , Eiji Miyagoshi , Takayuki Morishige
IPC分类号： H04N11/04 , H04N11/02 , H04N7/12 , H04B1/66
CPC分类号： H04N21/23406 , H04N21/44004
摘要： In order to cope with format conversion of user data, the bit rate value and VBV (Video Buffering Verifier) buffer size value in a sequence header of an input code and the VBV delay value in a picture header of the input code are modified to obtain an intermediate code (305 to 309), and additional information (300) is generated for distinguishing GOP (Group of Pictures) user data (307) from the other main data. A VBV buffer simulation is performed using this additional information (300) to multiplex the GOP user data in a picture user data region to a data amount such that the operation does not fail, whereby an output code is generated.
摘要翻译：为了应对用户数据的格式转换，对输入代码的序列标题中的比特率值和VBV（视频缓冲验证器）缓冲器大小值以及输入代码的图像头中的VBV延迟值进行修改以获得生成中间代码（305〜309）和附加信息（300），用于区分GOP（图片组）用户数据（307）与其他主数据。使用该附加信息（300）执行VBV缓冲器模拟，以将图像用户数据区域中的GOP用户数据复用到数据量，使得该操作不失败，由此产生输出代码。

2. 发明授权

US06597810B1 Image processor 有权
标题翻译：图像处理
公开(公告)号：US06597810B1
公开(公告)日：2003-07-22
申请号：US09463945
申请日：2000-02-07
申请人： Takayuki Morishige
发明人： Takayuki Morishige
IPC分类号： G06K936
CPC分类号： G06T1/20 , H04N19/42 , H04N19/423 , H04N19/61
摘要： An image processing device having a plurality of cores which attains more efficient memory access than conventionally attained. In the image processing device employing pipeline processing, a memory access section 20 executes data transfer between an operation section 10 including a plurality of cores each performing operation for image processing and an external memory 2. The memory access section 20 has an access schedule storage portion 22 which stores types of data transfers per stage, and executes data transfer between the operation section 10 and the external memory 2 in accordance with the storage contents of the access schedule storage portion 22. A system control section 30 sets the types of data transfers in the access schedule storage portion 22 at a stage preceding the stage at which the data transfers are executed. This makes it possible to change the types of data transfers with stages flexibly and thus allows the memory access section 20 to execute only necessary data transfers at each stage without the necessity of arbitration.
摘要翻译：一种具有多个核的图像处理装置，其获得比传统获得的更有效的存储器访问。在采用流水线处理的图像处理装置中，存储器访问部分20执行包括执行图像处理操作的多个核心的操作部分10和外部存储器2之间的数据传送。存储器访问部分20具有访问调度存储部分 22，其存储每级的数据传输类型，并且根据访问调度存储部分22的存储内容在操作部分10和外部存储器2之间执行数据传送。系统控制部分30将数据传输的类型访问调度存储部分22在执行数据传送的阶段之前的阶段。这使得可以灵活地分阶段地改变数据传输的类型，从而允许存储器访问部分20在每个阶段仅执行必要的数据传输，而不需要仲裁。

3. 发明授权

US07940799B2 Code conversion method and device thereof 有权
标题翻译：代码转换方法及其装置
公开(公告)号：US07940799B2
公开(公告)日：2011-05-10
申请号：US10541221
申请日：2004-02-02
申请人： Akihiro Watabe , Noboru Mizuguchi , Eiji Miyagoshi , Takayuki Morishige
发明人： Akihiro Watabe , Noboru Mizuguchi , Eiji Miyagoshi , Takayuki Morishige
IPC分类号： H04J3/24
CPC分类号： H04N21/23406 , H04N21/44004
摘要： In order to cope with format conversion of user data, the bit rate value and VBV (Video Buffering Verifier) buffer size value in a sequence header of an input code and the VBV delay value in a picture header of the input code are modified to obtain an intermediate code (305 to 309), and additional information (300) is generated for distinguishing GOP (Group of Pictures) user data (307) from the other main data. A VBV buffer simulation is performed using this additional information (300) to multiplex the GOP user data in a picture user data region to a data amount such that the operation does not fail, whereby an output code is generated.
摘要翻译：为了应对用户数据的格式转换，对输入代码的序列标题中的比特率值和VBV（视频缓冲验证器）缓冲器大小值以及输入代码的图像头中的VBV延迟值进行修改以获得生成中间代码（305〜309）和附加信息（300），用于区分GOP（图片组）用户数据（307）与其他主数据。使用该附加信息（300）执行VBV缓冲器模拟，以将图像用户数据区域中的GOP用户数据复用到数据量，使得该操作不失败，由此产生输出代码。

4. 发明授权

US07739437B2 Access arbiter and arbitrable condition verification device 有权
标题翻译：访问仲裁和可仲裁条件验证设备
公开(公告)号：US07739437B2
公开(公告)日：2010-06-15
申请号：US11883366
申请日：2006-01-26
申请人： Akihiro Watabe , Takayuki Morishige , Yuichiro Aihara
发明人： Akihiro Watabe , Takayuki Morishige , Yuichiro Aihara
IPC分类号： G06F12/00
CPC分类号： G06F13/1663 , G06F13/362
摘要： A priority control value, which is smaller as the priority of access by each of requesters is higher, decreases with the lapse of time when an access request is issued. When the access is completed, the priority control value increases by a priority decrease value (PERIOD). When there is no access request, the priority control value decreases to a reference priority value (TMIN) and is then maintained at the reference priority value. Access permission is given to the one of the requesters issuing requests which has the smallest priority control value. As a result, proper arbitration is performed at a high speed with a simple hardware configuration.
摘要翻译：随着每个请求者的访问优先级较小的优先级控制值较高，随着发出访问请求的时间的流逝而减小。当访问完成时，优先级控制值增加优先级降低值（PERIOD）。当没有访问请求时，优先级控制值减小到参考优先级值（TMIN），然后保持在参考优先级值。对发出具有最小优先级控制值的请求的请求者之一给予访问权限。结果，通过简单的硬件配置，高速执行适当的仲裁。

5. 发明申请

US20080263249A1 Access Arbiter and Arbitrable Condition Verification Device 有权
标题翻译：访问仲裁器和可仲裁条件验证设备
公开(公告)号：US20080263249A1
公开(公告)日：2008-10-23
申请号：US11883366
申请日：2006-01-26
申请人： Akihiro Watabe , Takayuki Morishige , Yuichiro Aihara
发明人： Akihiro Watabe , Takayuki Morishige , Yuichiro Aihara
IPC分类号： G06F13/30
CPC分类号： G06F13/1663 , G06F13/362
摘要： A priority control value, which is smaller as the priority of access by each of requesters is higher, decreases with the lapse of time when an access request is issued. When the access is completed, the priority control value increases by a priority decrease value (PERIOD). When there is no access request, the priority control value decreases to a reference priority value (TMIN) and is then maintained at the reference priority value. Access permission is given to the one of the requesters issuing requests which has the smallest priority control value. As a result, proper arbitration is performed at a high speed with a simple hardware configuration.
摘要翻译：随着每个请求者的访问优先级较小的优先级控制值较高，随着发出访问请求的时间的流逝而减小。当访问完成时，优先级控制值增加优先级降低值（PERIOD）。当没有访问请求时，优先级控制值减小到参考优先级值（TMIN），然后保持在参考优先级值。对发出具有最小优先级控制值的请求的请求者之一给予访问权限。结果，通过简单的硬件配置，高速执行适当的仲裁。

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