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    • 2. 发明授权
    • Video encoding apparatus and method
    • 视频编码装置及方法
    • US6137838A
    • 2000-10-24
    • US7069
    • 1998-01-14
    • Eiji MiyagoshiAkihiro Watabe
    • Eiji MiyagoshiAkihiro Watabe
    • H04N7/26H04N7/50
    • H04N19/423H04N19/124H04N19/152H04N19/176H04N19/61H04N19/91H04N19/149H04N19/15
    • The present invention provides a video encoding apparatus including a video processor for performing video processing on input video data, a variable length encoder for performing variable length encoding on the processed (quantized) video data and for supplying the encoded data and a generated bit quantity, a DRAM for storing the encoded data that is output as a bitstream, a bitstream output circuit for computing, based on a value found by subtracting the generated bit quantity from a set bit quantity predetermined in advance, a period taken to read from the DRAM the bitstream and for outputting the bitstream as output video data in the computed period, and an arbiter for controlling the operations of the video processor, the variable length encoder, the DRAM, and the bitstream output circuit.
    • 本发明提供一种包括用于对输入视频数据执行视频处理的视频处理器的视频编码装置,用于对经处理的(量化的)视频数据执行可变长度编码并提供编码数据和生成的比特量的可变长度编码器, 用于存储作为比特流输出的编码数据的DRAM,用于基于从预先预定的设定比特量中减去所生成的比特量而得到的值,计算从DRAM读取的周期的比特流输出电路 并且用于在计算的周期中输出比特流作为输出视频数据,以及用于控制视频处理器,可变长度编码器,DRAM和比特流输出电路的操作的仲裁器。
    • 4. 发明授权
    • Variable-length encoder
    • 可变长度编码器
    • US06741651B1
    • 2004-05-25
    • US09600573
    • 2000-07-19
    • Akihiro WatabeEiji Miyagoshi
    • Akihiro WatabeEiji Miyagoshi
    • H04N712
    • H03M7/40H04N19/13H04N19/132H04N19/15H04N19/577H04N19/587H04N19/61H04N19/91
    • A variable length encoding apparatus such as an encoding apparatus using the MPEG standard, wherein without degrading the precision of quantization step, the generated code bit amount is limited. Encoding is performed at the quantization step of required picture quality by an encoding part 106, and a bit stream 141 is written in an external memory 101. The generated encoded bit amount is measured from the increment of a write pointer 121 increased because of the writing in the external memory 101 by a control unit 107. If the amount is larger than a preset value, the data is replaced with data leading to the same decoding result as those of the preceding or following reference picture by using a replacement pattern in accordance with the picture type and the position on a times series, and the data is written in the external memory 101, thus outputting the data as an output bit stream 111 controlled to the generated code amount within an upper limit value.
    • 诸如使用MPEG标准的编码装置的可变长度编码装置,其中在不降低量化步长的精度的情况下,限制了所生成的码位数量。 通过编码部分106在所需图像质量的量化步骤进行编码,并且将比特流141写入外部存储器101.所生成的编码比特量由写入指针121的增量而被增加,因为写入 通过控制单元107在外部存储器101中。如果该量大于预设值,则数据被替换为导致与先前或后续参考图片相同的解码结果的数据,通过使用根据 图像类型和时间序列上的位置,并且将数据写入外部存储器101,从而将控制为生成代码量的输出比特流111作为上限值输出。
    • 5. 发明授权
    • Image information decoder with a reduced capacity frame memory
    • 具有减少容量帧存储器的图像信息解码器
    • US6064803A
    • 2000-05-16
    • US609020
    • 1996-02-29
    • Akihiro WatabeEiji MiyagoshiYoshiyuki GoiWilliam Brent Wilson
    • Akihiro WatabeEiji MiyagoshiYoshiyuki GoiWilliam Brent Wilson
    • G06T9/00G06F15/00G06K9/36
    • G06T9/007
    • The present invention discloses an MPEG decoder for reproducing moving picture data. A first frame memory (FM0) and a second frame memory (FM1), each of which is composed of 2N slots, are provided. A third frame memory (FM2) is provided which is composed of N+4 slots. Each slot is provided with a memory capacity of eight lines. FM0 and FM1 each have a 1-frame memory capacity for storing reference frames for motion compensation. FM2, on the other hand, has a memory capacity of half a frame+32 lines for B-PICTURE interlace conversion. A slot control memory (SM) is further provided which is composed of 2N+6 words each of which stores a respective slot number of FM2. For an output section to read the slots of FM2 in the correct order, the contents of SM are updated by an control section at the time of the writing of FM2 by a decoding section.
    • 本发明公开了一种用于再现运动图像数据的MPEG解码器。 提供由2N个时隙构成的第一帧存储器(FM0)和第二帧存储器(FM1)。 提供由N + 4个时隙组成的第三帧存储器(FM2)。 每个插槽提供八行的存储容量。 FM0和FM1每个都具有1帧存储器容量,用于存储用于运动补偿的参考帧。 另一方面,FM2对于B-PICTURE隔行转换具有半帧+ 32行的存储容量。 还提供了一个时隙控制存储器(SM),其由2N + 6个字组成,每个字存储FM2的相应时隙号。 对于以正确的顺序读取FM2的时隙的输出部分,在由解码部分写入FM2时,由控制部分更新SM的内容。
    • 9. 发明授权
    • Image processor
    • 图像处理器
    • US06356317B1
    • 2002-03-12
    • US08911919
    • 1997-08-15
    • Akihiro WatabeEiji Miyagoshi
    • Akihiro WatabeEiji Miyagoshi
    • H04N964
    • H04N19/427H04N19/423H04N19/61
    • A frame memory is provided which has five fields each having N slots, and three additional slots. Each slot has a storage capacity to store eight image lines. Four fields of the five fields serve to store motion compensation reference frames. The remaining one field and the three additional slots are used for B-picture interlace conversion. Disposed in a control unit are a slot control memory, a write slot pointer, and a read slot pointer. For an image output unit to acquire information from the frame memory in a correct slot order, the contents of the slot control memory are updated at the time of performing write operation to enter information into the frame memory by a bit stream analysis unit.
    • 提供了一个帧存储器,其具有五个场,每个场具有N个时隙,以及三个附加时隙。 每个插槽具有存储8个图像行的存储容量。 五个场中的四个场用于存储运动补偿参考帧。 剩余的一个场和三个附加时隙用于B图像交错转换。 设置在控制单元中的是时隙控制存储器,写槽指针和读槽指针。 对于图像输出单元,以正确的时隙顺序从帧存储器获取信息,在执行写入操作时更新时隙控制存储器的内容,以便通过比特流分析单元将信息输入到帧存储器中。