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    • 7. 发明申请
    • System and Method for Detecting a Defect
    • 检测缺陷的系统和方法
    • US20100138801A1
    • 2010-06-03
    • US12698201
    • 2010-02-02
    • Ryoichi MATSUOKAHidetoshi MorokumaTakumichi Sutani
    • Ryoichi MATSUOKAHidetoshi MorokumaTakumichi Sutani
    • G06F17/50
    • G06F17/5081G01R31/303
    • A system and a method for detecting a defect, capable of extracting a defect occurring depending on finishing accuracy required for circuit operation are provided. The system includes a timing analyzer for extracting a critical path in which a high accuracy is required for a signal transmission operation as compared with other portions based on circuit design data, a critical path extractor for comparing the circuit design data with layout design data on a pattern and for extracting graphical data including the critical path extracted by the timing analyzer, an inspection recipe creator for deciding a portion to be inspected, based on coordinate information on the graphical data including the critical path extracted by the critical path extractor, and an SEM defect review apparatus for acquiring an image of the decided portion to be inspected on a wafer according to an inspection recipe created by the inspection recipe creator.
    • 提供一种用于检测缺陷的系统和方法,其能够提取根据电路操作所需的精加工精度而发生的缺陷。 该系统包括用于提取与其他部分相比基于电路设计数据而与信号传输操作相比需要高精度的关键路径的定时分析器,用于将电路设计数据与布局设计数据进行比较的关键路径提取器 基于关于包括由关键路径提取器提取的关键路径的图形数据的坐标信息,以及扫描电子显微镜(SEM)来提取包括由定时分析器提取的关键路径的图形数据,用于决定待检查部分的检查配方生成器 缺陷检查装置,用于根据由检查配方创建者创建的检查配方在晶片上获取所确定的待检查部分的图像。
    • 9. 发明申请
    • PATTERN GENERATING APPARATUS AND PATTERN SHAPE EVALUATING APPARATUS
    • 图案生成装置和图案形状评估装置
    • US20090202139A1
    • 2009-08-13
    • US12366196
    • 2009-02-05
    • Yasutaka TOYODAHideo SAKAIRyoichi MATSUOKA
    • Yasutaka TOYODAHideo SAKAIRyoichi MATSUOKA
    • G06K9/00
    • G06K9/00G01R31/31813G06K9/6255G06T7/001G06T2207/30141
    • Although there has been a method for evaluating pattern shapes of electronic devices by using, as a reference pattern, design data or a non-defective pattern, the conventional method has a problem that the pattern shape cannot be evaluated with high accuracy because of the difficulty in defining an exact shape suitable for the manufacturing conditions of the electronic devices. The present invention provides a shape evaluation method for circuit patterns of electronic devices, the method including a means for generating contour distribution data of at least two circuit patterns from contour data sets on the circuit patterns; a means for generating a reference pattern used for the pattern shape evaluation, from the contour distribution data; and a means for evaluating the pattern shape by comparing each evaluation target pattern with the reference pattern.
    • 尽管通过使用设计数据或无缺陷图案作为参考图案来评估电子设备的图案形状的方法,但是由于难度而存在不能高精度地评估图案形状的问题 在定义适合于电子设备的制造条件的精确形状时。 本发明提供一种电子设备的电路图案的形状评估方法,该方法包括一种用于从电路图形上的轮廓数据集生成至少两个电路图案的轮廓分布数据的装置; 从轮廓分布数据生成用于图案形状评估的参考图案的装置; 以及用于通过将每个评估对象图案与参考图案进行比较来评估图案形状的装置。