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1. 发明授权

US06498518B1 Low input impedance line/bus receiver 失效
标题翻译：低输入阻抗线路/总线接收器
公开(公告)号：US06498518B1
公开(公告)日：2002-12-24
申请号：US09617680
申请日：2000-07-14
申请人： Russell J. Houghton , Jack A. Mandelman , Azzouz Nezar , Wilbur D. Pricer , William R. Tonti
发明人： Russell J. Houghton , Jack A. Mandelman , Azzouz Nezar , Wilbur D. Pricer , William R. Tonti
IPC分类号： H03K522
CPC分类号： H04L25/0292 , H03K5/24 , H03K19/017554
摘要： A current sensing circuit connected to a power supply terminal and having at least one input terminal and at least one output terminal includes at least one bipolar transistor having a base, emitter and collector, at least one current mirror amplifier connected to the power supply terminal, the current mirror amplifier having an input connected to the collector and having at least one output connected to the emitter, and a DC voltage source connected to the base.
摘要翻译：连接到电源端子并且具有至少一个输入端子和至少一个输出端子的电流感测电路包括至少一个具有基极，发射极和集电极的双极晶体管，连接到电源端子的至少一个电流镜放大器，所述电流镜放大器具有连接到所述集电极并且具有连接到所述发射极的至少一个输出的输入端和连接到所述基极的DC电压源。

2. 发明授权

US06436749B1 Method for forming mixed high voltage (HV/LV) transistors for CMOS devices using controlled gate depletion 失效
标题翻译：用于使用受控栅极耗尽的CMOS器件形成混合高压（HV / LV）晶体管的方法
公开(公告)号：US06436749B1
公开(公告)日：2002-08-20
申请号：US09658655
申请日：2000-09-08
申请人： William R. Tonti , Claude L. Bertin , Jeffrey P. Gambino , Russell J. Houghton , Jack A. Mandelman , Wilbur D. Pricer
发明人： William R. Tonti , Claude L. Bertin , Jeffrey P. Gambino , Russell J. Houghton , Jack A. Mandelman , Wilbur D. Pricer
IPC分类号： H01L218238
CPC分类号： H01L27/092 , H01L21/823842
摘要： A method for forming mixed high voltage/low voltage (HV/LV) transistors for CMOS devices is disclosed. In an exemplary embodiment, depletion of the gate conductor is controlled by leaving a fixed region of the gate conductor intrinsic, or lightly doped, thus separating the heavily doped low resistivity portion of the electrode with an intrinsic region by use of a conducting dopant barrier. The barrier is conductive in nature, but acts as a well-controlled diffusion barrier, stopping the “fast” diffusion which normally takes place in polysilicon, and eliminating diffusion between the conductors. Thereby, the device performance may be precisely predicted by carefully controlling the gate conductor thickness.
摘要翻译：公开了一种用于形成用于CMOS器件的混合高压/低压（HV / LV）晶体管的方法。在示例性实施例中，通过将栅极导体的固定区域固有或轻掺杂来控制栅极导体的耗尽，从而通过使用导电掺杂剂屏障将本征区域的重掺杂低电阻率部分与本征区域分离。阻挡层本质上是导电的，但是作为良好控制的扩散屏障，停止通常在多晶硅中发生的“快速”扩散，并消除导体之间的扩散。因此，可以通过仔细地控制栅极导体厚度来精确地预测器件性能。

3. 发明授权

US06790722B1 Logic SOI structure, process and application for vertical bipolar transistor 有权
标题翻译：逻辑SOI结构，工艺和应用于垂直双极晶体管
公开(公告)号：US06790722B1
公开(公告)日：2004-09-14
申请号：US09718850
申请日：2000-11-22
申请人： Ramachandra Divakaruni , Russell J. Houghton , Jack A. Mandelman , Wilbur D. Pricer , William R. Tonti
发明人： Ramachandra Divakaruni , Russell J. Houghton , Jack A. Mandelman , Wilbur D. Pricer , William R. Tonti
IPC分类号： H01L218238
CPC分类号： H01L29/66265 , H01L21/8249 , H01L27/0623 , H01L29/7317
摘要： A method and structure for forming an emitter in a vertical bipolar transistor includes providing a substrate having a collector layer and a base layer over the collector layer, forming a patterning mask over the collector layer, and filling openings in the mask with emitter material in a damascene process. The CMOS/vertical bipolar structure has the collector, base regions, and emitter regions vertically disposed on one another, the collector region having a peak dopant concentration adjacent the inter-substrate isolation oxide.
摘要翻译：用于在垂直双极晶体管中形成发射极的方法和结构包括在集电极层上提供具有集电极层和基极层的衬底，在集电极层上形成图案掩模，并在发光体材料中填充掩模中的开口大马士革过程。 CMOS /垂直双极结构具有彼此垂直设置的集电极，基极区域和发射极区域，集电极区域具有与衬底间隔离氧化物相邻的峰值掺杂剂浓度。

4. 发明授权

US06972220B2 Structures and methods of anti-fuse formation in SOI 失效
标题翻译： SOI中抗熔丝形成的结构和方法
公开(公告)号：US06972220B2
公开(公告)日：2005-12-06
申请号：US10366298
申请日：2003-02-12
申请人： Claude L. Bertin , Ramachandra Divakaruni , Russell J. Houghton , Jack A. Mandelman , William R. Tonti
发明人： Claude L. Bertin , Ramachandra Divakaruni , Russell J. Houghton , Jack A. Mandelman , William R. Tonti
IPC分类号： H01L21/82 , H01L21/334 , H01L23/525 , H01L27/108 , H01L27/12 , H01L21/00
CPC分类号： H01L23/5252 , H01L27/10829 , H01L27/10897 , H01L27/1203 , H01L29/66181 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An anti-fuse structure that can be programmed at low voltage and current and which potentially consumes very little chip spaces and can be formed interstitially between elements spaced by a minimum lithographic feature size is formed on a composite substrate such as a silicon-on-insulator wafer by etching a contact through an insulator to a support semiconductor layer, preferably in combination with formation of a capacitor-like structure reaching to or into the support layer. The anti-fuse may be programmed either by the selected location of conductor formation and/or damaging a dielectric of the capacitor-like structure. An insulating collar is used to surround a portion of either the conductor or the capacitor-like structure to confine damage to the desired location. Heating effects voltage and noise due to programming currents are effectively isolated to the bulk silicon layer, permitting programming during normal operation of the device. Thus the potential for self-repair without interruption of operation is realized.
摘要翻译：可以在低电压和电流下被编程并且潜在地消耗很少的芯片空间并且可以间隙地在间隔最小光刻特征尺寸的元件之间形成的反熔丝结构形成在复合衬底上，例如绝缘体上硅通过蚀刻通过绝缘体的接触到支撑半导体层，优选结合形成到达或支撑层的电容器状结构。反熔丝可以由导体形成的选定位置和/或损坏电容器状结构的电介质来编程。绝缘环用于围绕导体或电容器状结构的一部分，以将损伤限制在所需位置。由于编程电流导致的加热效应电压和噪声被有效地隔离到体硅层，从而允许在器件正常工作期间进行编程。因此实现了自动修复而不中断操作的可能性。

5. 发明授权

US07226816B2 Method of forming connection and anti-fuse in layered substrate such as SOI 有权
标题翻译：在诸如SOI的层状衬底中形成连接和反熔丝的方法
公开(公告)号：US07226816B2
公开(公告)日：2007-06-05
申请号：US11055106
申请日：2005-02-11
申请人： Claude L. Bertin , Ramachandra Divakaruni , Russell J. Houghton , Jack A. Mandelman , William R. Tonti
发明人： Claude L. Bertin , Ramachandra Divakaruni , Russell J. Houghton , Jack A. Mandelman , William R. Tonti
IPC分类号： H01L21/82
CPC分类号： H01L23/5252 , H01L27/10829 , H01L27/10897 , H01L27/1203 , H01L29/66181 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An anti-fuse structure that can be programmed at low voltage and current and which potentially consumes very little chip spaces and can be formed interstitially between elements spaced by a minimum lithographic feature size is formed on a composite substrate such as a silicon-on-insulator wafer by etching a contact through an insulator to a support semiconductor layer, preferably in combination with formation of a capacitor-like structure reaching to or into the support layer. The anti-fuse may be programmed either by the selected location of conductor formation and/or damaging a dielectric of the capacitor-like structure. An insulating collar is used to surround a portion of either the conductor or the capacitor-like structure to confine damage to the desired location. Heating effects voltage and noise due to programming currents are effectively isolated to the bulk silicon layer, permitting programming during normal operation of the device. Thus the potential for self-repair without interruption of operation is realized.
摘要翻译：可以在低电压和电流下被编程并且潜在地消耗很少的芯片空间并且可以间隙地在间隔最小光刻特征尺寸的元件之间形成的抗熔丝结构形成在复合衬底上，例如绝缘体上硅通过蚀刻通过绝缘体的接触到支撑半导体层，优选结合形成到达或支撑层的电容器状结构。反熔丝可以由导体形成的选定位置和/或损坏电容器状结构的电介质来编程。绝缘环用于围绕导体或电容器状结构的一部分，以将损伤限制在所需位置。由于编程电流导致的加热效应电压和噪声被有效地隔离到体硅层，从而允许在器件正常工作期间进行编程。因此实现了自动修复而不中断操作的可能性。

6. 发明授权

US06492211B1 Method for novel SOI DRAM BICMOS NPN 失效
标题翻译：新型SOI DRAM BICMOS NPN的方法
公开(公告)号：US06492211B1
公开(公告)日：2002-12-10
申请号：US09656819
申请日：2000-09-07
申请人： Ramachandra Divakaruni , Russell J. Houghton , Jack A. Mandelman , W. David Pricer , William R. Tonti
发明人： Ramachandra Divakaruni , Russell J. Houghton , Jack A. Mandelman , W. David Pricer , William R. Tonti
IPC分类号： H01L2100
CPC分类号： H01L27/10894 , G11C7/065 , G11C2207/005 , G11C2207/065 , H01L21/84 , H01L27/10861 , H01L27/10897 , H01L27/1203
摘要： There is disclosed herein a unique fabrication sequence and the structure of a vertical silicon on insulator (SOI) bipolar transistor integrated into a typical DRAM trench process sequence. A DRAM array utilizing an NFET allows for an integrated bipolar NPN sequence. Similarly, a vertical bipolar PNP device is implemented by changing the array transistor to a PFET. Particularly, a BICMOS device is fabricated in SOI. The bipolar emitter contacts and CMOS diffusion contacts are formed simultaneously of polysilicon plugs. The CMOS diffusion contact is the plug contact from bitline to storage node of a memory cell.
摘要翻译：在此公开了独特的制造顺序和集成到典型的DRAM沟槽工艺序列中的垂直绝缘体上硅（SOI）双极晶体管的结构。使用NFET的DRAM阵列允许集成双极NPN序列。类似地，通过将阵列晶体管改变为PFET来实现垂直双极PNP器件。特别地，在SOI中制造BICMOS器件。双极发射极触点和CMOS扩散触点同时形成多晶硅插头。 CMOS扩散触点是从存储单元的位线到存储节点的插头触点。

7. 发明授权

US06396121B1 Structures and methods of anti-fuse formation in SOI 失效
公开(公告)号：US06396121B1
公开(公告)日：2002-05-28
申请号：US09583468
申请日：2000-05-31
申请人： Claude L. Bertin , Ramachandra Divakaruni , Russell J. Houghton , Jack A. Mandelman , William R. Tonti
发明人： Claude L. Bertin , Ramachandra Divakaruni , Russell J. Houghton , Jack A. Mandelman , William R. Tonti
IPC分类号： H01L2900
CPC分类号： H01L23/5252 , H01L27/10829 , H01L27/10897 , H01L27/1203 , H01L29/66181 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An anti-fuse structure that can be programmed at low voltage and current and which potentially consumes very little chip spaces and can be formed interstitially between elements spaced by a minimum lithographic feature size is formed on a composite substrate such as a silicon-on-insulator wafer by etching a contact through an insulator to a support semiconductor layer, preferably in combination with formation of a capacitor-like structure reaching to or into the support layer. The anti-fuse may be programmed either by the selected location of conductor formation and/or damaging a dielectric of the capacitor-like structure. An insulating collar is used to surround a portion of either the conductor or the capacitor-like structure to confine damage to the desired location. Heating effects voltage and noise due to programming currents are effectively isolated to the bulk silicon layer, permitting programming during normal operation of the device. Thus the potential for self-repair without interruption of operation is realized.

8. 发明授权

US06596592B2 Structures and methods of anti-fuse formation in SOI 失效
公开(公告)号：US06596592B2
公开(公告)日：2003-07-22
申请号：US10066759
申请日：2002-02-06
申请人： Claude L. Bertin , Ramachandra Divakaruni , Russell J. Houghton , Jack A. Mandelman , William R. Tonti
发明人： Claude L. Bertin , Ramachandra Divakaruni , Russell J. Houghton , Jack A. Mandelman , William R. Tonti
IPC分类号： H01L21336
CPC分类号： H01L23/5252 , H01L27/10829 , H01L27/10897 , H01L27/1203 , H01L29/66181 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An anti-fuse structure that can be programmed at low voltage and current and which potentially consumes very little chip spaces and can be formed interstitially between elements spaced by a minimum lithographic feature size is formed on a composite substrate such as a silicon-on-insulator wafer by etching a contact through an insulator to a support semiconductor layer, preferably in combination with formation of a capacitor-like structure reaching to or into the support layer. The anti-fuse may be programmed either by the selected location of conductor formation and/or damaging a dielectric of the capacitor-like structure. An insulating collar is used to surround a portion of either the conductor or the capacitor-like structure to confine damage to the desired location. Heating effects voltage and noise due to programming currents are effectively isolated to the bulk silicon layer, permitting programming during normal operation of the device. Thus the potential for self-repair without interruption of operation is realized.

9. 发明申请

US20100230781A1 TRENCH ANTI-FUSE STRUCTURES FOR A PROGRAMMABLE INTEGRATED CIRCUIT 有权
标题翻译：用于可编程集成电路的抗融合结构
公开(公告)号：US20100230781A1
公开(公告)日：2010-09-16
申请号：US12537473
申请日：2009-08-07
申请人： Roger A. Booth, JR. , Kangguo Cheng , Jack A. Mandelman , William R. Tonti
发明人： Roger A. Booth, JR. , Kangguo Cheng , Jack A. Mandelman , William R. Tonti
IPC分类号： H01L23/525 , H01L21/768
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： Trench anti-fuse structures, design structures embodied in a machine readable medium for designing, manufacturing, or testing a programmable integrated circuit. The anti-fuse structure includes a trench having a plurality of sidewalls that extend into a substrate, a doped region in the semiconductor material of the substrate proximate to the sidewalls of the trench, a conductive plug in the trench, and a dielectric layer on the sidewalls of the trench. The dielectric layer is disposed between the conductive plug and the doped region. The dielectric layer is configured so that a programming voltage applied between the doped region and the conductive plug causes a breakdown of the dielectric layer within a region of the trench. The trench sidewalls are arranged with a cross-sectional geometrical shape that is independent of position between a bottom wall of the deep trench and a top surface of the substrate.
摘要翻译：沟槽反熔丝结构，设计结构体现在用于设计，制造或测试可编程集成电路的机器可读介质中。反熔丝结构包括具有延伸到衬底中的多个侧壁的沟槽，靠近沟槽侧壁的衬底的半导体材料中的掺杂区域，沟槽中的导电插塞以及沟槽中的介电层沟槽的侧壁。电介质层设置在导电插塞和掺杂区域之间。电介质层被配置为使得施加在掺杂区域和导电插塞之间的编程电压导致沟槽区域内的电介质层的击穿。沟槽侧壁布置成具有与深沟槽的底壁和基板的顶表面之间的位置无关的横截面几何形状。

10. 发明授权

US07656005B2 Electrically programmable π-shaped fuse structures and methods of fabrication thereof 失效
标题翻译：电气可编程的pi形熔丝结构及其制造方法
公开(公告)号：US07656005B2
公开(公告)日：2010-02-02
申请号：US11768254
申请日：2007-06-26
申请人： Roger A. Booth, Jr. , Kangguo Cheng , Jack A. Mandelman , William R. Tonti
发明人： Roger A. Booth, Jr. , Kangguo Cheng , Jack A. Mandelman , William R. Tonti
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Electrically programmable fuse structures for an integrated circuit and methods of fabrication thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second terminal portion reside over a first support and a second support, respectively, with the first support and the second support being spaced apart, and the fuse element bridging the distance between the first terminal portion over the first support and the second terminal portion over the second support. The fuse, first support and second support define a π-shaped structure in elevational cross-section through the fuse element. The first terminal portion, second terminal portion and fuse element are coplanar, with the fuse element residing above a void, which in one embodiment is filed by a thermally insulating dielectric material that surrounds the fuse element.
摘要翻译：提出了用于集成电路的电可编程熔丝结构及其制造方法，其中电可编程熔丝具有由熔丝元件互连的第一端子部分和第二端子部分。第一端子部分和第二端子部分分别驻留在第一支撑件和第二支撑件上，第一支撑件和第二支撑件间隔开，并且熔丝元件将第一端子部分之间的距离跨越第一支撑件和在第二支撑件上方的第二端子部分。保险丝，第一支撑件和第二支撑件通过保险丝元件在垂直截面中限定了一个pi形结构。第一端子部分，第二端子部分和熔丝元件是共面的，其中熔丝元件位于空隙上方，在一个实施例中，熔断元件由围绕熔丝元件的绝热介电材料覆盖。

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