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1. 发明申请

US20140070285A1 METHODS OF FORMING SEMICONDUCTOR DEVICES WITH SELF-ALIGNED CONTACTS AND THE RESULTING DEVICES 有权
标题翻译：用自对准接触形成半导体器件的方法和结果器件
公开(公告)号：US20140070285A1
公开(公告)日：2014-03-13
申请号：US13611652
申请日：2012-09-12
申请人： Ruilong Xie , Ponoth Shom , Xiuyu Cai , Balasubramanian Pranatharthiharan , Robert J. Miller
发明人： Ruilong Xie , Ponoth Shom , Xiuyu Cai , Balasubramanian Pranatharthiharan , Robert J. Miller
IPC分类号： H01L21/28 , H01L29/78
CPC分类号： H01L29/66545 , H01L21/76897 , H01L21/823431 , H01L21/823437 , H01L21/823468 , H01L29/6653 , H01L29/66553 , H01L29/66628 , H01L29/66636
摘要： One method includes forming a sacrificial gate structure above a substrate, forming a first sidewall spacer adjacent a sacrificial gate electrode, removing a portion of the first sidewall spacer to expose a portion of the sidewalls of the sacrificial gate electrode, and forming a liner layer on the exposed sidewalls of the sacrificial gate electrode and above a residual portion of the first sidewall spacer. The method further includes forming a first layer of insulating material above the liner layer, forming a second sidewall spacer above the first layer of insulating material and adjacent the liner layer, performing an etching process to remove the second sidewall spacer and sacrificial gate cap layer to expose an upper surface of the sacrificial gate electrode, removing the sacrificial gate electrode to define a gate cavity at least partially defined laterally by the liner layer, and forming a replacement gate structure in the cavity.
摘要翻译：一种方法包括在衬底上形成牺牲栅极结构，形成邻近牺牲栅电极的第一侧壁间隔物，去除第一侧壁间隔物的一部分以暴露牺牲栅电极的侧壁的一部分，以及在衬底上形成衬层牺牲栅电极的暴露的侧壁和第一侧壁间隔物的残留部分之上。该方法还包括在衬垫层之上形成绝缘材料的第一层，在第一绝缘材料层之上形成第二侧壁隔离层并与衬里层相邻，执行蚀刻工艺以除去第二侧壁间隔物和牺牲栅极盖层，暴露牺牲栅电极的上表面，去除牺牲栅电极以限定通过衬层至少部分地限定的侧壁的栅极腔，以及在空腔中形成替换栅极结构。

2. 发明授权

US08753970B2 Methods of forming semiconductor devices with self-aligned contacts and the resulting devices 有权
标题翻译：形成具有自对准触头的半导体器件的方法以及所产生的器件
公开(公告)号：US08753970B2
公开(公告)日：2014-06-17
申请号：US13611652
申请日：2012-09-12
申请人： Ruilong Xie , Ponoth Shom , Xiuyu Cai , Balasubramanian Pranatharthiharan , Robert J. Miller
发明人： Ruilong Xie , Ponoth Shom , Xiuyu Cai , Balasubramanian Pranatharthiharan , Robert J. Miller
IPC分类号： H01L21/3205 , H01L21/4763 , H01L21/28
CPC分类号： H01L29/66545 , H01L21/76897 , H01L21/823431 , H01L21/823437 , H01L21/823468 , H01L29/6653 , H01L29/66553 , H01L29/66628 , H01L29/66636
摘要： One method includes forming a sacrificial gate structure above a substrate, forming a first sidewall spacer adjacent a sacrificial gate electrode, removing a portion of the first sidewall spacer to expose a portion of the sidewalls of the sacrificial gate electrode, and forming a liner layer on the exposed sidewalls of the sacrificial gate electrode and above a residual portion of the first sidewall spacer. The method further includes forming a first layer of insulating material above the liner layer, forming a second sidewall spacer above the first layer of insulating material and adjacent the liner layer, performing an etching process to remove the second sidewall spacer and sacrificial gate cap layer to expose an upper surface of the sacrificial gate electrode, removing the sacrificial gate electrode to define a gate cavity at least partially defined laterally by the liner layer, and forming a replacement gate structure in the cavity.
摘要翻译：一种方法包括在衬底上形成牺牲栅极结构，形成邻近牺牲栅电极的第一侧壁间隔物，去除第一侧壁间隔物的一部分以暴露牺牲栅电极的侧壁的一部分，以及在衬底上形成衬层牺牲栅电极的暴露的侧壁和第一侧壁间隔物的残留部分之上。该方法还包括在衬垫层之上形成绝缘材料的第一层，在第一绝缘材料层之上形成第二侧壁隔离层并与衬里层相邻，执行蚀刻工艺以除去第二侧壁间隔物和牺牲栅极盖层，暴露牺牲栅电极的上表面，去除牺牲栅电极以限定通过衬层至少部分地限定的侧壁的栅极腔，以及在空腔中形成替换栅极结构。

3. 发明授权

US08691696B2 Methods for forming an integrated circuit with straightened recess profile 有权
标题翻译：用于形成具有拉直凹槽轮廓的集成电路的方法
公开(公告)号：US08691696B2
公开(公告)日：2014-04-08
申请号：US13476860
申请日：2012-05-21
申请人： Xiuyu Cai , Xunyuan Zhang , Ruilong Xie , Errol T. Ryan , John Iacoponi
发明人： Xiuyu Cai , Xunyuan Zhang , Ruilong Xie , Errol T. Ryan , John Iacoponi
IPC分类号： H01L21/311
CPC分类号： H01L21/311 , H01L21/3105 , H01L21/31116 , H01L21/76801 , H01L21/76816 , H01L21/76828 , H01L21/76831 , H01L29/66545
摘要： Methods are provided for forming an integrated circuit. In an embodiment, the method includes forming a sacrificial mandrel overlying a base substrate. Sidewall spacers are formed adjacent sidewalls of the sacrificial mandrel. The sidewall spacers have a lower portion that is proximal to the base substrate, and the lower portion has a substantially perpendicular outer surface relative to the base substrate. The sidewall spacers also have an upper portion that is spaced from the base substrate. The upper portion has a sloped outer surface. A first dielectric layer is formed overlying the base substrate and is conformal to at least a portion of the upper portion of the sidewall spacers. The upper portion of the sidewall spacers is removed after forming the first dielectric layer to form a recess having a re-entrant profile in the first dielectric layer. The re-entrant profile of the recess is straightened.
摘要翻译：为形成集成电路提供了方法。在一个实施例中，该方法包括形成覆盖在基底衬底上的牺牲心轴。侧壁间隔件形成在牺牲心轴的相邻侧壁处。侧壁间隔件具有靠近基底基底的下部，并且下部具有相对于基底的基本垂直的外表面。侧壁间隔物还具有与基底基板间隔开的上部。上部具有倾斜的外表面。第一电介质层形成在基底衬底上，并且与侧壁间隔物的上部的至少一部分共形。在形成第一介电层之后去除侧壁间隔物的上部，以在第一介电层中形成具有凹入轮廓的凹部。凹槽的重新设计简洁直观。

4. 发明授权

US09117877B2 Methods of forming a dielectric cap layer on a metal gate structure 有权
标题翻译：在金属栅极结构上形成电介质盖层的方法
公开(公告)号：US09117877B2
公开(公告)日：2015-08-25
申请号：US13350908
申请日：2012-01-16
申请人： Xiuyu Cai , Ruilong Xie , Jin Cho , John Iacoponi
发明人： Xiuyu Cai , Ruilong Xie , Jin Cho , John Iacoponi
IPC分类号： H01L21/311 , H01L21/762 , H01L29/78 , H01L29/66
CPC分类号： H01L29/785 , H01L21/76232 , H01L29/0649 , H01L29/0653 , H01L29/66795
摘要： Disclosed herein are various methods of forming isolation structures on FinFETs and other semiconductor devices, and the resulting devices that have such isolation structures. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate, wherein the trenches define a fin for a FinFET device, forming a layer of insulating material in the trenches, wherein the layer of insulating material covers a lower portion of the fin but not an upper portion of the fin, forming a protective material on the upper portion of the fin, and performing a heating process in an oxidizing ambient to form a thermal oxide region on the covered lower portion of the fin.
摘要翻译：本文公开了在FinFET和其它半导体器件上形成隔离结构的各种方法，以及具有这种隔离结构的所得器件。在一个示例中，该方法包括在半导体衬底中形成多个间隔开的沟槽，其中沟槽限定用于FinFET器件的鳍片，在沟槽中形成绝缘材料层，其中绝缘材料层覆盖下部翅片的一部分而不是翅片的上部，在翅片的上部形成保护材料，并且在氧化环境中进行加热处理，以在翅片的被覆盖的下部形成热氧化物区域。

5. 发明申请

US20140035010A1 INTEGRATED CIRCUIT HAVING A REPLACEMENT GATE STRUCTURE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：具有替代盖结构的集成电路及其制造方法
公开(公告)号：US20140035010A1
公开(公告)日：2014-02-06
申请号：US13562659
申请日：2012-07-31
申请人： Xiuyu Cai , Ruilong Xie , Kangguo Cheng , Ali Khakifirooz
发明人： Xiuyu Cai , Ruilong Xie , Kangguo Cheng , Ali Khakifirooz
IPC分类号： H01L29/772 , H01L21/283
CPC分类号： H01L21/76834 , H01L21/28518 , H01L21/76897 , H01L29/165 , H01L29/6653 , H01L29/66545 , H01L29/66628 , H01L29/7834
摘要： A method for fabricating an integrated circuit includes forming a temporary gate structure on a semiconductor substrate. The temporary gate structure includes a temporary gate material disposed between two spacer structures. The method further includes forming a first directional silicon nitride liner overlying the temporary gate structure and the semiconductor substrate, etching the first directional silicon nitride liner overlying the temporary gate structure and the temporary gate material to form a trench between the spacer structures, while leaving the directional silicon nitride liner overlying the semiconductor substrate in place, and forming a replacement metal gate structure in the trench. An integrated circuit includes a replacement metal gate structure overlying a semiconductor substrate, a silicide region overlying the semiconductor substrate and positioned adjacent the replacement gate structure; a directional silicon nitride liner overlying a portion of the replacement gate structure; and a contact plug in electrical communication with the silicide region.
摘要翻译：一种用于制造集成电路的方法包括在半导体衬底上形成临时栅极结构。临时栅极结构包括设置在两个间隔结构之间的临时栅极材料。该方法还包括形成覆盖临时栅极结构和半导体衬底的第一定向硅氮化物衬垫，蚀刻覆盖临时栅极结构的第一定向氮化硅衬底和临时栅极材料，以在间隔物结构之间形成沟槽，同时留下定向氮化硅衬垫覆盖半导体衬底就位，并在沟槽中形成置换金属栅极结构。集成电路包括覆盖半导体衬底的替代金属栅极结构，覆盖半导体衬底并邻近置换栅结构定位的硅化物区; 覆盖所述替代栅极结构的一部分的定向氮化硅衬垫; 以及与硅化物区域电连通的接触插塞。

6. 发明授权

US08551843B1 Methods of forming CMOS semiconductor devices 有权
标题翻译：形成CMOS半导体器件的方法
公开(公告)号：US08551843B1
公开(公告)日：2013-10-08
申请号：US13465486
申请日：2012-05-07
申请人： Xiuyu Cai , Ruilong Xie
发明人： Xiuyu Cai , Ruilong Xie
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L21/28123 , H01L21/823814 , H01L21/823864 , H01L21/823878 , H01L29/66545 , H01L29/66636 , H01L29/78
摘要： One method disclosed herein includes forming first, second and third gate stacks, wherein one of the gate stacks is an isolation stack positioned above an isolation structure and each of the gate stacks is comprised of three layers of hard mask material positioned above a layer of gate electrode material. The method also involves forming sidewall spacers proximate the second gate stack while the first and isolation gate stacks are masked, forming sidewall spacers proximate the first gate stack while the second and isolation gate stacks are masked, forming a polish stop layer between the plurality of gate stacks, performing another etching process on an etch stop layer, a layer of spacer material, and the second layer of hard mask material positioned above or proximate the isolation gate stack and performing a chemical mechanical polishing process to remove material positioned above an upper surface of the polish stop layer.
摘要翻译：本文公开的一种方法包括形成第一，第二和第三栅极堆叠，其中栅极堆叠中的一个是位于隔离结构上方的隔离堆叠，并且每个栅极堆叠由位于栅极层上方的三层硬掩模材料构成电极材料。该方法还涉及在第一和隔离栅极堆叠被掩蔽的同时形成靠近第二栅极堆叠的侧壁间隔物，在第二和隔离栅极叠层被掩蔽的同时形成靠近第一栅极堆叠的侧壁间隔，在多个栅极之间形成抛光停止层堆叠，在蚀刻停止层上执行另一蚀刻工艺，间隔物材料层，以及位于隔离栅极堆叠上方或附近的第二层硬掩模材料，并执行化学机械抛光工艺，以去除位于抛光止蚀层。

7. 发明授权

US08900941B2 Methods of forming spacers on FinFETs and other semiconductor devices 有权
标题翻译：在FinFET和其他半导体器件上形成间隔物的方法
公开(公告)号：US08900941B2
公开(公告)日：2014-12-02
申请号：US13462185
申请日：2012-05-02
申请人： Xiuyu Cai , Ruilong Xie , William J. Taylor, Jr.
发明人： Xiuyu Cai , Ruilong Xie , William J. Taylor, Jr.
IPC分类号： H01L21/336
CPC分类号： H01L29/0649 , H01L21/02263 , H01L21/76224 , H01L21/823431 , H01L21/823481 , H01L27/0886 , H01L29/66795 , H01L29/7851
摘要： Disclosed herein are various methods of forming spacers on FinFETs and other semiconductor devices. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate that defines a fin, forming a first layer of insulating material in the trenches that covers a lower portion of the fin but exposes an upper portion of the fin, and forming a second layer of insulating material on the exposed upper portion of the fin. The method further comprises selectively forming a dielectric material above an upper surface of the fin and in a bottom of the trench, depositing a layer of spacer material above a gate structure of the device and above the dielectric material above the fin and in the trench, and performing an etching process on the layer of spacer material to define sidewall spacers positioned adjacent the gate structure.
摘要翻译：这里公开了在FinFET和其它半导体器件上形成间隔物的各种方法。在一个示例中，该方法包括在半导体衬底中形成多个间隔开的沟槽，其限定鳍片，在沟槽中形成绝缘材料的第一层，所述第一绝缘材料层覆盖鳍片的下部，但暴露鳍片的上部并且在所述暴露的所述翅片的上部上形成第二绝缘材料层。所述方法还包括在所述鳍的上表面和所述沟槽的底部中选择性地形成电介质材料，在所述器件的栅极结构之上和在所述鳍上方和所述沟槽中的所述电介质材料之上沉积间隔物材料层，以及对所述隔离层材料层进行蚀刻处理以限定邻近所述栅极结构定位的侧壁间隔物。

8. 发明授权

US08580634B1 Methods of forming 3-D semiconductor devices with a nanowire gate structure wherein the nanowire gate structure is formed prior to source/drain formation 有权
标题翻译：形成具有纳米线栅极结构的三维半导体器件的方法，其中在源极/漏极形成之前形成纳米线栅极结构
公开(公告)号：US08580634B1
公开(公告)日：2013-11-12
申请号：US13609941
申请日：2012-09-11
申请人： Ruilong Xie , Xiuyu Cai , Kangguo Cheng , Ali Khakifirooz
发明人： Ruilong Xie , Xiuyu Cai , Kangguo Cheng , Ali Khakifirooz
IPC分类号： H01L21/8238
CPC分类号： H01L21/845 , H01L27/1211 , H01L29/42392
摘要： In one example, the method disclosed herein includes forming a fin comprised of a semiconducting material, wherein the fin has a first, as-formed cross-sectional configuration, forming a patterned hard mask above the fin, wherein the patterned hard mask has an opening that exposes a portion of the fin, performing a fin reflow process through the opening in the patterned hard mask on the exposed portion of the fin to define a nanowire structure having a cross-sectional configuration that is different from the first cross-sectional configuration, and forming a gate structure that extends at least partially around the nanowire structure.
摘要翻译：在一个示例中，本文公开的方法包括形成由半导体材料构成的鳍片，其中鳍片具有第一成形截面构造，在鳍片之上形成图案化的硬掩模，其中图案化的硬掩模具有开口其暴露所述翅片的一部分，通过所述翅片的暴露部分上的所述图案化硬掩模中的开口进行翅片回流处理，以限定具有不同于所述第一横截面构造的横截面构造的纳米线结构，以及形成至少部分地围绕纳米线结构延伸的栅极结构。

9. 发明申请

US20130187236A1 Methods of Forming Replacement Gate Structures for Semiconductor Devices 审中-公开
标题翻译：形成半导体器件的替代栅极结构的方法
公开(公告)号：US20130187236A1
公开(公告)日：2013-07-25
申请号：US13354844
申请日：2012-01-20
申请人： Ruilong Xie , Xiuyu Cai , Robert Miller , Andreas Knorr
发明人： Ruilong Xie , Xiuyu Cai , Robert Miller , Andreas Knorr
IPC分类号： H01L27/092 , H01L21/28
CPC分类号： H01L29/4966 , H01L21/82345 , H01L21/823456 , H01L21/823842 , H01L21/82385 , H01L29/517 , H01L29/66545 , H01L29/66553
摘要： Disclosed herein are methods of forming replacement gate structures. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, removing the sacrificial gate structure to thereby define a gate cavity, forming a layer of insulating material in the gate cavity and forming a layer of metal within the gate cavity above the layer of insulating material. The method further includes forming a sacrificial material in the gate cavity so as to cover a portion of the layer of metal and thereby define an exposed portion of the layer of metal, performing an etching process on the exposed portion of the layer of metal to thereby remove the exposed portion of the layer of metal from within the gate cavity, and, after performing the etching process, removing the sacrificial material and forming a conductive material above the remaining portion of the layer of metal.
摘要翻译：这里公开了形成替换栅极结构的方法。在一个示例中，该方法包括在半导体衬底之上形成牺牲栅极结构，去除牺牲栅极结构从而限定栅极腔，在栅极腔中形成绝缘材料层并在栅极腔内形成金属层绝缘材料层。该方法还包括在栅腔中形成牺牲材料以覆盖金属层的一部分，从而限定金属层的暴露部分，对金属层的暴露部分进行蚀刻工艺，由此从栅极腔内去除金属层的暴露部分，并且在执行蚀刻工艺之后，去除牺牲材料并在金属层的剩余部分上方形成导电材料。

10. 发明申请

US20130309868A1 METHODS FOR FORMING AN INTEGRATED CIRCUIT WITH STRAIGHTENED RECESS PROFILE 有权
标题翻译：用于形成具有连续记录轮廓的集成电路的方法
公开(公告)号：US20130309868A1
公开(公告)日：2013-11-21
申请号：US13476860
申请日：2012-05-21
申请人： Xiuyu Cai , Xunyuan Zhang , Ruilong Xie , Errol T. Ryan , John A. Iacoponi
发明人： Xiuyu Cai , Xunyuan Zhang , Ruilong Xie , Errol T. Ryan , John A. Iacoponi
IPC分类号： H01L21/311
CPC分类号： H01L21/311 , H01L21/3105 , H01L21/31116 , H01L21/76801 , H01L21/76816 , H01L21/76828 , H01L21/76831 , H01L29/66545
摘要： Methods are provided for forming an integrated circuit. In an embodiment, the method includes forming a sacrificial mandrel overlying a base substrate. Sidewall spacers are formed adjacent sidewalls of the sacrificial mandrel. The sidewall spacers have a lower portion that is proximal to the base substrate, and the lower portion has a substantially perpendicular outer surface relative to the base substrate. The sidewall spacers also have an upper portion that is spaced from the base substrate. The upper portion has a sloped outer surface. A first dielectric layer is formed overlying the base substrate and is conformal to at least a portion of the upper portion of the sidewall spacers. The upper portion of the sidewall spacers is removed after forming the first dielectric layer to form a recess having a re-entrant profile in the first dielectric layer. The re-entrant profile of the recess is straightened.
摘要翻译：为形成集成电路提供了方法。在一个实施例中，该方法包括形成覆盖在基底衬底上的牺牲心轴。侧壁间隔件形成在牺牲心轴的相邻侧壁处。侧壁间隔件具有靠近基底基底的下部，并且下部具有相对于基底的基本垂直的外表面。侧壁间隔物还具有与基底基板间隔开的上部。上部具有倾斜的外表面。第一电介质层形成在基底衬底上，并且与侧壁间隔物的上部的至少一部分共形。在形成第一介电层之后去除侧壁间隔物的上部，以在第一介电层中形成具有凹入轮廓的凹部。凹槽的重新设计简洁直观。

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