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1. 发明申请

US20140070285A1 METHODS OF FORMING SEMICONDUCTOR DEVICES WITH SELF-ALIGNED CONTACTS AND THE RESULTING DEVICES 有权
标题翻译：用自对准接触形成半导体器件的方法和结果器件
公开(公告)号：US20140070285A1
公开(公告)日：2014-03-13
申请号：US13611652
申请日：2012-09-12
申请人： Ruilong Xie , Ponoth Shom , Xiuyu Cai , Balasubramanian Pranatharthiharan , Robert J. Miller
发明人： Ruilong Xie , Ponoth Shom , Xiuyu Cai , Balasubramanian Pranatharthiharan , Robert J. Miller
IPC分类号： H01L21/28 , H01L29/78
CPC分类号： H01L29/66545 , H01L21/76897 , H01L21/823431 , H01L21/823437 , H01L21/823468 , H01L29/6653 , H01L29/66553 , H01L29/66628 , H01L29/66636
摘要： One method includes forming a sacrificial gate structure above a substrate, forming a first sidewall spacer adjacent a sacrificial gate electrode, removing a portion of the first sidewall spacer to expose a portion of the sidewalls of the sacrificial gate electrode, and forming a liner layer on the exposed sidewalls of the sacrificial gate electrode and above a residual portion of the first sidewall spacer. The method further includes forming a first layer of insulating material above the liner layer, forming a second sidewall spacer above the first layer of insulating material and adjacent the liner layer, performing an etching process to remove the second sidewall spacer and sacrificial gate cap layer to expose an upper surface of the sacrificial gate electrode, removing the sacrificial gate electrode to define a gate cavity at least partially defined laterally by the liner layer, and forming a replacement gate structure in the cavity.
摘要翻译：一种方法包括在衬底上形成牺牲栅极结构，形成邻近牺牲栅电极的第一侧壁间隔物，去除第一侧壁间隔物的一部分以暴露牺牲栅电极的侧壁的一部分，以及在衬底上形成衬层牺牲栅电极的暴露的侧壁和第一侧壁间隔物的残留部分之上。该方法还包括在衬垫层之上形成绝缘材料的第一层，在第一绝缘材料层之上形成第二侧壁隔离层并与衬里层相邻，执行蚀刻工艺以除去第二侧壁间隔物和牺牲栅极盖层，暴露牺牲栅电极的上表面，去除牺牲栅电极以限定通过衬层至少部分地限定的侧壁的栅极腔，以及在空腔中形成替换栅极结构。

2. 发明授权

US08753970B2 Methods of forming semiconductor devices with self-aligned contacts and the resulting devices 有权
标题翻译：形成具有自对准触头的半导体器件的方法以及所产生的器件
公开(公告)号：US08753970B2
公开(公告)日：2014-06-17
申请号：US13611652
申请日：2012-09-12
申请人： Ruilong Xie , Ponoth Shom , Xiuyu Cai , Balasubramanian Pranatharthiharan , Robert J. Miller
发明人： Ruilong Xie , Ponoth Shom , Xiuyu Cai , Balasubramanian Pranatharthiharan , Robert J. Miller
IPC分类号： H01L21/3205 , H01L21/4763 , H01L21/28
CPC分类号： H01L29/66545 , H01L21/76897 , H01L21/823431 , H01L21/823437 , H01L21/823468 , H01L29/6653 , H01L29/66553 , H01L29/66628 , H01L29/66636
摘要： One method includes forming a sacrificial gate structure above a substrate, forming a first sidewall spacer adjacent a sacrificial gate electrode, removing a portion of the first sidewall spacer to expose a portion of the sidewalls of the sacrificial gate electrode, and forming a liner layer on the exposed sidewalls of the sacrificial gate electrode and above a residual portion of the first sidewall spacer. The method further includes forming a first layer of insulating material above the liner layer, forming a second sidewall spacer above the first layer of insulating material and adjacent the liner layer, performing an etching process to remove the second sidewall spacer and sacrificial gate cap layer to expose an upper surface of the sacrificial gate electrode, removing the sacrificial gate electrode to define a gate cavity at least partially defined laterally by the liner layer, and forming a replacement gate structure in the cavity.
摘要翻译：一种方法包括在衬底上形成牺牲栅极结构，形成邻近牺牲栅电极的第一侧壁间隔物，去除第一侧壁间隔物的一部分以暴露牺牲栅电极的侧壁的一部分，以及在衬底上形成衬层牺牲栅电极的暴露的侧壁和第一侧壁间隔物的残留部分之上。该方法还包括在衬垫层之上形成绝缘材料的第一层，在第一绝缘材料层之上形成第二侧壁隔离层并与衬里层相邻，执行蚀刻工艺以除去第二侧壁间隔物和牺牲栅极盖层，暴露牺牲栅电极的上表面，去除牺牲栅电极以限定通过衬层至少部分地限定的侧壁的栅极腔，以及在空腔中形成替换栅极结构。

3. 发明授权

US08617973B2 Semiconductor device fabrication methods with enhanced control in recessing processes 有权
标题翻译：半导体器件制造方法具有增强的凹陷工艺控制
公开(公告)号：US08617973B2
公开(公告)日：2013-12-31
申请号：US13247763
申请日：2011-09-28
申请人： Ruilong Xie , Robert J. Miller
发明人： Ruilong Xie , Robert J. Miller
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/32134 , H01L21/28088 , H01L21/32135 , H01L21/823437 , H01L29/4966 , H01L29/66545 , H01L29/6656 , H01L29/7833
摘要： Semiconductor device fabrication methods having enhanced control in recessing processes are provided. In a method for fabricating a semiconductor device or plurality of them, a structure is formed. The method includes preparing a limited amount of the structure having a depth of less than ten atomic layers for removal. Further, the method includes performing a removal process to remove the limited amount of the structure. The method repeats preparation of successive limited amounts of the structure for removal, and performance of the removal process to form a recess at an upper portion of the structure.
摘要翻译：提供了具有增强的凹陷处理控制的半导体器件制造方法。在制造半导体器件或其中的多个器件的方法中，形成结构。该方法包括制备有限量的具有小于10个原子层的深度以去除的结构。此外，该方法包括执行去除处理以去除有限量的结构。该方法重复制备连续有限量的用于除去的结构，以及执行去除过程以在结构的上部形成凹部。

4. 发明申请

US20130078791A1 SEMICONDUCTOR DEVICE FABRICATION METHODS WITH ENHANCED CONTROL IN RECESSING PROCESSES 有权
标题翻译：具有增强控制功能的半导体器件制造方法
公开(公告)号：US20130078791A1
公开(公告)日：2013-03-28
申请号：US13247763
申请日：2011-09-28
申请人： Ruilong Xie , Robert J. Miller
发明人： Ruilong Xie , Robert J. Miller
IPC分类号： H01L21/28 , H01L21/302
CPC分类号： H01L21/32134 , H01L21/28088 , H01L21/32135 , H01L21/823437 , H01L29/4966 , H01L29/66545 , H01L29/6656 , H01L29/7833
摘要： Semiconductor device fabrication methods having enhanced control in recessing processes are provided. In a method for fabricating a semiconductor device or plurality of them, a structure is formed. The method includes preparing a limited amount of the structure having a depth of less than ten atomic layers for removal. Further, the method includes performing a removal process to remove the limited amount of the structure. The method repeats preparation of successive limited amounts of the structure for removal, and performance of the removal process to form a recess at an upper portion of the structure.
摘要翻译：提供了具有增强的凹陷处理控制的半导体器件制造方法。在制造半导体器件或其中的多个器件的方法中，形成结构。该方法包括制备有限量的具有小于10个原子层的深度以去除的结构。此外，该方法包括执行去除处理以去除有限量的结构。该方法重复制备连续有限量的用于除去的结构，以及执行去除过程以在结构的上部形成凹部。

5. 发明授权

US08760157B2 Multiferroic antenna/sensor 有权
标题翻译：多功能天线/传感器
公开(公告)号：US08760157B2
公开(公告)日：2014-06-24
申请号：US12561498
申请日：2009-09-17
申请人： Robert J. Miller , William P. Geren , Stephen P. Hubbell
发明人： Robert J. Miller , William P. Geren , Stephen P. Hubbell
IPC分类号： G01R33/02
CPC分类号： G01R33/18 , H01Q1/32 , H01Q1/52 , H01Q17/00
摘要： A multiferroic antenna and sensor where the sensor includes a multiferroic stack of multiple connected multiferroic layer-pairs, each multiferroic layer-pair comprising an alternating layer of a magnetostrictive material and a piezoelectric material bonded together enabling a high signal sensitivity, a magnetic field of an incident signal causing mechanical strain in the magnetostrictive material layers that strains adjacent piezoelectric material layers producing an electrical voltage in each multiferroic layer-pair proportional to the incident signal. An output of the multiferroic stack comprises the electrical voltage amplified proportional to a total number of multiple connected multiferroic layer-pairs in the multiferroic stack.
摘要翻译：一种多铁性天线和传感器，其中传感器包括多层连接的多铁层对的多层叠层，每个多层层对包括磁致伸缩材料的交替层和结合在一起的压电材料，能够实现高信号灵敏度，入射信号引起磁致伸缩材料层中的机械应变，使得相邻的压电材料层产生与入射信号成比例的每个多铁层对中的电压。多层堆叠的输出包括与多层堆叠中的多个连接的多铁层对的总数成比例放大的电压。

6. 发明申请

US20130330916A1 METHODS OF FORMING HIGH MOBILITY FIN CHANNELS ON THREE DIMENSIONAL SEMICONDUCTOR DEVICES 有权
标题翻译：在三维半导体器件上形成高移动性融合通道的方法
公开(公告)号：US20130330916A1
公开(公告)日：2013-12-12
申请号：US13493021
申请日：2012-06-11
申请人： Daniel T. Pham , Robert J. Miller , Kingsuk Maitra
发明人： Daniel T. Pham , Robert J. Miller , Kingsuk Maitra
IPC分类号： H01L21/205
CPC分类号： H01L29/1054 , H01L29/66795 , H01L29/785
摘要： Disclosed herein are various methods of forming high mobility fin channels on three dimensional semiconductor devices, such as, for example, FinFET semiconductor devices. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate, wherein the trenches define an original fin structure for the device, and wherein a portion of a mask layer is positioned above the original fin structure, forming a compressively-stressed material in the trenches and adjacent the portion of mask layer, after forming the compressively-stressed material, removing the portion of the mask layer to thereby expose an upper surface of the original fin structure, and forming a final fin structure above the exposed surface of the original fin structure.
摘要翻译：本文公开了在三维半导体器件（例如FinFET半导体器件）上形成高迁移率鳍通道的各种方法。在一个示例中，该方法包括在半导体衬底中形成多个间隔开的沟槽，其中沟槽限定用于器件的原始鳍状结构，并且其中掩模层的一部分位于原始鳍结构的上方，形成在形成压缩应力材料之后，在沟槽中并与掩模层的部分相邻的压缩应力材料，去除掩模层的部分，从而暴露原始鳍状结构的上表面，并且在裸露表面的原有翅片结构。

7. 发明授权

US08466034B2 Method of manufacturing a finned semiconductor device structure 有权
标题翻译：制造翅片半导体器件结构的方法
公开(公告)号：US08466034B2
公开(公告)日：2013-06-18
申请号：US12749220
申请日：2010-03-29
申请人： Witold Maszara , Robert J. Miller
发明人： Witold Maszara , Robert J. Miller
IPC分类号： H01L21/76
CPC分类号： H01L29/66545 , H01L29/66795
摘要： A method of manufacturing a finned semiconductor device structure is provided. The method begins by providing a substrate having bulk semiconductor material. The method continues by forming a semiconductor fin structure from the bulk semiconductor material, depositing an insulating material overlying the semiconductor fin structure such that the insulating material fills space adjacent to the semiconductor fin structure, and planarizing the deposited insulating material and the semiconductor fin structure to create a flat surface. Thereafter, a replacement gate procedure is performed to form a gate structure transversely overlying the semiconductor fin structure.
摘要翻译：提供一种制造翅片半导体器件结构的方法。该方法开始于提供具有体半导体材料的衬底。该方法继续通过从体半导体材料形成半导体鳍结构，沉积覆盖半导体鳍结构的绝缘材料，使得绝缘材料填充与半导体鳍结构相邻的空间，并将沉积的绝缘材料和半导体鳍结构平坦化为创建一个平坦的表面。此后，执行替换门程序以形成横向覆盖半导体鳍结构的栅极结构。

8. 发明授权

US08354719B2 Finned semiconductor device with oxygen diffusion barrier regions, and related fabrication methods 有权
标题翻译：具有氧扩散阻挡区域的翅片半导体器件及相关制造方法
公开(公告)号：US08354719B2
公开(公告)日：2013-01-15
申请号：US12708213
申请日：2010-02-18
申请人： Kisik Choi , Robert J. Miller
发明人： Kisik Choi , Robert J. Miller
IPC分类号： H01L27/12
CPC分类号： H01L29/66795 , H01L21/76229 , H01L29/66545 , H01L29/785
摘要： A semiconductor device and related fabrication methods are provided. One exemplary fabrication method forms a fin arrangement overlying an oxide layer, where the fin arrangement includes one or more semiconductor fin structures. The method continues by nitriding exposed portions of the oxide layer without nitriding the one or more semiconductor fin structures, resulting in nitrided portions of the oxide layer. Thereafter, a gate structure is formed transversely overlying the fin arrangement, and overlying the exposed portions of the oxide layer. The nitrided portions of the oxide layer substantially inhibit diffusion of oxygen from the oxide layer into the gate structure.
摘要翻译：提供半导体器件及相关的制造方法。一种示例性的制造方法形成覆盖氧化物层的翅片布置，其中翅片布置包括一个或多个半导体翅片结构。该方法通过氮化氧化物层的暴露部分而不渗透一个或多个半导体鳍结构，导致氧化物层的氮化部分继续。此后，栅极结构横向地形成在翅片布置上，并且覆盖在氧化物层的暴露部分上。氧化物层的氮化部分基本上抑制氧从氧化物层扩散到栅极结构中。

9. 发明申请

US20120111693A1 Method of Manufacturing a Transmission Clutch Assembly with Reduced Squawk 审中-公开
标题翻译：制造具有减少眩光的传动离合器组件的方法
公开(公告)号：US20120111693A1
公开(公告)日：2012-05-10
申请号：US13351447
申请日：2012-01-17
申请人： Jim Chern , Carl Garbacik , Robert J. Miller , Jau-Wen Tseng
发明人： Jim Chern , Carl Garbacik , Robert J. Miller , Jau-Wen Tseng
IPC分类号： F16F15/10 , B23P11/00
CPC分类号： F16D65/0006 , F16D13/683 , F16D25/0638 , F16D65/0018 , F16D65/092 , F16D65/12 , F16D2300/22 , F16F15/1336 , F16F15/1421 , Y10T29/49826
摘要： The present disclosure relates to a method of manufacturing a transmission clutch assembly configured to reduce squawk during engagement, the method including: forming a clutch component; and coupling a plurality of mass dampers to the clutch component to split a mode of vibration for the clutch component during engagement.
摘要翻译：本公开涉及一种制造传动离合器组件的方法，所述变速器离合器组件被构造成在接合期间减少冲击，所述方法包括：形成离合器部件; 以及将多个质量阻尼器联接到离合器部件，以在接合期间分离离合器部件的振动模式。

10. 发明申请

US20120031567A1 WIRELESS COMMUNICATION SYSTEM FOR A ROLL-UP DOOR 有权
标题翻译：无线通信系统
公开(公告)号：US20120031567A1
公开(公告)日：2012-02-09
申请号：US13274952
申请日：2011-10-17
申请人： William W. SHIER , Lee H. Theusch , Allan B. Czubin , Robert J. Miller
发明人： William W. SHIER , Lee H. Theusch , Allan B. Czubin , Robert J. Miller
IPC分类号： E05F15/20 , E06B9/68 , E05F15/10 , G08C19/16
CPC分类号： E06B9/68 , E05F15/668 , E05F15/70 , E05Y2400/44 , E05Y2400/512 , E05Y2400/612 , E05Y2400/66 , E05Y2600/46 , E05Y2900/00 , E05Y2900/106
摘要： A door system includes a support connected to a structure, and a door mounted on the support and movable relative to the support between an opened position and a closed position. The door includes a detection device and a remote module coupled to the detection device. The remote module includes a battery and an RF module for supporting two-way communication and sending signals indicative of the status of the detection device and the battery. The door system also includes a motor to drive the door, and a controller to control the motor. The controller includes a user interface and a memory. The door system also includes a base module coupled to the controller for receiving signals from the remote module. The received signals are indicative of the status of the detection device and the battery. The base module also sends signals related to successful transmission acknowledgements to the remote module.
摘要翻译：门系统包括连接到结构的支撑件和安装在支撑件上并可相对于支撑件在打开位置和关闭位置之间移动的门。门包括检测装置和耦合到检测装置的远程模块。远程模块包括电池和用于支持双向通信并发送指示检测装置和电池的状态的信号的RF模块。门系统还包括驱动门的马达和控制器来控制马达。控制器包括用户界面和存储器。门系统还包括耦合到控制器的基本模块，用于从远程模块接收信号。所接收的信号表示检测装置和电池的状态。基本模块还向远程模块发送与成功发送确认有关的信号。

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