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1. 发明申请

US20130309868A1 METHODS FOR FORMING AN INTEGRATED CIRCUIT WITH STRAIGHTENED RECESS PROFILE 有权
标题翻译：用于形成具有连续记录轮廓的集成电路的方法
公开(公告)号：US20130309868A1
公开(公告)日：2013-11-21
申请号：US13476860
申请日：2012-05-21
申请人： Xiuyu Cai , Xunyuan Zhang , Ruilong Xie , Errol T. Ryan , John A. Iacoponi
发明人： Xiuyu Cai , Xunyuan Zhang , Ruilong Xie , Errol T. Ryan , John A. Iacoponi
IPC分类号： H01L21/311
CPC分类号： H01L21/311 , H01L21/3105 , H01L21/31116 , H01L21/76801 , H01L21/76816 , H01L21/76828 , H01L21/76831 , H01L29/66545
摘要： Methods are provided for forming an integrated circuit. In an embodiment, the method includes forming a sacrificial mandrel overlying a base substrate. Sidewall spacers are formed adjacent sidewalls of the sacrificial mandrel. The sidewall spacers have a lower portion that is proximal to the base substrate, and the lower portion has a substantially perpendicular outer surface relative to the base substrate. The sidewall spacers also have an upper portion that is spaced from the base substrate. The upper portion has a sloped outer surface. A first dielectric layer is formed overlying the base substrate and is conformal to at least a portion of the upper portion of the sidewall spacers. The upper portion of the sidewall spacers is removed after forming the first dielectric layer to form a recess having a re-entrant profile in the first dielectric layer. The re-entrant profile of the recess is straightened.
摘要翻译：为形成集成电路提供了方法。在一个实施例中，该方法包括形成覆盖在基底衬底上的牺牲心轴。侧壁间隔件形成在牺牲心轴的相邻侧壁处。侧壁间隔件具有靠近基底基底的下部，并且下部具有相对于基底的基本垂直的外表面。侧壁间隔物还具有与基底基板间隔开的上部。上部具有倾斜的外表面。第一电介质层形成在基底衬底上，并且与侧壁间隔物的上部的至少一部分共形。在形成第一介电层之后去除侧壁间隔物的上部，以在第一介电层中形成具有凹入轮廓的凹部。凹槽的重新设计简洁直观。

2. 发明授权

US08691696B2 Methods for forming an integrated circuit with straightened recess profile 有权
标题翻译：用于形成具有拉直凹槽轮廓的集成电路的方法
公开(公告)号：US08691696B2
公开(公告)日：2014-04-08
申请号：US13476860
申请日：2012-05-21
申请人： Xiuyu Cai , Xunyuan Zhang , Ruilong Xie , Errol T. Ryan , John Iacoponi
发明人： Xiuyu Cai , Xunyuan Zhang , Ruilong Xie , Errol T. Ryan , John Iacoponi
IPC分类号： H01L21/311
CPC分类号： H01L21/311 , H01L21/3105 , H01L21/31116 , H01L21/76801 , H01L21/76816 , H01L21/76828 , H01L21/76831 , H01L29/66545
摘要： Methods are provided for forming an integrated circuit. In an embodiment, the method includes forming a sacrificial mandrel overlying a base substrate. Sidewall spacers are formed adjacent sidewalls of the sacrificial mandrel. The sidewall spacers have a lower portion that is proximal to the base substrate, and the lower portion has a substantially perpendicular outer surface relative to the base substrate. The sidewall spacers also have an upper portion that is spaced from the base substrate. The upper portion has a sloped outer surface. A first dielectric layer is formed overlying the base substrate and is conformal to at least a portion of the upper portion of the sidewall spacers. The upper portion of the sidewall spacers is removed after forming the first dielectric layer to form a recess having a re-entrant profile in the first dielectric layer. The re-entrant profile of the recess is straightened.
摘要翻译：为形成集成电路提供了方法。在一个实施例中，该方法包括形成覆盖在基底衬底上的牺牲心轴。侧壁间隔件形成在牺牲心轴的相邻侧壁处。侧壁间隔件具有靠近基底基底的下部，并且下部具有相对于基底的基本垂直的外表面。侧壁间隔物还具有与基底基板间隔开的上部。上部具有倾斜的外表面。第一电介质层形成在基底衬底上，并且与侧壁间隔物的上部的至少一部分共形。在形成第一介电层之后去除侧壁间隔物的上部，以在第一介电层中形成具有凹入轮廓的凹部。凹槽的重新设计简洁直观。

3. 发明授权

US08431482B1 Integrated circuits and methods for processing integrated circuits with embedded features 有权
标题翻译：用于处理具有嵌入式功能的集成电路的集成电路和方法
公开(公告)号：US08431482B1
公开(公告)日：2013-04-30
申请号：US13362981
申请日：2012-01-31
申请人： Errol T. Ryan , Xunyuan Zhang
发明人： Errol T. Ryan , Xunyuan Zhang
IPC分类号： H01L21/4763
CPC分类号： H01L23/535 , H01L21/76832 , H01L21/76834 , H01L21/76883 , H01L21/76886 , H01L2924/0002 , H01L2924/00
摘要： Integrated circuits, a process for recessing an embedded copper feature within a substrate, and a process for recessing an embedded copper interconnect within an interlayer dielectric substrate of an integrated circuit are provided. In an embodiment, a process for recessing an embedded copper feature, such as an embedded copper interconnect, within a substrate, such as an interlayer dielectric substrate, includes providing a substrate having an embedded copper feature disposed therein. The embedded copper feature has an exposed surface and the substrate has a substrate surface adjacent to the exposed surface of the embedded copper feature. The exposed surface of the embedded copper feature is nitrided to form a layer of copper nitride in the embedded copper feature. Copper nitride is selectively etched from the embedded copper feature to recess the embedded copper feature within the substrate.
摘要翻译：提供集成电路，用于凹入衬底内的嵌入式铜特征的工艺，以及用于使集成电路的层间电介质衬底内的嵌入式铜互连凹陷的工艺。在一个实施例中，在诸如层间电介质基板的衬底内嵌入诸如嵌入式铜互连的嵌入式铜特征的方法包括提供其中布置有嵌入式铜特征的衬底。嵌入的铜特征具有暴露的表面，并且衬底具有与嵌入的铜特征的暴露表面相邻的衬底表面。嵌入的铜特征的暴露表面被氮化以在嵌入的铜特征中形成一层氮化铜。从嵌入的铜特征中选择性地蚀刻氮化铜以将嵌入的铜特征凹入到衬底内。

4. 发明授权

US08357609B2 Dual damascene-like subtractive metal etch scheme 有权
标题翻译：双镶嵌式减法金属蚀刻方案
公开(公告)号：US08357609B2
公开(公告)日：2013-01-22
申请号：US12773219
申请日：2010-05-04
申请人： Errol T. Ryan
发明人： Errol T. Ryan
IPC分类号： H01L21/4763
CPC分类号： H01L21/76885 , H01L21/32139 , H01L21/76852 , H01L21/76897
摘要： Metal interconnects are formed with larger grain size and improved uniformity. Embodiments include patterning metal layers into metal interconnects and vias prior to depositing a dielectric layer. An embodiment includes forming metal layers on a substrate, patterning the metal layers to form metal interconnect lines and vias, and forming a dielectric layer on the substrate, metal interconnect lines, and vias, thereby filling gaps between the metal interconnect lines and between the vias. The metal layers may be annealed prior to patterning. A liner may be formed on the sidewalls of the metal interconnect lines and vias prior to forming the dielectric layer. The dielectric layer may be formed of a porous material with a dielectric constant less than 2.4.
摘要翻译：金属互连形成为具有更大的晶粒尺寸和改进的均匀性。实施例包括在沉积介电层之前将金属层图案化成金属互连和通孔。一个实施例包括在衬底上形成金属层，图案化金属层以形成金属互连线和通孔，以及在衬底，金属互连线和通孔上形成电介质层，由此填充金属互连线之间和通孔之间的间隙。金属层可以在图案化之前退火。在形成介电层之前，可以在金属互连线和通孔的侧壁上形成衬垫。电介质层可以由介电常数小于2.4的多孔材料形成。

5. 发明申请

US20130072019A1 METHODS FOR FORMING SEMICONDUCTOR DEVICES 有权
标题翻译：形成半导体器件的方法
公开(公告)号：US20130072019A1
公开(公告)日：2013-03-21
申请号：US13235194
申请日：2011-09-16
申请人： Errol T. Ryan
发明人： Errol T. Ryan
IPC分类号： H01L21/768 , H01L21/28
CPC分类号： H01L21/76843 , H01L21/76856 , H01L21/76865
摘要： Embodiments of methods for forming a semiconductor device are provided. The method includes forming a metal layer overlying a dielectric material. A thickness of the metal layer is reduced including oxidizing an exposed outer portion of the metal layer to form a metal oxide portion overlying a remaining portion of the metal layer and removing the metal oxide portion.
摘要翻译：提供了形成半导体器件的方法的实施例。该方法包括形成覆盖电介质材料的金属层。减少金属层的厚度，包括氧化金属层的暴露的外部部分，以形成覆盖金属层的剩余部分并去除金属氧化物部分的金属氧化物部分。

6. 发明申请

US20110275214A1 DUAL DAMASCENE-LIKE SUBTRACTIVE METAL ETCH SCHEME 有权
标题翻译：双重类似相似金属蚀刻方案
公开(公告)号：US20110275214A1
公开(公告)日：2011-11-10
申请号：US12773219
申请日：2010-05-04
申请人： Errol T. Ryan
发明人： Errol T. Ryan
IPC分类号： H01L21/768
CPC分类号： H01L21/76885 , H01L21/32139 , H01L21/76852 , H01L21/76897
摘要： Metal interconnects are formed with larger grain size and improved uniformity. Embodiments include patterning metal layers into metal interconnects and vias prior to depositing a dielectric layer. An embodiment includes forming metal layers on a substrate, patterning the metal layers to form metal interconnect lines and vias, and forming a dielectric layer on the substrate, metal interconnect lines, and vias, thereby filling gaps between the metal interconnect lines and between the vias. The metal layers may be annealed prior to patterning. A liner may be formed on the sidewalls of the metal interconnect lines and vias prior to forming the dielectric layer. The dielectric layer may be formed of a porous material with a dielectric constant less than 2.4.
摘要翻译：金属互连形成为具有更大的晶粒尺寸和改进的均匀性。实施例包括在沉积介电层之前将金属层图案化成金属互连和通孔。一个实施例包括在衬底上形成金属层，图案化金属层以形成金属互连线和通孔，以及在衬底，金属互连线和通孔上形成电介质层，由此填充金属互连线之间和通孔之间的间隙。金属层可以在图案化之前退火。在形成介电层之前，可以在金属互连线和通孔的侧壁上形成衬垫。电介质层可以由介电常数小于2.4的多孔材料形成。

7. 发明申请

US20130221524A1 INTEGRATED CIRCUITS WITH IMPROVED INTERCONNECT RELIABILITY USING AN INSULATING MONOLAYER AND METHODS FOR FABRICATING SAME 审中-公开
标题翻译：具有改进的使用绝缘单层的互连可靠性的集成电路及其制造方法
公开(公告)号：US20130221524A1
公开(公告)日：2013-08-29
申请号：US13407815
申请日：2012-02-29
申请人： Roderick A. Augur , Errol T. Ryan
发明人： Roderick A. Augur , Errol T. Ryan
IPC分类号： H01L23/48 , H01L21/56
CPC分类号： H01L21/76832 , H01L21/76834 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00012 , H01L2924/00
摘要： Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, an integrated circuit includes an interlayer dielectric material having a top surface and overlying semiconductor devices formed on a semiconductor substrate. The integrated circuit includes a metal interconnect formed in the interlayer dielectric material. The metal interconnect includes an upper surface to which an insulating monolayer is bonded. The integrated circuit further includes a dielectric cap that overlies the top surface of the interlayer dielectric material and encapsulates the insulating monolayer.
摘要翻译：提供了用于制造集成电路的集成电路和方法。在一个实施例中，集成电路包括具有顶表面的层间电介质材料和形成在半导体衬底上的上覆半导体器件。集成电路包括形成在层间电介质材料中的金属互连。金属互连件包括粘合绝缘单层的上表面。集成电路还包括覆盖层间电介质材料的顶表面并封装绝缘单层的电介质盖。

8. 发明申请

US20100233879A1 METHOD FOR UNIFORM NANOSCALE FILM DEPOSITION 有权
标题翻译：用于均匀纳米膜沉积的方法
公开(公告)号：US20100233879A1
公开(公告)日：2010-09-16
申请号：US12404890
申请日：2009-03-16
申请人： Errol T. Ryan
发明人： Errol T. Ryan
IPC分类号： H01L21/285 , C23C16/54
CPC分类号： H01L21/76834 , C23C16/345 , C23C16/45565 , C23C16/45587 , C23C16/4583 , C23C16/505 , H01L21/0217 , H01L21/02271 , H01L21/3185
摘要： Ultrathin layers are deposited by chemical vapor deposition (CVD) with reduced discontinuities, such as pinholes. Embodiments include depositing a material on a wafer by CVD while rotating the CVD showerhead and/or the wafer mounting surface, e.g., at least 45°. Embodiments include rotating the showerhead and/or mounting surface continuously through the deposition of the material. Embodiments also include forming subfilms of the material and rotating the showerhead and/or mounting surface after the deposition of each subfilm. The rotation of the showerhead and/or mounting surface averages out the non-uniformities introduced by the CVD showerhead, thereby eliminating discontinuities and improving within wafer and wafer-to-wafer uniformity.
摘要翻译：通过具有减小的不连续性（例如针孔）的化学气相沉积（CVD）沉积超薄层。实施例包括在旋转CVD喷头和/或晶片安装表面的情况下通过CVD在晶片上沉积材料，例如至少45°。实施例包括通过材料的沉积来连续旋转喷头和/或安装表面。实施例还包括在沉积每个子膜之后形成材料的子膜并旋转喷头和/或安装表面。喷头和/或安装面的旋转平均化了由CVD喷头引入的不均匀性，从而消除了晶片间的不连续性和提高晶片与晶片的均匀性。

9. 发明授权

US08871635B2 Integrated circuits and processes for forming integrated circuits having an embedded electrical interconnect within a substrate 有权
标题翻译：用于形成在衬底内具有嵌入式电互连的集成电路的集成电路和工艺
公开(公告)号：US08871635B2
公开(公告)日：2014-10-28
申请号：US13466895
申请日：2012-05-08
申请人： Chanro Park , Errol T. Ryan
发明人： Chanro Park , Errol T. Ryan
IPC分类号： H01L21/4763
CPC分类号： H01L21/76883 , H01L21/76832 , H01L21/76834
摘要： Integrated circuits and processes for forming integrated circuits are provided. An exemplary process for forming an integrated circuit includes providing a substrate including an oxide layer and a protecting layer disposed over the oxide layer. A recess is etched through the protecting layer and at least partially into the oxide layer. A barrier material is deposited in the recess to form a barrier layer over the oxide layer and protecting layer in the recess. Electrically-conductive material is deposited over the barrier layer in the recess to form the embedded electrical interconnect. The embedded electrical interconnect and barrier layer are recessed to an interconnect recess depth and a barrier recess depth, respectively, within the substrate. At least a portion of the protecting layer remains over the oxide layer after recessing the barrier layer and is removed after recessing the barrier layer.
摘要翻译：提供了用于形成集成电路的集成电路和工艺。用于形成集成电路的示例性方法包括提供包括氧化物层和设置在氧化物层上的保护层的衬底。通过保护层蚀刻凹陷，并且至少部分地蚀刻到氧化物层中。阻挡材料沉积在凹部中以在氧化物层和凹部中的保护层之上形成阻挡层。导电材料沉积在凹槽中的势垒层上以形成嵌入的电互连。嵌入的电互连和阻挡层分别凹陷到衬底内的互连凹槽深度和阻挡凹槽深度。在使阻挡层凹陷之后，保护层的至少一部分保留在氧化物层上方，并且在凹陷阻挡层之后被去除。

10. 发明申请

US20130175680A1 DIELECTRIC MATERIAL WITH HIGH MECHANICAL STRENGTH 审中-公开
标题翻译：具有高机械强度的电介质材料
公开(公告)号：US20130175680A1
公开(公告)日：2013-07-11
申请号：US13347687
申请日：2012-01-10
申请人： Stephen M. Gates , Alfred Grill , Errol T. Ryan
发明人： Stephen M. Gates , Alfred Grill , Errol T. Ryan
IPC分类号： H01L23/532 , C07F7/18 , H01L21/314
CPC分类号： H01L23/5329 , H01L21/02126 , H01L21/02203 , H01L21/02274 , H01L21/02348 , H01L21/7682 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： A multiphase ultra low k dielectric process is described incorporating a first precursor comprising at least one of carbosilane and alkoxycarbosilane molecules containing the group Si—(CH2)n—Si where n is an integer 1, 2 or 3 and a second precursor containing the group Si—R* where R* is an embedded organic porogen, a high frequency radio frequency power in a PECVD chamber and an energy post treatment including ultraviolet radiation. An ultra low k porous SiCOH dielectric material having at least one of a k in the range from 2.2 to 2.3, 2.3 to 2.4, 2.4 to 2.5, and 2.5 to 2.55 and a modulus of elasticity greater than 5, 6, 7.8 and 9 GPa, respectively and a semiconductor integrated circuit comprising interconnect wiring having porous SiCOH dielectric material as described above.
摘要翻译：描述了一种多相超低k电介质方法，其包括含有碳硅烷和含有Si-（CH 2）n -Si基团的烷氧基碳硅烷分子中的至少一种的第一前体，其中n为整数1,2或3，第二前体包含基团 Si-R *，其中R *是嵌入的有机致孔剂，PECVD室中的高频射频功率和包括紫外线辐射的能量后处理。一种超低k多孔SiCOH介电材料，其具有在2.2至2.3,2.3至2.4,2.4至2.5和2.5至2.55范围内的ak中的至少一种和大于5,6,7,8和9GPa的弹性模量，分别包括如上所述的具有多孔SiCOH介电材料的互连布线的半导体集成电路。

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