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1. 发明授权

US08669147B2 Methods of forming high mobility fin channels on three dimensional semiconductor devices 有权
标题翻译：在三维半导体器件上形成高迁移率翅片通道的方法
公开(公告)号：US08669147B2
公开(公告)日：2014-03-11
申请号：US13493021
申请日：2012-06-11
申请人： Daniel T. Pham , Robert J. Miller , Kingsuk Maitra
发明人： Daniel T. Pham , Robert J. Miller , Kingsuk Maitra
IPC分类号： H01L21/00
CPC分类号： H01L29/1054 , H01L29/66795 , H01L29/785
摘要： Disclosed herein are various methods of forming high mobility fin channels on three dimensional semiconductor devices, such as, for example, FinFET semiconductor devices. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate, wherein the trenches define an original fin structure for the device, and wherein a portion of a mask layer is positioned above the original fin structure, forming a compressively-stressed material in the trenches and adjacent the portion of mask layer, after forming the compressively-stressed material, removing the portion of the mask layer to thereby expose an upper surface of the original fin structure, and forming a final fin structure above the exposed surface of the original fin structure.
摘要翻译：本文公开了在三维半导体器件（例如FinFET半导体器件）上形成高迁移率鳍通道的各种方法。在一个示例中，该方法包括在半导体衬底中形成多个间隔开的沟槽，其中沟槽限定用于器件的原始鳍状结构，并且其中掩模层的一部分位于原始鳍结构的上方，形成在形成压缩应力材料之后，在沟槽中并与掩模层的部分相邻的压缩应力材料，去除掩模层的部分，从而暴露原始鳍状结构的上表面，并且在裸露表面的原有翅片结构。

2. 发明申请

US20130330916A1 METHODS OF FORMING HIGH MOBILITY FIN CHANNELS ON THREE DIMENSIONAL SEMICONDUCTOR DEVICES 有权
标题翻译：在三维半导体器件上形成高移动性融合通道的方法
公开(公告)号：US20130330916A1
公开(公告)日：2013-12-12
申请号：US13493021
申请日：2012-06-11
申请人： Daniel T. Pham , Robert J. Miller , Kingsuk Maitra
发明人： Daniel T. Pham , Robert J. Miller , Kingsuk Maitra
IPC分类号： H01L21/205
CPC分类号： H01L29/1054 , H01L29/66795 , H01L29/785
摘要： Disclosed herein are various methods of forming high mobility fin channels on three dimensional semiconductor devices, such as, for example, FinFET semiconductor devices. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate, wherein the trenches define an original fin structure for the device, and wherein a portion of a mask layer is positioned above the original fin structure, forming a compressively-stressed material in the trenches and adjacent the portion of mask layer, after forming the compressively-stressed material, removing the portion of the mask layer to thereby expose an upper surface of the original fin structure, and forming a final fin structure above the exposed surface of the original fin structure.
摘要翻译：本文公开了在三维半导体器件（例如FinFET半导体器件）上形成高迁移率鳍通道的各种方法。在一个示例中，该方法包括在半导体衬底中形成多个间隔开的沟槽，其中沟槽限定用于器件的原始鳍状结构，并且其中掩模层的一部分位于原始鳍结构的上方，形成在形成压缩应力材料之后，在沟槽中并与掩模层的部分相邻的压缩应力材料，去除掩模层的部分，从而暴露原始鳍状结构的上表面，并且在裸露表面的原有翅片结构。

3. 发明授权

US06838322B2 Method for forming a double-gated semiconductor device 失效
标题翻译：双门控半导体器件的形成方法
公开(公告)号：US06838322B2
公开(公告)日：2005-01-04
申请号：US10427577
申请日：2003-05-01
申请人： Daniel T. Pham , Alexander L. Barr , Leo Mathew , Bich-Yen Nguyen , Anne M. Vandooren , Ted R. White
发明人： Daniel T. Pham , Alexander L. Barr , Leo Mathew , Bich-Yen Nguyen , Anne M. Vandooren , Ted R. White
IPC分类号： H01L21/336 , H01L29/786 , H01L21/00 , H01L21/20 , H01L21/3205
CPC分类号： H01L29/785 , H01L29/66795
摘要： A method for forming a polysilicon FinFET (10) or other thin film transistor structure includes forming an insulative layer (12) over a semiconductor substrate (14). An amorphous silicon layer (32) forms over the insulative layer (12). A silicon germanium seed layer (44) forms in association with the amorphous silicon layer (32) for controlling silicon grain growth. The polysilicon layer arises from annealing the amorphous silicon layer (32). During the annealing step, silicon germanium seed layer (44), together with silicon germanium layer (34), catalyzes silicon recrystallization to promote growing larger crystalline grains, as well as fewer grain boundaries within the resulting polysilicon layer. Source (16), drain (18), and channel (20) regions are formed within the polysilicon layer. A double-gated region (24) forms in association with source (16), drain (18), and channel (20) to produce polysilicon FinFET (10).
摘要翻译：一种用于形成多晶硅FinFET（10）或其它薄膜晶体管结构的方法包括在半导体衬底（14）上形成绝缘层（12）。在绝缘层（12）上形成非晶硅层（32）。与用于控制硅晶粒生长的非晶硅层（32）相关联地形成硅锗籽晶层（44）。多晶硅层由退火非晶硅层（32）引起。在退火步骤期间，硅锗籽晶层（44）与硅锗层（34）一起催化硅重结晶以促进生长较大的晶粒以及所得多晶硅层内的较少的晶界。源极（16），漏极（18）和沟道（20）区域形成在多晶硅层内。与源极（16），漏极（18）和沟道（20）相关联地形成双门控区域（24）以产生多晶硅FinFET（10）。

4. 发明授权

US08664093B2 Methods of forming a silicon seed layer and layers of silicon and silicon-containing material therefrom 有权
标题翻译：形成硅种子层的方法和硅和含硅材料层的方法
公开(公告)号：US08664093B2
公开(公告)日：2014-03-04
申请号：US13476552
申请日：2012-05-21
申请人： Daniel T. Pham , William J. Taylor, Jr.
发明人： Daniel T. Pham , William J. Taylor, Jr.
IPC分类号： H01L21/36 , H01L21/20 , H01L21/336
CPC分类号： H01L21/0245 , H01L21/02532 , H01L21/02612 , H01L21/02639 , H01L21/02658 , H01L29/66795
摘要： Disclosed herein are various methods of forming a silicon seed layer and layers of silicon and silicon-containing material therefrom. In one example, the method includes forming a layer of silicon dioxide above a structure, converting at least a portion of the layer of silicon dioxide into a silicon-salt layer and converting at least a portion of the silicon-salt layer to a layer of silicon.
摘要翻译：本文公开了形成硅种子层的各种方法以及硅和含硅材料的层。在一个实例中，该方法包括在结构之上形成二氧化硅层，将二氧化硅层的至少一部分转化为硅盐层并将至少一部分硅盐层转化为硅。

5. 发明授权

US08309410B2 Power MOSFET with a gate structure of different material 有权
标题翻译：功率MOSFET具有栅极结构不同的材料
公开(公告)号：US08309410B2
公开(公告)日：2012-11-13
申请号：US13088071
申请日：2011-04-15
申请人： Daniel T. Pham , Bich-Yen Nguyen
发明人： Daniel T. Pham , Bich-Yen Nguyen
IPC分类号： H01L21/8238
CPC分类号： H01L29/7833 , H01L21/28105 , H01L29/42372
摘要： A semiconductor device includes a semiconductor layer of a first conductivity type and a first doping concentration. A first semiconductor region, used as drain, of the first conductivity type has a lower doping concentration than the semiconductor layer and is over the semiconductor layer. A gate dielectric is over the first semiconductor region. A gate electrode over the gate dielectric has a metal-containing center portion and first and second silicon portions on opposite sides of the center portion. A second semiconductor region, used as a channel, of the second conductivity type has a first portion under the first silicon portion and the gate dielectric. A third semiconductor region, used as a source, of the first conductivity type is laterally adjacent to the first portion of the second semiconductor region. The metal-containing center portion, replacing silicon, increases the source to drain breakdown voltage.
摘要翻译：半导体器件包括第一导电类型和第一掺杂浓度的半导体层。用作第一导电类型的漏极的第一半导体区域具有比半导体层更低的掺杂浓度，并且在半导体层之上。栅极电介质在第一半导体区域之上。栅极电介质上的栅极电极在中心部分的相对侧上具有含金属的中心部分和第一和第二硅部分。用作第二导电类型的沟道的第二半导体区域具有在第一硅部分下面的第一部分和栅极电介质。用作第一导电类型的源的第三半导体区域与第二半导体区域的第一部分横向相邻。置换硅的含金属中心部分将源极增加到漏极击穿电压。

6. 发明授权

US07645651B2 LDMOS with channel stress 有权
标题翻译： LDMOS具有通道压力
公开(公告)号：US07645651B2
公开(公告)日：2010-01-12
申请号：US11951702
申请日：2007-12-06
申请人： Xiaoqiu Huang , Veeraraghavan Dhandapani , Bich-Yen Nguyen , Amanda M. Kroll , Daniel T. Pham
发明人： Xiaoqiu Huang , Veeraraghavan Dhandapani , Bich-Yen Nguyen , Amanda M. Kroll , Daniel T. Pham
IPC分类号： H01L21/00 , H01L21/84 , H01L21/337 , H01L21/8238 , H01L21/8236 , H01L21/336
CPC分类号： H01L29/7835 , H01L29/1054 , H01L29/161 , H01L29/165 , H01L29/66659 , H01L29/7781
摘要： A method of forming a metal oxide semiconductor (MOS) device comprises defining an active area in an unstrained semiconductor layer structure, depositing a hard mask overlying the active area and a region outside of the active area, patterning the hard mask to expose the active area, selectively growing a strained semiconductor layer overlying the exposed active area, and forming a remainder of the MOS device. The active area includes a first doped region of first conductivity type and a second doped region of second conductivity type. The strained semiconductor layer provides a biaxially strained channel for the MOS device. During a portion of forming the remainder of the MOS device, dopant of the first conductivity type of the first doped region of the active area and dopant of the second conductivity type of the second doped region of the active area diffuses into overlying portions of the strained semiconductor layer to create a correspondingly doped strained semiconductor layer, thereby providing corresponding doping for the biaxially strained channel.
摘要翻译：一种形成金属氧化物半导体（MOS）器件的方法包括：在非限制性半导体层结构中限定有源区，沉积覆盖有源区的硬掩模和有源区外的区域，使硬掩模图形化以暴露有源区选择性地生长覆盖暴露的有源区的应变半导体层，以及形成MOS器件的其余部分。有源区包括第一导电类型的第一掺杂区和第二导电类型的第二掺杂区。应变半导体层为MOS器件提供双向应变通道。在形成MOS器件的其余部分的部分期间，有源区的第一掺杂区的第一导电类型的掺杂剂和有源区的第二掺杂区的第二导电类型的掺杂剂扩散到应变的上覆部分以产生相应掺杂的应变半导体层，从而为双轴应变通道提供相应的掺杂。

7. 发明申请

US20130309846A1 METHODS OF FORMING A SILICON SEED LAYER AND LAYERS OF SILICON AND SILICON-CONTAINING MATERIAL THEREFROM 有权
标题翻译：形成硅层和硅层及其含硅材料的方法
公开(公告)号：US20130309846A1
公开(公告)日：2013-11-21
申请号：US13476552
申请日：2012-05-21
申请人： Daniel T. Pham , William J. Taylor, JR.
发明人： Daniel T. Pham , William J. Taylor, JR.
IPC分类号： H01L21/20
CPC分类号： H01L21/0245 , H01L21/02532 , H01L21/02612 , H01L21/02639 , H01L21/02658 , H01L29/66795
摘要： Disclosed herein are various methods of forming a silicon seed layer and layers of silicon and silicon-containing material therefrom. In one example, the method includes forming a layer of silicon dioxide above a structure, converting at least a portion of the layer of silicon dioxide into a silicon-salt layer and converting at least a portion of the silicon-salt layer to a layer of silicon.
摘要翻译：本文公开了形成硅种子层的各种方法以及硅和含硅材料的层。在一个实例中，该方法包括在结构之上形成二氧化硅层，将二氧化硅层的至少一部分转化为硅盐层并将至少一部分硅盐层转化为硅。

8. 发明申请

US20090146180A1 LDMOS WITH CHANNEL STRESS 有权
标题翻译： LDMOS与通道应力
公开(公告)号：US20090146180A1
公开(公告)日：2009-06-11
申请号：US11951702
申请日：2007-12-06
申请人： Xiaoqiu Huang , Veeraraghavan Dhandapani , Bich-Yen Nguyen , Amanda M. Kroll , Daniel T. Pham
发明人： Xiaoqiu Huang , Veeraraghavan Dhandapani , Bich-Yen Nguyen , Amanda M. Kroll , Daniel T. Pham
IPC分类号： H01L29/778 , H01L21/336
CPC分类号： H01L29/7835 , H01L29/1054 , H01L29/161 , H01L29/165 , H01L29/66659 , H01L29/7781
摘要： A method of forming a metal oxide semiconductor (MOS) device comprises defining an active area in an unstrained semiconductor layer structure, depositing a hard mask overlying the active area and a region outside of the active area, patterning the hard mask to expose the active area, selectively growing a strained semiconductor layer overlying the exposed active area, and forming a remainder of the MOS device. The active area includes a first doped region of first conductivity type and a second doped region of second conductivity type. The strained semiconductor layer provides a biaxially strained channel for the MOS device. During a portion of forming the remainder of the MOS device, dopant of the first conductivity type of the first doped region of the active area and dopant of the second conductivity type of the second doped region of the active area diffuses into overlying portions of the strained semiconductor layer to create a correspondingly doped strained semiconductor layer, thereby providing corresponding doping for the biaxially strained channel.
摘要翻译：一种形成金属氧化物半导体（MOS）器件的方法包括：在非限制性半导体层结构中限定有源区，沉积覆盖有源区的硬掩模和有源区外的区域，使硬掩模图形化以暴露有源区选择性地生长覆盖暴露的有源区的应变半导体层，以及形成MOS器件的其余部分。有源区包括第一导电类型的第一掺杂区和第二导电类型的第二掺杂区。应变半导体层为MOS器件提供双向应变通道。在形成MOS器件的其余部分的部分期间，有源区的第一掺杂区的第一导电类型的掺杂剂和有源区的第二掺杂区的第二导电类型的掺杂剂扩散到应变的上覆部分以产生相应掺杂的应变半导体层，从而为双轴应变通道提供相应的掺杂。

9. 发明授权

US06413819B1 Memory device and method for using prefabricated isolated storage elements 有权
标题翻译：使用预制隔离存储元件的存储器件和方法
公开(公告)号：US06413819B1
公开(公告)日：2002-07-02
申请号：US09595821
申请日：2000-06-16
申请人： Sufi Zafar , Ramachandran Muralidhar , Bich-Yen Nguyen , Sucharita Madhukar , Daniel T. Pham , Michael A. Sadd , Chitra K. Subramanian
发明人： Sufi Zafar , Ramachandran Muralidhar , Bich-Yen Nguyen , Sucharita Madhukar , Daniel T. Pham , Michael A. Sadd , Chitra K. Subramanian
IPC分类号： H01L21336
CPC分类号： B82Y10/00 , H01L21/28273 , H01L29/7883 , H01L29/7888
摘要： A semiconductor device that includes a floating gate made up of a plurality of pre-formed isolated storage elements (18) and a method for making such a device is presented. The device is formed by first providing a semiconductor layer (12) upon which a first gate insulator (14) is formed. A plurality of pre-fabricated isolated storage elements (18) is then deposited on the first gate insulator (14). This deposition step may be accomplished by immersion in a colloidal solution (16) that includes a solvent and pre-fabricated isolated storage elements (18). Once deposited, the solvent of the solution (16) can be removed, leaving the pre-fabricated isolated storage elements (18) deposited on the first gate insulator (14). After depositing the pre-fabricated isolated storage elements (18), a second gate insulator (20) is formed over the pre-fabricated isolated storage elements (18). A gate electrode (24) is then formed over the second gate insulator (20), and portions the first and second gate insulators and the plurality of pre-fabricated isolated storage elements that do not underlie the gate electrode are selectively removed. A source region (32) and a drain region (34) are then formed in the semiconductor layer (12) such that a channel region is formed between underlying the gate electrode (24).
摘要翻译：提供了一种半导体器件，其包括由多个预先形成的隔离存储元件（18）构成的浮动栅极和用于制造这种器件的方法。该器件通过首先提供形成第一栅极绝缘体（14）的半导体层（12）形成。然后，多个预制隔离存储元件（18）沉积在第一栅极绝缘体（14）上。该沉积步骤可以通过浸入包括溶剂和预制隔离存储元件（18）的胶体溶液（16）中来实现。一旦沉积，可以除去溶液（16）的溶剂，留下沉积在第一栅极绝缘体（14）上的预制隔离存储元件（18）。在沉积预制隔离存储元件（18）之后，在预制隔离存储元件（18）上形成第二栅极绝缘体（20）。然后，在第二栅极绝缘体（20）之上形成栅电极（24），并且选择性地去除不在栅电极下面的第一和第二栅极绝缘体和多个预制隔离存储元件的部分。然后在半导体层（12）中形成源极区（32）和漏极区（34），使得在栅电极（24）下方形成沟道区。

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