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1. 发明授权

US5140193A Programmable connector for programmable logic device 失效
标题翻译：可编程逻辑器件的可编程连接器
公开(公告)号：US5140193A
公开(公告)日：1992-08-18
申请号：US499759
申请日：1990-03-27
申请人： Ross H. Freeman, deceased , Khue Duong , Hung-Cheng Hsieh , Charles R. Erickson , William S. Carter
发明人： Ross H. Freeman, deceased , Khue Duong , Hung-Cheng Hsieh , Charles R. Erickson , William S. Carter
IPC分类号： G06F3/00 , H01L21/82 , H03K19/173
CPC分类号： H03K19/1736
摘要： A structure especially useful in a configurable logic array includes a plurality of conductive interconnect lines located along the perimeter of a logic array chip. Lines running from exterior pins or pads can be used by a programmable interconnect circuit to control signals applied to these interconnect lines. In particular, both the signal and the complement of the signal can be used by the programmable interconnect to control application of a supply voltage to an interconnect line. A second supply voltage is applied through a resistor to the interconnect line with the result that the interconnect line will carry a logical signal representing a logical function, for example AND, of a selected set of input signals or their complements. Lines running from points interior to the configurable logic array chip may also contribute to the signal generated on an interconnect line. In one embodiment, bidirectional programmable interconnect circuits allow the input pins to function as either input or output pins. An application of the decoder circuit is described for use with a latch as a data/address demultiplexer.

2. 发明授权

US5880492A Dedicated local line interconnect layout 失效
标题翻译：专用本地线路互连布局
公开(公告)号：US5880492A
公开(公告)日：1999-03-09
申请号：US543532
申请日：1995-10-16
申请人： Khue Duong , Stephen M. Trimberger
发明人： Khue Duong , Stephen M. Trimberger
IPC分类号： H03K19/177 , H01K27/10
CPC分类号： H03K19/17736 , H03K19/1778 , H03K19/17792
摘要： An electrical connection arrangement for a programmable integrated circuit is provided. An electrical device is disposed proximate to a vertical longline which is used for transporting address and data signals. The electrical device includes a vertical address line extending from the device. A horizontally arranged interconnection line is electrically connected to the vertical address line extending from the device. Furthermore, the horizontally arranged interconnection line is programmably connectable to the vertical longline. By electrically hardwire connecting the horizontally arranged interconnection line to the vertical address line extending from the device, only one programmable interconnect point is required to transfer signals from the vertical longline into the electrical device itself. Thus, impedance is reduced, while addressing speed is improved. Also, by adding additional horizontal interconnect lines, the present invention reduces routing barriers.
摘要翻译：提供了一种用于可编程集成电路的电连接装置。电气设备靠近用于传送地址和数据信号的垂直延长线设置。电气设备包括从设备延伸的垂直地址线。水平布置的互连线电连接到从设备延伸的垂直地址线。此外，水平布置的互连线可编程地连接到垂直延长线。通过电连接将水平布置的互连线连接到从器件延伸的垂直地址线，仅需要一个可编程互连点，将信号从垂直延长线传输到电子器件本身。因此，减小了阻抗，同时提高了寻址速度。此外，通过添加额外的水平互连线，本发明减少了路由障碍。

3. 发明授权

US5815004A Multi-buffered configurable logic block output lines in a field programmable gate array 失效
标题翻译：现场可编程门阵列中的多缓冲可配置逻辑块输出线
公开(公告)号：US5815004A
公开(公告)日：1998-09-29
申请号：US543591
申请日：1995-10-16
申请人： Stephen M. Trimberger , Khue Duong
发明人： Stephen M. Trimberger , Khue Duong
IPC分类号： H03K19/177 , H03K7/38
CPC分类号： H03K19/17736 , H03K19/17728 , H03K19/17792
摘要： A field programmable gate array having independently buffered output lines of a CLB for handling critical path situations. One of the CLB's output ports is coupled to a vertical interconnect line and a horizontal interconnect line. Two separate buffers are used to drive these lines. One buffer drives the horizontal interconnect line, while the other drives the vertical interconnect line. One of these lines is used to conduct the output signal that corresponds to the critical path. The other line is used to conduct the output signal onto other branches that are not part of the critical path. Hence, by using a separate buffer to drive the critical path, it is not loaded with the circuits associated with the non-critical branches.
摘要翻译：具有用于处理关键路径情况的CLB的独立缓冲输出线的现场可编程门阵列。 CLB的输出端口之一耦合到垂直互连线和水平互连线。使用两个单独的缓冲区来驱动这些线路。一个缓冲器驱动水平互连线，而另一个缓冲器驱动垂直互连线。这些线之一用于进行与关键路径对应的输出信号。另一条线用于将输出信号传导到不属于关键路径的其他分支上。因此，通过使用单独的缓冲器来驱动关键路径，它不会加载与非关键分支相关联的电路。

4. 发明授权

US5880598A Tile-based modular routing resources for high density programmable logic device 失效
标题翻译：基于瓦片的模块化路由资源，用于高密度可编程逻辑器件
公开(公告)号：US5880598A
公开(公告)日：1999-03-09
申请号：US781251
申请日：1997-01-10
申请人： Khue Duong
发明人： Khue Duong
IPC分类号： H03K19/177 , H03K7/38
CPC分类号： H03K19/17736 , H03K19/17796
摘要： Signal routing resource tiles that can be manipulated as circuit "cells" in that they can be readily characterized and implemented on a programmable logic device, e.g., a field programmable gate array (FPGA). In one embodiment, vertical placement and horizontal placement routing resource tiles are provided. Routing resources tiles may be selectively added in areas of the programmable logic device determined to be prone to high signal congestion, e.g., the central portions of the array, and along the array perimeter. The additional routing resource tiles simplify routing for complex logic functions and increase utilization of configurable logic blocks (CLBs) forming the array. The tiles can be positioned within the array in any position horizontally or vertically within the CLB array. Specifically, placement can be either in the core of the chip or along the periphery with each tile providing programmable connections to the existing routing resources (e.g., input/output ports) within the CLBs. A corner tile is also provided that permits interconnection between horizontal and vertical tiles. The tiles are modular in nature so the number of tiles provided within an array and their placement are determined based on the array's particular need for routing resources, e.g., an array can have one, two or more tiles associated with a row or column of CLBs in areas of the chip where congestion is typically encountered. Each tile of the present invention can also include a plurality of switch matrices, buffers, or other active gates to facilitate signal routing.
摘要翻译：可以被操纵为电路“单元”的信号路由资源块，因为它们可以容易地在可编程逻辑器件（例如现场可编程门阵列（FPGA））上表征和实现。在一个实施例中，提供垂直布置和水平布置布线资源瓦片。路由资源瓦片可以被选择性地添加到被确定为容易发生高信号拥塞的可编程逻辑设备的区域中，例如阵列的中心部分以及阵列周边。额外的路由资源瓦片简化了复杂逻辑功能的路由，并提高了构成阵列的可配置逻辑块（CLB）的利用率。可以在CLB阵列内水平或垂直的任何位置将瓦片定位在阵列内。具体来说，放置可以在芯片的核心中，也可以沿着周边，每个瓦片提供到CLB内的现有路由资源（例如，输入/输出端口）的可编程连接。还提供了一个角瓦，可以允许水平和垂直瓦片之间的互连。瓦片本质上是模块化的，因此阵列中提供的瓦片数量及其布局是基于阵列对路由资源的特殊需求来确定的，例如，阵列可以具有与CLB的行或列相关联的一个，两个或更多个瓦片在通常遇到拥塞的芯片的区域中。本发明的每个瓦片还可以包括多个开关矩阵，缓冲器或其他有源门以便于信号路由。

5. 发明授权

US5600264A Programmable single buffered six pass transistor configuration 失效
标题翻译：可编程单缓冲六通晶体管配置
公开(公告)号：US5600264A
公开(公告)日：1997-02-04
申请号：US543454
申请日：1995-10-16
申请人： Khue Duong , Stephen M. Trimberger , Alok Mehrotra
发明人： Khue Duong , Stephen M. Trimberger , Alok Mehrotra
IPC分类号： H03K17/693 , H03K19/173 , H03K19/177 , H03K19/01
CPC分类号： H03K19/1736 , H03K17/693 , H03K19/17704
摘要： A programmable single buffered six transistor switch box is provided. A six transistor switch box acts as a programmable junction between four intersecting lines. The switch box allows any two of the lines to be programmably interconnected to form a signal channel. Alternatively, two sets of the four lines can also be programmably interconnected so that two signal channels are formed. The present invention modifies the known six transistor switch box so that one line output from the switch box can be programmably buffered. By buffering the output signal, delay introduced by resistance and capacitance of the transistors switch box is significantly reduced. For short line lengths, the buffer delay can be greater than the delay associated with the resistance and capacitance of the transistors of the switch box. In these cases, the output is not buffered and the buffer is programmably bypassed. Although there are four possible outputs that can be programmably selected in the present invention switch box, the present invention advantageously utilizes a single buffer resource to perform output buffering. A multiplexer circuit and demultiplexer circuit configuration is used to perform the proper routing.
摘要翻译：提供可编程单缓冲六晶体管开关盒。六个晶体管开关盒作为四条相交线之间的可编程连接。开关盒允许任何两条线路可编程地互连以形成信号通道。或者，四组的两组也可编程互连，从而形成两个信号通道。本发明修改已知的六个晶体管开关盒，从而可以可编程地缓冲来自开关盒的一行输出。通过缓冲输出信号，晶体管开关盒的电阻和电容引入的延迟显着降低。对于短线路长度，缓冲器延迟可以大于与开关盒的晶体管的电阻和电容相关联的延迟。在这些情况下，输出不缓冲，缓冲区可编程旁路。尽管在本发明的开关盒中可以可编程地选择四个可能的输出，但是本发明有利地利用单个缓冲器资源来执行输出缓冲。多路复用器电路和解复用器电路配置用于执行正确的路由。

6. 发明授权

US5689133A ESD protection circuit 失效
标题翻译： ESD保护电路
公开(公告)号：US5689133A
公开(公告)日：1997-11-18
申请号：US709611
申请日：1996-09-09
申请人： Sheau-Suey Li , Randy T. Ong , Samuel Broydo , Khue Duong
发明人： Sheau-Suey Li , Randy T. Ong , Samuel Broydo , Khue Duong
IPC分类号： H01L27/02 , H01L23/62
CPC分类号： H01L27/0251 , H01L27/0259
摘要： An ESD protection circuit combines a split bipolar transistor with a transistor layout which exhibits very high tolerance to ESD events. The split bipolar transistor divides current among many segments and prevents the current hogging which often causes an ESD failure. Several splitting structures are disclosed, each combining a resistor in series with each segment to distribute current evenly. The transistor takes advantage of the snap-back effect to increase current carrying capacity. Layout positions metal contacts away from regions of highest energy dissipation. Layout also allows high currents to be dissipated through ESD protection structures and not through circuit devices such as output drivers or through parasitic bipolar transistors not designed for high current. Sharp changes in electron density are avoided by the use of high-diffusing phosphorus in N-regions implanted to both lightly and heavily doped levels. Critical corners are rounded rather than sharp. Certain P-type channel stop implants are positioned away from nearby N-regions to increase breakdown voltage.
摘要翻译： ESD保护电路将分离双极晶体管与晶体管布局相结合，对ESD事件表现出非常高的耐受性。分离双极晶体管在许多段之间划分电流，并防止通常导致ESD故障的电流异常。公开了几种分裂结构，每个组合电阻器与每个段串联以分布电流均匀。晶体管利用闪回效应来增加载流能力。布局位置金属触点远离能量消耗最高的区域。布局还允许高电流通过ESD保护结构消散，而不是通过电路设备（如输出驱动器）或通过非高电流设计的寄生双极型晶体管来消除。通过在注入轻掺杂和重掺杂水平的N区中使用高扩散性磷来避免电子密度的急剧变化。关键角是圆形而不是锋利的。某些P型通道停止植入物远离附近的N区域以增加击穿电压。

7. 发明授权

US5675262A Fast carry-out scheme in a field programmable gate array 失效
标题翻译：在现场可编程门阵列中的快速执行方案
公开(公告)号：US5675262A
公开(公告)日：1997-10-07
申请号：US548775
申请日：1995-10-26
申请人： Khue Duong , Stephen M. Trimberger , Bernard J. New
发明人： Khue Duong , Stephen M. Trimberger , Bernard J. New
IPC分类号： H03K19/177
CPC分类号： H03K19/17748 , H03K19/17704 , H03K19/17736
摘要： A fast carry-out scheme in a field programmable logic array. The configurable logic blocks (CLBs) are arranged in columns. The carry-out signals are routed from the bottom CLB of a column to the top CLB of that column. The carry-out from the top-most CLB is then multiplexed onto a clock line that is normally used to conduct clocking signals to the CLBs. Instead of conducting clocking signals, the existing clock line is now used to route the carry-out signal onto a vertical longline spanning the entire height of the column. Eventually, the carry-out signal is routed from the longline to its destination CLB of the adjacent column via local interconnect resources.
摘要翻译：现场可编程逻辑阵列中的快速实现方案。可配置逻辑块（CLB）按列排列。进位信号从列的底部CLB路由到该列的顶部CLB。然后，最顶层CLB的进位复用到通常用于向CLB传送时钟信号的时钟线上。现在的时钟线代替传输时钟信号，而不是用于将进位信号路由到跨越列的整个高度的垂直延长线。最终，进位信号通过局部互连资源从延长线路路由到相邻列的目的地CLB。

8. 发明授权

US5656950A Interconnect lines including tri-directional buffer circuits 失效
标题翻译：互连线路包括三向缓冲电路
公开(公告)号：US5656950A
公开(公告)日：1997-08-12
申请号：US548791
申请日：1995-10-26
申请人： Khue Duong , Stephen M. Trimberger
发明人： Khue Duong , Stephen M. Trimberger
IPC分类号： H03K19/0185 , H03K19/177 , H03K19/173
CPC分类号： H03K19/17736 , H03K19/018592 , H03K19/17704
摘要： A metal interconnect line for conducting a first signal from a first line segment of a field programmable gate array to a second line segment. The metal interconnect line substantially spans across the width of the field programmable gate array and has at least one bi-directional buffer that separates the metal interconnect line into a plurality of independent segments. Each of these segments can conduct signals independently from the other segments when the bidirectional buffer is in a tristate mode. Alternatively, a single signal may be routed through the entire length of the metal line in one or the other direction, and repowered along the way. One or more of the bi-directional buffers are used to actively drive the signal(s) onto later segments of the metal interconnect line.
摘要翻译：一种金属互连线，用于将来自现场可编程门阵列的第一线段的第一信号传导到第二线段。金属互连线基本跨越现场可编程门阵列的宽度，并且具有将金属互连线分离成多个独立段的至少一个双向缓冲器。当双向缓冲器处于三态模式时，这些段中的每一个可独立于其它段进行信号。或者，单个信号可以在一个或另一个方向上穿过金属线的整个长度，并沿途重新驱动。一个或多个双向缓冲器用于主动地将信号驱动到金属互连线的稍后段上。

9. 发明授权

US5477414A ESD protection circuit 失效
标题翻译： ESD保护电路
公开(公告)号：US5477414A
公开(公告)日：1995-12-19
申请号：US58189
申请日：1993-05-03
申请人： Sheau-Suey Li , Randy T. Ong , Samuel Broydo , Khue Duong
发明人： Sheau-Suey Li , Randy T. Ong , Samuel Broydo , Khue Duong
IPC分类号： H01L27/02 , H02H9/04
CPC分类号： H01L27/0251 , H01L27/0259
摘要： An ESD protection circuit combines a split bipolar transistor with a transistor layout which exhibits very high tolerance to ESD events. The split bipolar transistor divides current among many segments and prevents the current hogging which often causes an ESD failure. Several splitting structures are disclosed, each combining a resistor in series with each segment to distribute current evenly. The transistor takes advantage of the snap-back effect to increase current carrying capacity. Layout positions metal contacts away from regions of highest energy dissipation. Layout also allows high currents to be dissipated through ESD protection structures and not through circuit devices such as output drivers or through parasitic bipolar transistors not designed for high current. Sharp changes in electron density are avoided by the use of high-diffusing phosphorus in N-regions implanted to both lightly and heavily doped levels. Critical corners are rounded rather than sharp. Certain P-type channel stop implants are positioned away from nearby N-regions to increase breakdown voltage.
摘要翻译： ESD保护电路将分离双极晶体管与晶体管布局相结合，对ESD事件表现出非常高的耐受性。分离双极晶体管在许多段之间划分电流，并防止通常导致ESD故障的电流异常。公开了几种分裂结构，每个组合电阻器与每个段串联以分布电流均匀。晶体管利用闪回效应来增加载流能力。布局位置金属触点远离能量消耗最高的区域。布局还允许高电流通过ESD保护结构消散，而不是通过电路设备（如输出驱动器）或通过非高电流设计的寄生双极型晶体管来消除。通过在注入轻掺杂和重掺杂水平的N区中使用高扩散性磷来避免电子密度的急剧变化。关键角是圆形而不是锋利的。某些P型通道停止植入物远离附近的N区域以增加击穿电压。

10. 发明授权

US5811985A Output multiplexer circuit for input/output block 失效
标题翻译：用于输入/输出块的输出多路复用器电路
公开(公告)号：US5811985A
公开(公告)日：1998-09-22
申请号：US783389
申请日：1997-01-31
申请人： Stephen M. Trimberger , Khue Duong , Robert O. Conn, Jr.
发明人： Stephen M. Trimberger , Khue Duong , Robert O. Conn, Jr.
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/17744 , H03K19/1737 , H03K19/17704
摘要： A input/output circuit (IOB) within an integrated circuit (IC) device, the output signal driving circuitry of the input/output device contains a dedicated multiplexer on the output path wherein a first and second output signal can be time multiplexed on a single output pad. The multiplexer can also be configured to perform as a high speed gate to realize AND, OR, XOR, and XNOR functions. Within an input/output circuit of a programmable integrated circuit, the system provides a dedicated multiplexer that can select between one of two output signals for sending over the single output pad of the IC device. In lieu of using a programmable memory cell as the select control for the dedicated multiplexer, the system allows a number of lines, including an output clock signal, to be the select control. By using the output clock as the select control, the data signals can be effectively time multiplexed over a single output pad and referenced by the output clock. This output multiplexer circuit effectively doubles the number of output signals the IC device can provide with a given number of output pads. The dedicated multiplexer when configured as a high speed gate is useful for generating very high speed system level reset or enable signals or any logic function.
摘要翻译：在集成电路（IC）装置内的输入/输出电路（IOB）中，输入/输出装置的输出信号驱动电路在输出路径上包含专用多路复用器，其中第一和第二输出信号可以在单个输出板。复用器也可以被配置为执行高速门以实现AND，OR，XOR和XNOR功能。在可编程集成电路的输入/输出电路内，该系统提供专用多路复用器，其可以在两个输出信号中的一个之间进行选择，以便通过IC器件的单个输出焊盘进行发送。代替使用可编程存储器单元作为专用多路复用器的选择控制，系统允许包括输出时钟信号在内的多条线路成为选择控制。通过使用输出时钟作为选择控制，数据信号可以在单个输出焊盘上有效地进行时分复用，并由输出时钟参考。该输出多路复用器电路有效地将IC器件可以提供的输出信号的数量加倍到给定数量的输出焊盘。配置为高速门时的专用多路复用器可用于产生非常高速的系统级复位或使能信号或任何逻辑功能。

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