专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5675262A Fast carry-out scheme in a field programmable gate array 失效
标题翻译：在现场可编程门阵列中的快速执行方案
公开(公告)号：US5675262A
公开(公告)日：1997-10-07
申请号：US548775
申请日：1995-10-26
申请人： Khue Duong , Stephen M. Trimberger , Bernard J. New
发明人： Khue Duong , Stephen M. Trimberger , Bernard J. New
IPC分类号： H03K19/177
CPC分类号： H03K19/17748 , H03K19/17704 , H03K19/17736
摘要： A fast carry-out scheme in a field programmable logic array. The configurable logic blocks (CLBs) are arranged in columns. The carry-out signals are routed from the bottom CLB of a column to the top CLB of that column. The carry-out from the top-most CLB is then multiplexed onto a clock line that is normally used to conduct clocking signals to the CLBs. Instead of conducting clocking signals, the existing clock line is now used to route the carry-out signal onto a vertical longline spanning the entire height of the column. Eventually, the carry-out signal is routed from the longline to its destination CLB of the adjacent column via local interconnect resources.
摘要翻译：现场可编程逻辑阵列中的快速实现方案。可配置逻辑块（CLB）按列排列。进位信号从列的底部CLB路由到该列的顶部CLB。然后，最顶层CLB的进位复用到通常用于向CLB传送时钟信号的时钟线上。现在的时钟线代替传输时钟信号，而不是用于将进位信号路由到跨越列的整个高度的垂直延长线。最终，进位信号通过局部互连资源从延长线路路由到相邻列的目的地CLB。

2. 发明授权

US5880492A Dedicated local line interconnect layout 失效
标题翻译：专用本地线路互连布局
公开(公告)号：US5880492A
公开(公告)日：1999-03-09
申请号：US543532
申请日：1995-10-16
申请人： Khue Duong , Stephen M. Trimberger
发明人： Khue Duong , Stephen M. Trimberger
IPC分类号： H03K19/177 , H01K27/10
CPC分类号： H03K19/17736 , H03K19/1778 , H03K19/17792
摘要： An electrical connection arrangement for a programmable integrated circuit is provided. An electrical device is disposed proximate to a vertical longline which is used for transporting address and data signals. The electrical device includes a vertical address line extending from the device. A horizontally arranged interconnection line is electrically connected to the vertical address line extending from the device. Furthermore, the horizontally arranged interconnection line is programmably connectable to the vertical longline. By electrically hardwire connecting the horizontally arranged interconnection line to the vertical address line extending from the device, only one programmable interconnect point is required to transfer signals from the vertical longline into the electrical device itself. Thus, impedance is reduced, while addressing speed is improved. Also, by adding additional horizontal interconnect lines, the present invention reduces routing barriers.
摘要翻译：提供了一种用于可编程集成电路的电连接装置。电气设备靠近用于传送地址和数据信号的垂直延长线设置。电气设备包括从设备延伸的垂直地址线。水平布置的互连线电连接到从设备延伸的垂直地址线。此外，水平布置的互连线可编程地连接到垂直延长线。通过电连接将水平布置的互连线连接到从器件延伸的垂直地址线，仅需要一个可编程互连点，将信号从垂直延长线传输到电子器件本身。因此，减小了阻抗，同时提高了寻址速度。此外，通过添加额外的水平互连线，本发明减少了路由障碍。

3. 发明授权

US5600264A Programmable single buffered six pass transistor configuration 失效
标题翻译：可编程单缓冲六通晶体管配置
公开(公告)号：US5600264A
公开(公告)日：1997-02-04
申请号：US543454
申请日：1995-10-16
申请人： Khue Duong , Stephen M. Trimberger , Alok Mehrotra
发明人： Khue Duong , Stephen M. Trimberger , Alok Mehrotra
IPC分类号： H03K17/693 , H03K19/173 , H03K19/177 , H03K19/01
CPC分类号： H03K19/1736 , H03K17/693 , H03K19/17704
摘要： A programmable single buffered six transistor switch box is provided. A six transistor switch box acts as a programmable junction between four intersecting lines. The switch box allows any two of the lines to be programmably interconnected to form a signal channel. Alternatively, two sets of the four lines can also be programmably interconnected so that two signal channels are formed. The present invention modifies the known six transistor switch box so that one line output from the switch box can be programmably buffered. By buffering the output signal, delay introduced by resistance and capacitance of the transistors switch box is significantly reduced. For short line lengths, the buffer delay can be greater than the delay associated with the resistance and capacitance of the transistors of the switch box. In these cases, the output is not buffered and the buffer is programmably bypassed. Although there are four possible outputs that can be programmably selected in the present invention switch box, the present invention advantageously utilizes a single buffer resource to perform output buffering. A multiplexer circuit and demultiplexer circuit configuration is used to perform the proper routing.
摘要翻译：提供可编程单缓冲六晶体管开关盒。六个晶体管开关盒作为四条相交线之间的可编程连接。开关盒允许任何两条线路可编程地互连以形成信号通道。或者，四组的两组也可编程互连，从而形成两个信号通道。本发明修改已知的六个晶体管开关盒，从而可以可编程地缓冲来自开关盒的一行输出。通过缓冲输出信号，晶体管开关盒的电阻和电容引入的延迟显着降低。对于短线路长度，缓冲器延迟可以大于与开关盒的晶体管的电阻和电容相关联的延迟。在这些情况下，输出不缓冲，缓冲区可编程旁路。尽管在本发明的开关盒中可以可编程地选择四个可能的输出，但是本发明有利地利用单个缓冲器资源来执行输出缓冲。多路复用器电路和解复用器电路配置用于执行正确的路由。

4. 发明授权

US5815004A Multi-buffered configurable logic block output lines in a field programmable gate array 失效
标题翻译：现场可编程门阵列中的多缓冲可配置逻辑块输出线
公开(公告)号：US5815004A
公开(公告)日：1998-09-29
申请号：US543591
申请日：1995-10-16
申请人： Stephen M. Trimberger , Khue Duong
发明人： Stephen M. Trimberger , Khue Duong
IPC分类号： H03K19/177 , H03K7/38
CPC分类号： H03K19/17736 , H03K19/17728 , H03K19/17792
摘要： A field programmable gate array having independently buffered output lines of a CLB for handling critical path situations. One of the CLB's output ports is coupled to a vertical interconnect line and a horizontal interconnect line. Two separate buffers are used to drive these lines. One buffer drives the horizontal interconnect line, while the other drives the vertical interconnect line. One of these lines is used to conduct the output signal that corresponds to the critical path. The other line is used to conduct the output signal onto other branches that are not part of the critical path. Hence, by using a separate buffer to drive the critical path, it is not loaded with the circuits associated with the non-critical branches.
摘要翻译：具有用于处理关键路径情况的CLB的独立缓冲输出线的现场可编程门阵列。 CLB的输出端口之一耦合到垂直互连线和水平互连线。使用两个单独的缓冲区来驱动这些线路。一个缓冲器驱动水平互连线，而另一个缓冲器驱动垂直互连线。这些线之一用于进行与关键路径对应的输出信号。另一条线用于将输出信号传导到不属于关键路径的其他分支上。因此，通过使用单独的缓冲器来驱动关键路径，它不会加载与非关键分支相关联的电路。

5. 发明授权

US5656950A Interconnect lines including tri-directional buffer circuits 失效
标题翻译：互连线路包括三向缓冲电路
公开(公告)号：US5656950A
公开(公告)日：1997-08-12
申请号：US548791
申请日：1995-10-26
申请人： Khue Duong , Stephen M. Trimberger
发明人： Khue Duong , Stephen M. Trimberger
IPC分类号： H03K19/0185 , H03K19/177 , H03K19/173
CPC分类号： H03K19/17736 , H03K19/018592 , H03K19/17704
摘要： A metal interconnect line for conducting a first signal from a first line segment of a field programmable gate array to a second line segment. The metal interconnect line substantially spans across the width of the field programmable gate array and has at least one bi-directional buffer that separates the metal interconnect line into a plurality of independent segments. Each of these segments can conduct signals independently from the other segments when the bidirectional buffer is in a tristate mode. Alternatively, a single signal may be routed through the entire length of the metal line in one or the other direction, and repowered along the way. One or more of the bi-directional buffers are used to actively drive the signal(s) onto later segments of the metal interconnect line.
摘要翻译：一种金属互连线，用于将来自现场可编程门阵列的第一线段的第一信号传导到第二线段。金属互连线基本跨越现场可编程门阵列的宽度，并且具有将金属互连线分离成多个独立段的至少一个双向缓冲器。当双向缓冲器处于三态模式时，这些段中的每一个可独立于其它段进行信号。或者，单个信号可以在一个或另一个方向上穿过金属线的整个长度，并沿途重新驱动。一个或多个双向缓冲器用于主动地将信号驱动到金属互连线的稍后段上。

6. 发明授权

US5811985A Output multiplexer circuit for input/output block 失效
标题翻译：用于输入/输出块的输出多路复用器电路
公开(公告)号：US5811985A
公开(公告)日：1998-09-22
申请号：US783389
申请日：1997-01-31
申请人： Stephen M. Trimberger , Khue Duong , Robert O. Conn, Jr.
发明人： Stephen M. Trimberger , Khue Duong , Robert O. Conn, Jr.
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/17744 , H03K19/1737 , H03K19/17704
摘要： A input/output circuit (IOB) within an integrated circuit (IC) device, the output signal driving circuitry of the input/output device contains a dedicated multiplexer on the output path wherein a first and second output signal can be time multiplexed on a single output pad. The multiplexer can also be configured to perform as a high speed gate to realize AND, OR, XOR, and XNOR functions. Within an input/output circuit of a programmable integrated circuit, the system provides a dedicated multiplexer that can select between one of two output signals for sending over the single output pad of the IC device. In lieu of using a programmable memory cell as the select control for the dedicated multiplexer, the system allows a number of lines, including an output clock signal, to be the select control. By using the output clock as the select control, the data signals can be effectively time multiplexed over a single output pad and referenced by the output clock. This output multiplexer circuit effectively doubles the number of output signals the IC device can provide with a given number of output pads. The dedicated multiplexer when configured as a high speed gate is useful for generating very high speed system level reset or enable signals or any logic function.
摘要翻译：在集成电路（IC）装置内的输入/输出电路（IOB）中，输入/输出装置的输出信号驱动电路在输出路径上包含专用多路复用器，其中第一和第二输出信号可以在单个输出板。复用器也可以被配置为执行高速门以实现AND，OR，XOR和XNOR功能。在可编程集成电路的输入/输出电路内，该系统提供专用多路复用器，其可以在两个输出信号中的一个之间进行选择，以便通过IC器件的单个输出焊盘进行发送。代替使用可编程存储器单元作为专用多路复用器的选择控制，系统允许包括输出时钟信号在内的多条线路成为选择控制。通过使用输出时钟作为选择控制，数据信号可以在单个输出焊盘上有效地进行时分复用，并由输出时钟参考。该输出多路复用器电路有效地将IC器件可以提供的输出信号的数量加倍到给定数量的输出焊盘。配置为高速门时的专用多路复用器可用于产生非常高速的系统级复位或使能信号或任何逻辑功能。

7. 发明授权

US5712579A Deskewed clock distribution network with edge clock 失效
标题翻译：带有边缘时钟的偏光时钟分配网络
公开(公告)号：US5712579A
公开(公告)日：1998-01-27
申请号：US543693
申请日：1995-10-16
申请人： Khue Duong , Stephen M. Trimberger , Robert O. Conn, Jr. , John E. Mahoney
发明人： Khue Duong , Stephen M. Trimberger , Robert O. Conn, Jr. , John E. Mahoney
IPC分类号： H03K5/15 , H03K19/177 , H03K19/00
CPC分类号： H03K19/1774 , H03K19/17704 , H03K5/1502
摘要： A clock distribution network and mechanisms therein for an integrated circuit (IC) including an edge clock and distribution system for same. The invention includes a deskewed clock distribution network for circuits situated in columns wherein buffering is done in columns less than half of the IC length. The mechanism allows each of at least eight vertical column distribution lines to couple with any horizontal clock supply line of at least eight lines. The horizontal clock supply lines include local interconnect inputs. To increase clock source signals, special lines, Kx lines, are provided that are buffered and traverse directionally in 1/4 IC lengths from the top down, bottom up, and midsection both up and down. Kx lines can be sourced from carry signals, IOBs, interconnects, or from an edge clock and supply to clock lines, longlines, or interconnect lines. Kx lines allow vertical signal displacement, e.g., for clock signals, etc., within the chip. An edge clock is provided that is not deskewed and is directly coupled to an edge clock distribution system along the left and right edges of the IC to supply a clock signal to an entire edge or half of an edge with less delay relative to the deskewed clock. Also, a super fast edge clock is provided for very high speed circuits.
摘要翻译：一种用于集成电路（IC）的时钟分配网络及其机构，包括用于其的边缘时钟和分配系统。本发明包括用于位于列中的电路的偏斜校正时钟分配网络，其中缓冲在小于IC长度的一半的列中进行。该机构允许至少八个垂直列分配线中的每一个与至少八行的任何水平时钟供应线耦合。水平时钟电源线包括局部互连输入。为了增加时钟源信号，提供专门的线路Kx线，它们在+ E中进行缓冲和定向移动，从上到下，从上到下和上下中间的1/4 + EE IC长度。 Kx线可以来自进位信号，IOB，互连或从边沿时钟提供到时钟线，延长线或互连线。 Kx线允许垂直信号位移，例如芯片内的时钟信号等。提供边缘时钟，其不进行去校正，并且沿着IC的左边缘和右边缘直接耦合到边缘时钟分配系统，以将时钟信号提供给相对于偏移校正时钟的延迟较小的边缘的整个边缘或一半。此外，为超高速电路提供超快速时钟。

8. 发明授权

US5642058A Periphery input/output interconnect structure 失效
标题翻译：周边输入/输出互连结构
公开(公告)号：US5642058A
公开(公告)日：1997-06-24
申请号：US543534
申请日：1995-10-16
申请人： Stephen M. Trimberger , Khue Duong
发明人： Stephen M. Trimberger , Khue Duong
IPC分类号： H03K19/177
CPC分类号： H03K19/17796 , H03K19/17704
摘要： A mechanism is provided for allowing input/output signal routing along the periphery of a programmable integrated circuit (IC) so that uniform circuit usage across the programmable integrated circuit is allowed in conjunction with predetermined pin assignments. The mechanism includes a plurality of periphery interconnect lines that run along the periphery of a programmable IC. Input/output blocks (IOBs) that are similarly along the periphery of the programmable IC and configurable logic blocks (CLBs) are coupled to the plurality of periphery interconnect lines using a programmable local interconnect structure. Each IOB includes an associated pad and an input/output external pin. Individual segments of the plurality of periphery interconnect lines utilize a bi-directional buffer to buffer a line of the periphery interconnect. Uniform buffered segments of the periphery interconnect are disposed such that for an interconnect of n lines, each line of the periphery interconnect is buffered at least once every n segments. In operation, a CLB located away from the periphery of the IC can output a signal over the local interconnect, onto the plurality of periphery interconnect lines, onto another local interconnect, into an IOB and over its external pin. To input a signal, the path is reversed. The pin and the CLB do not need to be adjacent.
摘要翻译：提供了一种用于允许沿着可编程集成电路（IC）的周边进行输入/输出信号路由的机制，使得跨越可编程集成电路的均匀电路使用被允许结合预定的引脚分配。该机构包括沿可编程IC的周边延伸的多个周边互连线。类似地沿着可编程IC和可配置逻辑块（CLB）的周边的输入/输出块（IOB）使用可编程局部互连结构耦合到多个外围互连线。每个IOB包括一个相关的焊盘和一个输入/输出外部引脚。多个周边互连线的单个片段利用双向缓冲器来缓冲周边互连线。外围互连的均匀缓冲段被设置为使得对于n行的互连，外围互连的每一行至少每n个段被缓冲一次。在操作中，位于远离IC外围的CLB可以通过局部互连线将多个外围互连线上的信号输出到另一个局部互连上，并将其输出到IOB中并在其外部引脚上。要输入信号，路径相反。引脚和CLB不需要相邻。

9. 发明授权

US5594367A Output multiplexer within input/output circuit for time multiplexing and high speed logic 失效
标题翻译：用于时间复用和高速逻辑的输入/输出电路中的输出多路复用器
公开(公告)号：US5594367A
公开(公告)日：1997-01-14
申请号：US543521
申请日：1995-10-16
申请人： Stephen M. Trimberger , Khue Duong , Robert O. Conn, Jr.
发明人： Stephen M. Trimberger , Khue Duong , Robert O. Conn, Jr.
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/17744 , H03K19/1737 , H03K19/17704
摘要： A input/output circuit (IOB) within an integrated circuit (IC) device, the output signal driving circuitry of the input/output device contains a dedicated multiplexer on the output path wherein a first and second output signal can be time multiplexed on a single output pad. The multiplexer can also be configured to perform as a high speed gate to realize AND, OR, XOR, and XNOR functions. Within an input/output circuit of a programmable integrated circuit, the system provides a dedicated multiplexer that can select between one of two output signals for sending over the single output pad of the IC device. In lieu of using a programmable memory cell as the select control for the dedicated multiplexer, the system allows a number of lines, including an output clock signal, to be the select control. By using the output clock as the select control, the data signals can be effectively time multiplexed over a single output pad and referenced by the output clock. This effectively doubles the number of output signals the IC device can provide with a given number of pads. The dedicated multiplexer when configured as a high speed gate is useful for generating very high speed system level reset or enable signals or any logic function.
摘要翻译：在集成电路（IC）装置内的输入/输出电路（IOB）中，输入/输出装置的输出信号驱动电路在输出路径上包含专用多路复用器，其中第一和第二输出信号可以在单个输出板。复用器也可以被配置为执行高速门以实现AND，OR，XOR和XNOR功能。在可编程集成电路的输入/输出电路内，该系统提供专用多路复用器，其可以在两个输出信号中的一个之间进行选择，以便通过IC器件的单个输出焊盘进行发送。代替使用可编程存储器单元作为专用多路复用器的选择控制，系统允许包括输出时钟信号在内的多条线路成为选择控制。通过使用输出时钟作为选择控制，数据信号可以在单个输出焊盘上有效地进行时分复用，并由输出时钟参考。这有效地将IC器件可以提供的输出信号的数量加倍到给定数量的焊盘。配置为高速门时的专用多路复用器可用于产生非常高速的系统级复位或使能信号或任何逻辑功能。

10. 发明授权

US5583452A Tri-directional buffer 失效
标题翻译：三向缓冲区
公开(公告)号：US5583452A
公开(公告)日：1996-12-10
申请号：US548926
申请日：1995-10-26
申请人： Khue Duong , Stephen M. Trimberger
发明人： Khue Duong , Stephen M. Trimberger
IPC分类号： H03K19/177 , H03K19/0944
CPC分类号： H03K19/17792 , H03K19/17704 , H03K19/17788
摘要： A configurable multi-directional buffer circuit for a programmable integrated circuit. The novel buffer circuit is a configurable multi-directional buffer circuit having one pair of inverters and having a first input/output line and a second input/output line and a third input line multiplexed with the first input/output line. The novel buffer circuit is configurable to allow a signal from the first input/output line to be driven over the second input/output line or configurable to allow a signal from the second input/output line to be driven over the first input/output line. The novel buffer circuit also allows a signal over the third input line to be driven over the second input/output line. In either case, only a single pair of inverter circuits are used. In an alternate embodiment, the novel buffer allows signal over a fourth input line to be driven over the first input/output line. The novel buffer is configurable to realize any of the above configurations using programmable memory cells and therefore is well suited for application within a programmable integrated circuit. Since the novel buffer utilizes only a single pair of inverters to provide the buffering, in any configuration, it does not contain unused driver circuitry when configured. Therefore, the novel buffer advantageously consumes a relatively small amount of substrate area.
摘要翻译：一种用于可编程集成电路的可配置多方向缓冲电路。新颖的缓冲电路是具有一对反相器并具有与第一输入/输出线复用的第一输入/输出线和第二输入/输出线和第三输入线的可配置多方向缓冲电路。新型缓冲电路可配置为允许来自第一输入/输出线的信号通过第二输入/输出线驱动，或者可配置为允许来自第二输入/输出线的信号通过第一输入/输出线。新型缓冲电路还允许在第三输入线上的信号通过第二输入/输出线驱动。在任一种情况下，仅使用一对逆变器电路。在替代实施例中，新型缓冲器允许在第四输入线上的信号通过第一输入/输出线驱动。新型缓冲器可配置为使用可编程存储器单元实现上述任何一种配置，因此非常适用于可编程集成电路中的应用。由于新型缓冲器仅使用一对反相器来提供缓冲，在任何配置中，配置时不包含未使用的驱动器电路。因此，新型缓冲液有利地消耗相对少量的衬底面积。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式