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    • 7. 发明授权
    • Status bit controlled HDLC accelerator
    • 状态位控制HDLC加速器
    • US5638370A
    • 1997-06-10
    • US365356
    • 1994-12-28
    • Mark SeconiPaul McAllisterGlenn Lewis
    • Mark SeconiPaul McAllisterGlenn Lewis
    • H04L1/00H04L29/06H04L29/08H04T3/06
    • H04L1/0057H04L29/06H04L69/324
    • A status bit controlled HDLC accelerator comprises a fully programmable CRC generation circuit, a partial data packet formatting/unformatting capability and a dual-mode register set. The HDLC accelerator includes a set of registers that can be written to and read from directly via a bus interface circuit. Moreover, these registers may be written to and read from at any time so that the state of the HDLC accelerator during a formatting or unformatting operation may be stored in mid-operation. The HDLC accelerator further includes a CRC generation circuit that can perform various checkword generation functions in response to a programmable CRC generator polynomial. In addition, programmable counters within the HDLC accelerator allow partial data packets to be processed which thereby enables formatting and unformatting data packets of all valid bit enumerations.
    • 状态位控制的HDLC加速器包括完全可编程的CRC生成电路,部分数据分组格式化/非格式化能力以及双模式寄存器组。 HDLC加速器包括一组可以通过总线接口电路直接写入和读取的寄存器。 此外,这些寄存器可以在任何时刻被写入和读取,使得格式化或非格式化操作期间的HDLC加速器的状态可以被存储在中间操作中。 HDLC加速器还包括CRC生成电路,其可以响应于可编程CRC生成多项式来执行各种复制词生成功能。 此外,HDLC加速器内的可编程计数器允许处理部分数据包,从而可以格式化和取消格式化所有有效位枚举的数据包。