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    • 3. 发明授权
    • Mitigating noise created by spread spectrum clocks
    • 降低扩频时钟产生的噪音
    • US08054921B2
    • 2011-11-08
    • US11963021
    • 2007-12-21
    • Marc JalfonRafi Ravid
    • Marc JalfonRafi Ravid
    • H03D1/04
    • H04B1/7097H04B15/04H04B2201/70715
    • A platform to mitigate noise caused by spread spectrum clock signals. The platform may comprise a noise mitigation block, which may include a first set of analog-to-digital converters, a second analog-to-digital, and a noise canceller. The first set of analog-to-digital converters may generate clock samples by digitizing the plurality of spread spectrum clock signals, which are provided as inputs to the noise mitigation block. The second analog-to-digital converter may generate data samples by digitizing the data signal. The noise canceller coupled to the first set of analog-to-digital converters and the second analog-to-digital converter may identify an interference portion in the data signal using the clock samples and the data samples and remove the interference portion from the data signal.
    • 一个减轻由扩频时钟信号引起的噪声的平台。 平台可以包括噪声抑制块,其可以包括第一组模数转换器,第二模数转换器和噪声消除器。 第一组模拟 - 数字转换器可以通过数字化多个扩频时钟信号来产生时钟采样,这些时钟信号作为输入提供给噪声抑制块。 第二模数转换器可以通过数字化数据信号来生成数据采样。 耦合到第一组模数转换器和第二模数转换器的噪声消除器可以使用时钟采样和数据样本来识别数据信号中的干扰部分,并从数据信号中去除干扰部分 。
    • 10. 发明授权
    • Memory address translations for programs code execution/relocation
    • 程序代码执行/重定位的内存地址转换
    • US5909702A
    • 1999-06-01
    • US724610
    • 1996-09-30
    • Marc JalfonDavid RegenoldFranco RicciRamprasad Satagopan
    • Marc JalfonDavid RegenoldFranco RicciRamprasad Satagopan
    • G06F12/02G06F13/00
    • G06F12/0284
    • A multiprocessor data processing system includes a private data bus and a private program bus coupled to each of the processors. Coupled between the private data buses is a plurality of memory banks, each of which can be dynamically switched between the processors to move blocks of data without physically transferring the data from one bank to another. Likewise, a plurality of memory banks is coupled between the program buses. These memory banks are loaded with pages of program instructions from external memory over a shared bus. Any one of the pages can be coupled to either of the processors on its respective private program bus. When the pages are coupled to the shared bus, they appear as a contiguous address space. When a page is coupled to one of the private program buses, the addressing mode is changed so that the page is mapped to a common address space. This permits the program code to be loaded into any available page, and the processors can execute the code regardless of where it has been loaded, thereby permitting easy relocatability.
    • 多处理器数据处理系统包括专用数据总线和耦合到每个处理器的专用程序总线。 在专用数据总线之间耦合的是多个存储器组,每个存储体可以在处理器之间动态地切换以移动数据块,而无需将数据从一个存储体物理传送到另一个存储体。 同样地,多个存储体耦合在程序总线之间。 这些存储体通过共享总线从外部存储器加载程序指令页面。 任何一个页面都可以耦合到其各自的专用程序总线上的任一个处理器。 当页面耦合到共享总线时,它们显示为连续的地址空间。 当页面耦合到专用程序总线之一时,改变寻址模式,使得页面被映射到公共地址空间。 这允许将程序代码加载到任何可用的页面中,并且处理器可以执行代码,而不管它在哪里被加载,从而允许容易地重新定位。