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1. 发明授权

US07683644B2 Extrusion failure monitor structures 失效
标题翻译：挤出破坏监测结构
公开(公告)号：US07683644B2
公开(公告)日：2010-03-23
申请号：US11834054
申请日：2007-08-06
申请人： Ronald G. Filippi , James R. Lloyd, Jr.
发明人： Ronald G. Filippi , James R. Lloyd, Jr.
IPC分类号： G01R27/26 , G01R27/08 , G01N27/60
CPC分类号： G01R31/2858 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A structure and method for monitoring extrusion failures. The structure includes: a test wire having first and second ends; first and second vias contacting first and second ends of the test wire; a first monitor structure electrically isolated from the test wire and surrounding a periphery of the test wire; and a second monitor structure over the test wire, the second monitor structure electrically isolated from the test wire, the second monitor structure extending over at least the first end of the test wire.
摘要翻译：一种用于监测挤压失效的结构和方法。该结构包括：具有第一端和第二端的测试线; 第一和第二通孔接触测试丝的第一和第二端; 与测试线电隔离并围绕测试线周边的第一监视器结构; 以及在所述测试线上的第二监视器结构，所述第二监视器结构与所述测试线电隔离，所述第二监视器结构至少延伸到所述测试线的第一端。

2. 发明申请

US20090039896A1 EXTRUSION FAILURE MONITOR STRUCTURES 失效
标题翻译：挤出失效监测结构
公开(公告)号：US20090039896A1
公开(公告)日：2009-02-12
申请号：US11834054
申请日：2007-08-06
申请人： Ronald G. Filippi , James R. Lloyd, JR.
发明人： Ronald G. Filippi , James R. Lloyd, JR.
IPC分类号： G01R31/02
CPC分类号： G01R31/2858 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A structure and method for monitoring extrusion failures. The structure includes: a test wire having first and second ends; first and second vias contacting first and second ends of the test wire; a first monitor structure electrically isolated from the test wire and surrounding a periphery of the test wire; and a second monitor structure over the test wire, the second monitor structure electrically isolated from the test wire, the second monitor structure extending over at least the first end of the test wire.
摘要翻译：一种用于监测挤压失效的结构和方法。该结构包括：具有第一端和第二端的测试线; 第一和第二通孔接触测试丝的第一和第二端; 与测试线电隔离并围绕测试线周边的第一监视器结构; 以及在所述测试线上的第二监视器结构，所述第二监视器结构与所述测试线电隔离，所述第二监视器结构至少延伸到所述测试线的第一端。

3. 发明授权

US09059169B2 E-fuse structures and methods of manufacture 有权
标题翻译：电熔丝结构和制造方法
公开(公告)号：US09059169B2
公开(公告)日：2015-06-16
申请号：US13165087
申请日：2011-06-21
申请人： Griselda Bonilla , Kaushik Chanda , Samuel S. Choi , Ronald G. Filippi , Stephan Grunow , Naftali E. Lustig , Andrew H. Simon
发明人： Griselda Bonilla , Kaushik Chanda , Samuel S. Choi , Ronald G. Filippi , Stephan Grunow , Naftali E. Lustig , Andrew H. Simon
IPC分类号： H01L21/26 , H01L23/525 , H01L23/522 , H01L21/768
CPC分类号： H01L23/5256 , H01L21/768 , H01L21/76808 , H01L21/76811 , H01L21/76813 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： E-fuse structures in back end of the line (BEOL) interconnects and methods of manufacture are provided. The method includes forming an interconnect via in a substrate in alignment with a first underlying metal wire and forming an e-fuse via in the substrate, exposing a second underlying metal wire. The method further includes forming a defect with the second underlying metal wire and filling the interconnect via with metal and in contact with the first underlying metal wire thereby forming an interconnect structure. The method further includes filling the e-fuse via with the metal and in contact with the defect and the second underlying metal wire thereby forming an e-fuse structure.
摘要翻译：提供线后端的电熔丝结构（BEOL）互连和制造方法。该方法包括在衬底中与第一底层金属线对齐形成互连通孔，并在衬底中形成电熔丝通孔，露出第二下面的金属线。该方法还包括用第二底层金属线形成缺陷并用金属填充互连通孔并与第一底层金属线接触，从而形成互连结构。该方法还包括用金属填充e熔丝通孔并与缺陷和第二下面的金属线接触，从而形成电熔丝结构。

4. 发明授权

US08446014B2 Integrated circuit interconnect structure 失效
标题翻译：集成电路互连结构
公开(公告)号：US08446014B2
公开(公告)日：2013-05-21
申请号：US13531008
申请日：2012-06-22
申请人： Hanyi Ding , Ronald G. Filippi , Jong-Ru Guo , Ping-Chuan Wang
发明人： Hanyi Ding , Ronald G. Filippi , Jong-Ru Guo , Ping-Chuan Wang
IPC分类号： H01L23/48
CPC分类号： H01L23/528 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a dielectric and coupled to the first via at an opposite end thereof. The buffer metal segment includes a plurality of electrically insulating inter-dielectric (ILD) pads forming an ILD cheesing pattern thereon, to direct current. The IC interconnect structure further includes a second via positioned in a dielectric formed over the buffer metal segment and coupled to the buffer metal segment at one end and a metal power line formed in a dielectric and coupled to the second via at an opposite end thereof. The use of the ILD pads on the buffer metal segment enables a more even distribution of current along the metal power line.
摘要翻译：一种集成电路（IC）互连结构，其包括位于电介质中并且在一端耦合到高电流器件的第一通孔和位于电介质中的缓冲金属段，并在其相对端耦合到第一通孔。缓冲金属段包括在其上形成ILD干酪糖化图案的多个电绝缘介电层（ILD）焊盘以引导电流。 IC互连结构还包括位于介质上的第二通孔，该电介质形成在缓冲金属段上并且在一端耦合到缓冲金属段，并且金属电源线形成在电介质中，并在其相对端耦合到第二通孔。缓冲金属片段上的ILD焊盘的使用使得能够沿着金属电源线更均匀地分布电流。

5. 发明申请

US20110108990A1 Capping of Copper Interconnect Lines in Integrated Circuit Devices 有权
标题翻译：集成电路器件中铜互连线的封盖
公开(公告)号：US20110108990A1
公开(公告)日：2011-05-12
申请号：US12613551
申请日：2009-11-06
申请人： Griselda Bonilla , Kaushik Chanda , Ronald G. Filippi , Stephan Grunow , David L. Rath , Sujatha Sankaran , Andrew H. Simon , Theodorus E. Standaert , Chih-Chao Yang
发明人： Griselda Bonilla , Kaushik Chanda , Ronald G. Filippi , Stephan Grunow , David L. Rath , Sujatha Sankaran , Andrew H. Simon , Theodorus E. Standaert , Chih-Chao Yang
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L23/53238 , H01L21/76834 , H01L21/76849 , H01L21/76865 , H01L2924/0002 , H01L2924/00
摘要： A method for capping lines includes forming a metal film layer on a copper line by a selective deposition process, the copper line disposed in a dielectric substrate, wherein the depositing also results in the deposition of stray metal material on the surface of the dielectric substrate, and etching with an isotropic etching process to remove a portion of the metal film layer and the stray metal material on the surface of the dielectric substrate, wherein the metal film layer is deposited at an initial thickness sufficient to leave a metal film layer cap remaining on the copper line following the removal of the stray metal material.
摘要翻译：一种封盖线的方法包括通过选择性沉积工艺在铜线上形成金属膜层，铜线设置在电介质基底中，其中沉积还导致杂散金属材料沉积在介质基片的表面上，并用各向同性蚀刻工艺进行蚀刻以除去电介质基底表面上的金属膜层和杂散金属材料的一部分，其中金属膜层以足以使金属膜层盖保持在其上的初始厚度沉积铜线除去杂散金属材料。

6. 发明授权

US07671362B2 Test structure for determining optimal seed and liner layer thicknesses for dual damascene processing 失效
标题翻译：用于确定双镶嵌加工的最佳种子和衬层层厚度的测试结构
公开(公告)号：US07671362B2
公开(公告)日：2010-03-02
申请号：US11953568
申请日：2007-12-10
申请人： Tibor Bolom , Kaushik Chanda , Ronald G. Filippi , Stephan Grunow , Paul S. McLaughlin , Sujatha Sankaran , Andrew H. Simon , Theodorus E. Standaert , James Werking
发明人： Tibor Bolom , Kaushik Chanda , Ronald G. Filippi , Stephan Grunow , Paul S. McLaughlin , Sujatha Sankaran , Andrew H. Simon , Theodorus E. Standaert , James Werking
IPC分类号： H01L23/58
CPC分类号： H01L22/12 , H01L22/34
摘要： A test structure for integrated circuit (IC) device fabrication includes a plurality of test structure chains formed at various regions of an IC wafer, each of the plurality of test structure chains including one or more vias; each of the one or more vias in contact with a conductive line disposed thereabove, the conductive line being configured such that at least one dimension thereof varies from chain to chain so as to produce variations in seed layer and liner layer thickness from chain to chain for the same deposition process conditions.
摘要翻译：集成电路（IC）器件制造的测试结构包括形成在IC晶片的各个区域的多个测试结构链，所述多个测试结构链中的每一个包括一个或多个通孔; 所述一个或多个通孔中的每一个与设置在其上的导电线接触，所述导电线被配置为使得其至少一个尺寸从链到链变化，从而在种子层和衬层层厚度之间产生从链到链的变化，相同的沉积工艺条件。

7. 发明申请

US20090294901A1 STRUCTURE AND METHOD OF FORMING ELECTRICALLY BLOWN METAL FUSES FOR INTEGRATED CIRCUITS 有权
标题翻译：集成电路形成电动金属熔断器的结构与方法
公开(公告)号：US20090294901A1
公开(公告)日：2009-12-03
申请号：US12132337
申请日：2008-06-03
申请人： Griselda Bonilla , Kaushik Chanda , Ronald G. Filippi , Jeffrey P. Gambino , Stephan Grunow , Chao-Kun Hu , Sujatha Sankaran , Andrew H. Simon , Theodorus E. Standaert
发明人： Griselda Bonilla , Kaushik Chanda , Ronald G. Filippi , Jeffrey P. Gambino , Stephan Grunow , Chao-Kun Hu , Sujatha Sankaran , Andrew H. Simon , Theodorus E. Standaert
IPC分类号： H01L21/768 , H01L23/58
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A fuse structure for an integrated circuit device includes an elongated metal interconnect layer defined within an insulating layer; a metal cap layer formed on only a portion of a top surface of the metal interconnect layer; and a dielectric cap layer formed on both the metal cap layer and the remaining portions of the metal interconnect layer not having the metal cap layer formed thereon; wherein the remaining portions of the metal interconnect layer not having the metal cap layer formed thereon are susceptible to an electromigration failure mechanism so as to facilitate programming of the fuse structure by application of electric current through the elongated metal interconnect layer.
摘要翻译：用于集成电路器件的熔丝结构包括限定在绝缘层内的细长金属互连层; 仅在所述金属互连层的顶表面的一部分上形成的金属盖层; 以及形成在所述金属盖层和所述金属互连层的其余部分上的电介质盖层，其不形成有所述金属盖层; 其中不具有形成在其上的金属覆盖层的金属互连层的其余部分容易受到电迁移故障机制的影响，以便通过施加通过细长金属互连层的电流来编程熔丝结构。

8. 发明申请

US20080231312A1 Structure for modeling stress-induced degradation of conductive interconnects 失效
标题翻译：用于建模导电互连的应力诱导退化的结构
公开(公告)号：US20080231312A1
公开(公告)日：2008-09-25
申请号：US12154304
申请日：2008-05-22
申请人： Kaushik Chanda , Birendra Agarwala , Lawrence A. Clevenger , Andrew P. Cowley , Ronald G. Filippi , Jason P. Gill , Tom C. Lee , Baozhen Li , Paul S. McLaughlin , Du B. Nguyen , Hazara S. Rathore , Timothy D. Sullivan , Chih-Chao Yang
发明人： Kaushik Chanda , Birendra Agarwala , Lawrence A. Clevenger , Andrew P. Cowley , Ronald G. Filippi , Jason P. Gill , Tom C. Lee , Baozhen Li , Paul S. McLaughlin , Du B. Nguyen , Hazara S. Rathore , Timothy D. Sullivan , Chih-Chao Yang
IPC分类号： G01R31/26
CPC分类号： G01R31/2858 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A structure representative of a conductive interconnect of a microelectronic element is provided, which may include a conductive metallic plate having an upper surface, a lower surface, and a plurality of peripheral edges extending between the upper and lower surfaces, the upper surface defining a horizontally extending plane. The structure may also include a lower via having a top end in conductive communication with the metallic plate and a bottom end vertically displaced from the top end. A lower conductive or semiconductive element can be in contact with the bottom end of the lower via. An upper metallic via can lie in at least substantial vertical alignment with the lower conductive via, the upper metallic via having a bottom end in conductive communication with the metallic plate and a top end vertically displaced from the bottom end. The upper metallic via may have a width at least about ten times than the length of the metallic plate and about ten times smaller than the width of the metallic plate. The structure may further include an upper metallic line element in contact with the top end of the upper metallic via.
摘要翻译：提供了表示微电子元件的导电互连的结构，其可以包括具有上表面，下表面和在上表面和下表面之间延伸的多个周边边缘的导电金属板，上表面限定水平延伸平面该结构还可以包括具有与金属板导电连通的顶端和从顶端垂直移位的底端的下通孔。下导电或半导体元件可以与下通孔的底端接触。上金属通孔可以与下导电通孔至少基本垂直对准，上金属通孔具有与金属板导电连通的底端和从底端垂直移位的顶端。上部金属通孔的宽度可以比金属板的长度至少大约十倍，并且比金属板的宽度小约十倍。该结构还可以包括与上金属通孔的顶端接触的上金属线元件。

9. 发明授权

US06870263B1 Device interconnection 失效
标题翻译：设备互连
公开(公告)号：US06870263B1
公开(公告)日：2005-03-22
申请号：US09052688
申请日：1998-03-31
申请人： Lawrence A. Clevenger , Ronald G. Filippi , Mark Hoinkis , Jeffery L. Hurd , Roy C. Iggulden , Herbert Palm , Hans W. Poetzlberger , Kenneth P. Rodbell , Florian Schnabel , Stefan Weber , Ebrahim A. Mehter
发明人： Lawrence A. Clevenger , Ronald G. Filippi , Mark Hoinkis , Jeffery L. Hurd , Roy C. Iggulden , Herbert Palm , Hans W. Poetzlberger , Kenneth P. Rodbell , Florian Schnabel , Stefan Weber , Ebrahim A. Mehter
IPC分类号： H01L21/28 , H01L21/768 , H01L23/485 , H01L23/532 , H01L23/48
CPC分类号： H01L21/76843 , H01L21/76807 , H01L21/76849 , H01L21/76876 , H01L23/485 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： A conductor for interconnecting integrated circuit components having improved reliability. The conductor includes a liner surrounding at least three surfaces of the conductor, producing a low textured conductor. It has been found that low textured conductor results in improved electromigration lifetime.
摘要翻译：用于互连具有改进的可靠性的集成电路部件的导体。导体包括围绕导体的至少三个表面的衬垫，产生低纹理导体。已经发现，低纹理导体导致改善的电迁移寿命。

10. 发明授权

US06518670B1 Electrically porous on-chip decoupling/shielding layer 有权
标题翻译：多孔片上去耦/屏蔽层
公开(公告)号：US06518670B1
公开(公告)日：2003-02-11
申请号：US10091643
申请日：2002-03-06
申请人： Jack A. Mandelman , Ronald G. Filippi , Jeffrey P. Gambino , Richard A. Wachnik
发明人： Jack A. Mandelman , Ronald G. Filippi , Jeffrey P. Gambino , Richard A. Wachnik
IPC分类号： H01L2940
CPC分类号： H01L21/76897 , H01L23/5222 , H01L23/5228 , H01L23/5286 , H01L27/0802 , H01L27/0805 , H01L28/82 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes interconnected conductor lines comprising a lower Interlayer Dielectric (ILD) layer having a top surface formed on a substrate. Several lower conductor lines are formed on the top surface of the lower ILD layer surrounded by an insulator formed on the lower ILD layer. Each of a set of resistive studs has sidewalls, a lower end and an upper end and it is joined to the top of the lower conductor line at the lower end. There are several intermediate conductor lines formed between the resistive studs separated from adjacent studs by a liner layer and a capacitor dielectric layer. Upper conductor lines are formed on a upper level. Each has a bottom surface in contact with a corresponding one of the resistive studs. A central ILD layer is formed below the intermediate conductor to electrically insulate and separate the intermediate conductor lines from the lower conductor lines. A upper ILD layer overlies the intermediate conductor for electrically insulating and separating the intermediate conductor lines from the upper conductor lines. The resistive stud, the capacitor dielectric, and the intermediate conductor across the capacitor dielectric layer and the liner layer form an electrically porous, distributed resistive-capacitive low-pass decoupling network.
摘要翻译：半导体器件包括互连的导体线，其包括在衬底上形成有顶表面的下层间介电层（ILD）层。在由形成在下ILD层上的绝缘体围绕的下ILD层的顶表面上形成几个下导体线。一组电阻螺柱中的每一个具有侧壁，下端和上端，并且在下端处连接到下导体线的顶部。在通过衬垫层和电容器电介质层从相邻螺柱分离的电阻螺柱之间形成几个中间导体线。上导体线形成在上层。每个具有与相应的一个电阻螺柱接触的底表面。在中间导体下方形成中心ILD层，以将中间导线与下导体线电绝缘和分离。上部ILD层覆盖中间导体，用于将中间导体线与上部导体线电绝缘和分离。电阻螺柱，电容器电介质和跨过电容器电介质层和衬层的中间导体形成电多孔分布式电阻电容低通去耦网络。

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