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1. 发明授权

US08652583B2 Method for producing a three-dimensionally controlled surface coating in a cavity 有权
标题翻译：在空腔中制造三维控制表面涂层的方法
公开(公告)号：US08652583B2
公开(公告)日：2014-02-18
申请号：US12965063
申请日：2010-12-10
申请人： Romain Wacquez , Christophe Constancias , Philippe Coronel
发明人： Romain Wacquez , Christophe Constancias , Philippe Coronel
IPC分类号： B05D3/00
CPC分类号： B81C1/00047 , B81B2203/0315 , B81C1/00206
摘要： The cavity has first and second main walls covered by a photoresist. The photoresist is subjected to electronic or electromagnetic radiation of wavelength comprised between 12.5 nm and 15 nm. A first thickness of the photoresist is exposed to form a first area of sacrificial material and a second area of different nature defining the surface coating. The sacrificial material is removed, the surface coating is formed and has a surface against one of the main walls and a free opposite surface. The lateral dimensions of the surface coating are defined in the cavity by the radiation through the first main wall.
摘要翻译：空腔具有由光致抗蚀剂覆盖的第一和第二主壁。光致抗蚀剂经受在12.5nm和15nm之间的波长的电子或电磁辐射。暴露光致抗蚀剂的第一厚度以形成牺牲材料的第一区域和限定表面涂层的不同性质的第二区域。去除牺牲材料，形成表面涂层并且具有抵抗主壁之一和自由相对表面的表面。表面涂层的横向尺寸通过穿过第一主壁的辐射在空腔中限定。

2. 发明授权

US07420253B2 Three-gate transistor structure 有权
标题翻译：三栅晶体管结构
公开(公告)号：US07420253B2
公开(公告)日：2008-09-02
申请号：US11434561
申请日：2006-05-15
申请人： Philippe Coronel , Romain Wacquez
发明人： Philippe Coronel , Romain Wacquez
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L29/1037 , H01L29/42384 , H01L29/66484 , H01L29/66795 , H01L29/7831
摘要： A transistor structure comprises a semiconductor element extending between a source zone and a drain zone, as well as three portions of gates disposed on different sides of the semiconductor element. Such a structure is especially compact and may be used as two or three transistors having independent respective functions. In particular, the structure may be used as a combination of a transistor with a logic or analog function, with one or two random access memory cells.
摘要翻译：晶体管结构包括在源极区和漏极区之间延伸的半导体元件，以及设置在半导体元件的不同侧上的三个栅极部分。这种结构特别紧凑，并且可以用作具有独立相应功能的两个或三个晶体管。特别地，该结构可以被用作具有逻辑或模拟功能的晶体管与一个或两个随机存取存储器单元的组合。

3. 发明申请

US20070018227A1 Three-gate transistor structure 有权
标题翻译：三栅晶体管结构
公开(公告)号：US20070018227A1
公开(公告)日：2007-01-25
申请号：US11434561
申请日：2006-05-15
申请人： Philippe Coronel , Romain Wacquez
发明人： Philippe Coronel , Romain Wacquez
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L29/1037 , H01L29/42384 , H01L29/66484 , H01L29/66795 , H01L29/7831
摘要： A transistor structure comprises a semiconductor element extending between a source zone and a drain zone, as well as three portions of gates disposed on different sides of the semiconductor element. Such a structure is especially compact and may be used as two or three transistors having independent respective functions. In particular, the structure may be used as a combination of a transistor with a logic or analog function, with one or two random access memory cells.
摘要翻译：晶体管结构包括在源极区和漏极区之间延伸的半导体元件，以及设置在半导体元件的不同侧上的三个栅极部分。这种结构特别紧凑，并且可以用作具有独立相应功能的两个或三个晶体管。特别地，该结构可以被用作具有逻辑或模拟功能的晶体管与一个或两个随机存取存储器单元的组合。

4. 发明授权

US08460978B2 Method for manufacturing a transistor with parallel semiconductor nanofingers 有权
标题翻译：制造具有并联半导体纳米装置的晶体管的方法
公开(公告)号：US08460978B2
公开(公告)日：2013-06-11
申请号：US12063288
申请日：2006-08-07
申请人： Philippe Coronel , Jessy Bustos , Romain Wacquez
发明人： Philippe Coronel , Jessy Bustos , Romain Wacquez
IPC分类号： H01L21/00 , H01L27/01
CPC分类号： H01L29/785 , H01L29/42392 , H01L29/66772
摘要： A method of producing a transistor having parallel semiconductor nanofingers. The method includes: forming a monocrystalline layer of a semiconductor material on a layer of a subjacent material which can be selectively etched in relation to the monocrystalline layer; etching parallel partitions in the monocrystalline layer and in the subjacent layer and continuing said etching operation in order to hollow out part of the subjacent layer of material; filling the gap between the partitions and the hollowed-out part with a first insulating material; defining a central part of the partitions and removing the first insulating material from around the central part of the monocrystalline layer, thereby forming a finger of semiconductor material; and filling and coating the central part with a conductor material.
摘要翻译：一种制造具有并联半导体纳米装置的晶体管的方法。该方法包括：在可以相对于单晶层选择性地蚀刻的下层材料层上形成半导体材料的单晶层; 蚀刻单晶层和下层中的平行隔板，并继续进行所述蚀刻操作，以便中断部分下层材料; 用第一绝缘材料填充隔板和中空部分之间的间隙; 限定隔板的中心部分，并且从单晶层的中心部分周围去除第一绝缘材料，从而形成半导体材料的手指; 并用导体材料填充和涂覆中心部分。

5. 发明授权

US07803668B2 Transistor and fabrication process 有权
标题翻译：晶体管和制造工艺
公开(公告)号：US07803668B2
公开(公告)日：2010-09-28
申请号：US11710599
申请日：2007-02-23
申请人： Romain Wacquez , Philippe Coronel , Jessy Bustos
发明人： Romain Wacquez , Philippe Coronel , Jessy Bustos
IPC分类号： H01L21/335
CPC分类号： H01L29/42392 , H01L21/28158 , H01L29/42384 , H01L29/66772 , H01L29/78645 , H01L29/78654
摘要： Process for fabricating a transistor, in which an electron-sensitive resist layer lying between at least two semiconductor fingers is formed and said resist lying between at least two wires is converted into a dielectric. For example, in one embodiment of the present disclosure an integrated circuit includes a transistor having an insulating substrate including, for example, based on silicon oxide. Transistor also includes a conducting gate region comprising, for example, TiN or polysilicon, formed on a localized zone of the upper surface of the substrate, and an isolating region, comprising, for example, silicon oxide and surrounding the conducting region. The conducting region is also bounded in the direction normal to the plane of the drawing.
摘要翻译：制造其中形成位于至少两个半导体指状物之间的电子敏感抗蚀剂层并且位于至少两条导线之间的所述抗蚀剂的晶体管的工艺被转换为电介质。例如，在本公开的一个实施例中，集成电路包括具有例如基于氧化硅的绝缘衬底的晶体管。晶体管还包括形成在衬底的上表面的局部区域上的例如TiN或多晶硅的导电栅极区域，以及包括例如氧化硅并且围绕导电区域的隔离区域。导电区域也沿垂直于图面平面的方向界定。

6. 发明申请

US20100184274A1 METHOD FOR MANUFACTURING A TRANSISTOR WITH PARALLEL SEMICONDUCTOR NANOFINGERS 有权
标题翻译：用平行半导体纳米ZnO制造晶体管的方法
公开(公告)号：US20100184274A1
公开(公告)日：2010-07-22
申请号：US12063288
申请日：2006-08-07
申请人： Philippe Coronel , Jessy Bustos , Romain Wacquez
发明人： Philippe Coronel , Jessy Bustos , Romain Wacquez
IPC分类号： H01L21/762
CPC分类号： H01L29/785 , H01L29/42392 , H01L29/66772
摘要： A method of producing a transistor having parallel semiconductor nanofingers. The method includes: forming a monocrystalline layer of a semiconductor material on a layer of a subjacent material which can be selectively etched in relation to the monocrystalline layer; etching parallel partitions in the monocrystalline layer and in the subjacent layer and continuing said etching operation in order to hollow out part of the subjacent layer of material; filling the gap between the partitions and the hollowed-out part with a first insulating material; defining a central part of the partitions and removing the first insulating material from around the central part of the monocrystalline layer, thereby forming a finger of semiconductor material; and filling and coating the central part with a conductor material.
摘要翻译：一种制造具有并联半导体纳米装置的晶体管的方法。该方法包括：在可以相对于单晶层选择性地蚀刻的下层材料层上形成半导体材料的单晶层; 蚀刻单晶层和下层中的平行隔板，并继续进行所述蚀刻操作，以便中断部分下层材料; 用第一绝缘材料填充隔板和中空部分之间的间隙; 限定隔板的中心部分，并且从单晶层的中心部分周围去除第一绝缘材料，从而形成半导体材料的手指; 并用导体材料填充和涂覆中心部分。

7. 发明授权

US08110460B2 Method for producing stacked and self-aligned components on a substrate 有权
标题翻译：在基板上制造层叠和自对准部件的方法
公开(公告)号：US08110460B2
公开(公告)日：2012-02-07
申请号：US12577379
申请日：2009-10-12
申请人： Romain Wacquez , Philippe Coronel , Vincent Destefanis , Jean-Michel Hartmann
发明人： Romain Wacquez , Philippe Coronel , Vincent Destefanis , Jean-Michel Hartmann
IPC分类号： H01L21/8238
CPC分类号： H01L21/84 , H01L21/76264 , H01L21/8221
摘要： A method for producing stacked and self-aligned components on a substrate, including: providing a substrate made of monocrystalline silicon having one face enabling production of components, forming a stack of layers on the face of the substrate, selective etching by a gaseous mixture comprising gaseous HCl conveyed by a carrier gas and at a temperature between 450° C. and 900° C., depositing resin, implementing lithography of the resin, replacing resin eliminated during the lithography with a material for confining remaining resin, and forming elements of the components.
摘要翻译：一种用于在衬底上制备堆叠和自对准部件的方法，包括：提供由单晶硅制成的衬底，其具有能够生产部件的一个面，在衬底的表面上形成一叠层，通过气体混合物进行选择性蚀刻，所述气体混合物包括通过载气输送的气态HCl，在450℃和900℃之间的温度下，沉积树脂，实现树脂的光刻，在光刻期间用用于限制剩余树脂的材料替代消除的树脂，并形成元素组件。

8. 发明授权

US07994008B2 Transistor device with two planar gates and fabrication process 有权
标题翻译：具有两个平面栅极和制造工艺的晶体管器件
公开(公告)号：US07994008B2
公开(公告)日：2011-08-09
申请号：US11698755
申请日：2007-01-26
申请人： Romain Wacquez , Philippe Coronel , Damien Lenoble , Robin Cerutti , Thomas Skotnicki
发明人： Romain Wacquez , Philippe Coronel , Damien Lenoble , Robin Cerutti , Thomas Skotnicki
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L27/1203 , H01L29/78648
摘要： A planar transistor device includes two independent gates (a first and second gates) along with a semiconductor channel lying between the gates. The semiconductor channel is formed of a first material. The channel includes opposed ends comprising dielectric zone with a channel region positioned between the gates. The dielectric zones comprises an oxide of the first material.
摘要翻译：平面晶体管器件包括两个独立的栅极（第一和第二栅极）以及位于栅极之间的半导体沟道。半导体通道由第一材料形成。通道包括相对的端部，其包括介电区域，沟道区域位于栅极之间。介电区包括第一材料的氧化物。

9. 发明申请

US20100099233A1 METHOD FOR PRODUCING STACKED AND SELF-ALIGNED COMPONENTS ON A SUBSTRATE 有权
标题翻译：在衬底上生产堆叠和自对准组件的方法
公开(公告)号：US20100099233A1
公开(公告)日：2010-04-22
申请号：US12577379
申请日：2009-10-12
申请人： Romain Wacquez , Philippe Coronel , Vincent Destefanis , Jean-Michel Hartmann
发明人： Romain Wacquez , Philippe Coronel , Vincent Destefanis , Jean-Michel Hartmann
IPC分类号： H01L21/762
CPC分类号： H01L21/84 , H01L21/76264 , H01L21/8221
摘要： The invention relates to a method for producing stacked and self-aligned components on a substrate, comprising the following steps: forming a stack of layers on one face of the substrate, the stack comprising a first sacrificial layer, a second sacrificial layer and a superficial layer, selective etching of a zone of the first sacrificial layer, the second sacrificial layer and the superficial layer forming a bridge above the etched zone of the first sacrificial layer, depositing resin in the etched zone of the first sacrificial layer and on the superficial layer, lithography of the resin to leave remaining at least one zone of resin in the etched zone of the first sacrificial layer, in alignment with at least one resin zone on the superficial layer, replacing the eliminated resin in the etched zone of the first sacrificial layer and on the superficial layer with a material for confining the remaining resin, eliminating the remaining resin zones in the etched zone of the first sacrificial layer and on the superficial layer to provide zones dedicated to the production of components, forming elements of components in the dedicated zones, selective etching of a zone of the second sacrificial layer, the superficial layer forming a bridge above the etched zone of the second sacrificial layer.
摘要翻译：本发明涉及一种用于在衬底上制备堆叠和自对准部件的方法，包括以下步骤：在衬底的一个面上形成一叠层，所述堆叠包括第一牺牲层，第二牺牲层和表面层，选择性蚀刻第一牺牲层的区域，第二牺牲层和表层在第一牺牲层的蚀刻区上形成桥，在第一牺牲层的蚀刻区和表层上沉积树脂在所述第一牺牲层的所述蚀刻区中保留至少一个树脂区域，以与所述表面层上的至少一个树脂区域对准，替换所述第一牺牲层的所述蚀刻区域中被去除的树脂，并且在表面层上具有用于限制剩余树脂的材料，消除了第一次牺牲的蚀刻区域中剩余的树脂区域提供专用于生产部件的区域，在专用区域中形成部件的元件，选择性蚀刻第二牺牲层的区域，在第二蚀刻区域的蚀刻区域之上形成桥接的表面层牺牲层。

10. 发明申请

US20070278575A1 Transistor and fabrication process 有权
标题翻译：晶体管和制造工艺
公开(公告)号：US20070278575A1
公开(公告)日：2007-12-06
申请号：US11710599
申请日：2007-02-23
申请人： Romain Wacquez , Philippe Coronel , Jessy Bustos
发明人： Romain Wacquez , Philippe Coronel , Jessy Bustos
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/42392 , H01L21/28158 , H01L29/42384 , H01L29/66772 , H01L29/78645 , H01L29/78654
摘要： Process for fabricating a transistor, in which an electron-sensitive resist layer lying between at least two semiconductor fingers is formed and said resist lying between at least two wires is converted into a dielectric. For example, in one embodiment of the present disclosure an integrated circuit includes a transistor having an insulating substrate including, for example, based on silicon oxide. Transistor also includes a conducting gate region comprising, for example, TiN or polysilicon, formed on a localized zone of the upper surface of the substrate, and an isolating region, comprising, for example, silicon oxide and surrounding the conducting region. The conducting region is also bounded in the direction normal to the plane of the drawing.
摘要翻译：制造其中形成位于至少两个半导体指状物之间的电子敏感抗蚀剂层并且位于至少两条导线之间的所述抗蚀剂的晶体管的工艺被转换为电介质。例如，在本公开的一个实施例中，集成电路包括具有例如基于氧化硅的绝缘衬底的晶体管。晶体管还包括形成在衬底的上表面的局部区域上的例如TiN或多晶硅的导电栅极区域，以及包括例如氧化硅并且围绕导电区域的隔离区域。导电区域也沿垂直于图面平面的方向界定。

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