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1. 发明授权

US07420253B2 Three-gate transistor structure 有权
标题翻译：三栅晶体管结构
公开(公告)号：US07420253B2
公开(公告)日：2008-09-02
申请号：US11434561
申请日：2006-05-15
申请人： Philippe Coronel , Romain Wacquez
发明人： Philippe Coronel , Romain Wacquez
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L29/1037 , H01L29/42384 , H01L29/66484 , H01L29/66795 , H01L29/7831
摘要： A transistor structure comprises a semiconductor element extending between a source zone and a drain zone, as well as three portions of gates disposed on different sides of the semiconductor element. Such a structure is especially compact and may be used as two or three transistors having independent respective functions. In particular, the structure may be used as a combination of a transistor with a logic or analog function, with one or two random access memory cells.
摘要翻译：晶体管结构包括在源极区和漏极区之间延伸的半导体元件，以及设置在半导体元件的不同侧上的三个栅极部分。这种结构特别紧凑，并且可以用作具有独立相应功能的两个或三个晶体管。特别地，该结构可以被用作具有逻辑或模拟功能的晶体管与一个或两个随机存取存储器单元的组合。

2. 发明申请

US20070018227A1 Three-gate transistor structure 有权
标题翻译：三栅晶体管结构
公开(公告)号：US20070018227A1
公开(公告)日：2007-01-25
申请号：US11434561
申请日：2006-05-15
申请人： Philippe Coronel , Romain Wacquez
发明人： Philippe Coronel , Romain Wacquez
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L29/1037 , H01L29/42384 , H01L29/66484 , H01L29/66795 , H01L29/7831
摘要： A transistor structure comprises a semiconductor element extending between a source zone and a drain zone, as well as three portions of gates disposed on different sides of the semiconductor element. Such a structure is especially compact and may be used as two or three transistors having independent respective functions. In particular, the structure may be used as a combination of a transistor with a logic or analog function, with one or two random access memory cells.
摘要翻译：晶体管结构包括在源极区和漏极区之间延伸的半导体元件，以及设置在半导体元件的不同侧上的三个栅极部分。这种结构特别紧凑，并且可以用作具有独立相应功能的两个或三个晶体管。特别地，该结构可以被用作具有逻辑或模拟功能的晶体管与一个或两个随机存取存储器单元的组合。

3. 发明授权

US09396984B2 Method of producing a microelectronic device in a monocrystalline semiconductor substrate with isolation trenches partially formed under an active region 有权
标题翻译：在单晶半导体衬底中制造微电子器件的方法，其中隔离沟部分形成在有源区下
公开(公告)号：US09396984B2
公开(公告)日：2016-07-19
申请号：US14425977
申请日：2012-05-09
申请人： Maud Vinet , Nicolas Loubet , Romain Wacquez
发明人： Maud Vinet , Nicolas Loubet , Romain Wacquez
IPC分类号： H01L21/00 , H01L21/762 , H01L21/311 , H01L29/04 , H01L29/06 , H01L21/8234 , H01L21/3065
CPC分类号： H01L21/76224 , H01L21/3065 , H01L21/31116 , H01L21/76232 , H01L21/76283 , H01L21/823481 , H01L29/04 , H01L29/045 , H01L29/0653 , H01L29/66772
摘要： A method of producing a microelectronic device in a substrate including a first semiconductor layer, a dielectric layer and a second monocrystalline semiconductor layer, the method including: etching a trench through the first semiconductor layer and the dielectric layer, and such that the trench delimits one active region of the microelectronic device; chemical vapor etching the second semiconductor layer, at a level of a bottom wall of the trench, according to at least two crystalline planes of the second semiconductor layer such that an etched part of the second semiconductor layer extends under a part of the active region; filling the trench and the etched part of the second semiconductor layer with a dielectric material.
摘要翻译：一种在包括第一半导体层，电介质层和第二单晶半导体层的衬底中制造微电子器件的方法，所述方法包括：通过所述第一半导体层和所述介电层蚀刻沟槽，并且使得所述沟槽限定一个微电子器件的有源区; 根据所述第二半导体层的至少两个晶面，使所述第二半导体层的蚀刻部分在所述有源区的一部分下方延伸，在所述沟槽的底壁的水平面刻蚀所述第二半导体层; 用介电材料填充沟槽和第二半导体层的蚀刻部分。

4. 发明授权

US08652583B2 Method for producing a three-dimensionally controlled surface coating in a cavity 有权
标题翻译：在空腔中制造三维控制表面涂层的方法
公开(公告)号：US08652583B2
公开(公告)日：2014-02-18
申请号：US12965063
申请日：2010-12-10
申请人： Romain Wacquez , Christophe Constancias , Philippe Coronel
发明人： Romain Wacquez , Christophe Constancias , Philippe Coronel
IPC分类号： B05D3/00
CPC分类号： B81C1/00047 , B81B2203/0315 , B81C1/00206
摘要： The cavity has first and second main walls covered by a photoresist. The photoresist is subjected to electronic or electromagnetic radiation of wavelength comprised between 12.5 nm and 15 nm. A first thickness of the photoresist is exposed to form a first area of sacrificial material and a second area of different nature defining the surface coating. The sacrificial material is removed, the surface coating is formed and has a surface against one of the main walls and a free opposite surface. The lateral dimensions of the surface coating are defined in the cavity by the radiation through the first main wall.
摘要翻译：空腔具有由光致抗蚀剂覆盖的第一和第二主壁。光致抗蚀剂经受在12.5nm和15nm之间的波长的电子或电磁辐射。暴露光致抗蚀剂的第一厚度以形成牺牲材料的第一区域和限定表面涂层的不同性质的第二区域。去除牺牲材料，形成表面涂层并且具有抵抗主壁之一和自由相对表面的表面。表面涂层的横向尺寸通过穿过第一主壁的辐射在空腔中限定。

5. 发明申请

US20110143050A1 METHOD FOR PRODUCING A THREE-DIMENSIONALLY CONTROLLED SURFACE COATING IN A CAVITY 有权
标题翻译：用于在空腔中生产三维控制表面涂层的方法
公开(公告)号：US20110143050A1
公开(公告)日：2011-06-16
申请号：US12965063
申请日：2010-12-10
申请人： Romain WACQUEZ , Christophe CONSTANCIAS , Philippe CORONEL
发明人： Romain WACQUEZ , Christophe CONSTANCIAS , Philippe CORONEL
IPC分类号： B05D5/00 , B05D3/06 , C23C16/56
CPC分类号： B81C1/00047 , B81B2203/0315 , B81C1/00206
摘要： The cavity has first and second main walls covered by a photoresist. The photoresist is subjected to electronic or electromagnetic radiation of wavelength comprised between 12.5 nm and 15 nm. A first thickness of the photoresist is exposed to form a first area of sacrificial material and a second area of different nature defining the surface coating. The sacrificial material is removed, the surface coating is formed and has a surface against one of the main walls and a free opposite surface. The lateral dimensions of the surface coating are defined in the cavity by the radiation through the first main wall.
摘要翻译：空腔具有由光致抗蚀剂覆盖的第一和第二主壁。光致抗蚀剂经受在12.5nm和15nm之间的波长的电子或电磁辐射。暴露光致抗蚀剂的第一厚度以形成牺牲材料的第一区域和限定表面涂层的不同性质的第二区域。去除牺牲材料，形成表面涂层并且具有抵抗主壁之一和自由相对表面的表面。表面涂层的横向尺寸通过穿过第一主壁的辐射在空腔中限定。

6. 发明申请

US20150294903A1 METHOD FOR FABRICATING MICROELECTRONIC DEVICES WITH ISOLATION TRENCHES PARTIALLY FORMED UNDER ACTIVE REGIONS 有权
标题翻译：用于在有源区域部分地形成隔离斜面的微电子器件制造方法
公开(公告)号：US20150294903A1
公开(公告)日：2015-10-15
申请号：US14425891
申请日：2012-09-05
申请人： Laurent Grenouillet , Yannick Le Tiec , Nicolas Loubet , Maud Vinet , Romain Wacquez
发明人： Laurent Grenouillet , Yannick Le Tiec , Nicolas Loubet , Maud Vinet , Romain Wacquez
IPC分类号： H01L21/762 , H01L21/306 , H01L21/265 , H01L21/84
CPC分类号： H01L21/76283 , H01L21/26506 , H01L21/26586 , H01L21/30604 , H01L21/3065 , H01L21/3086 , H01L21/76224 , H01L21/76232 , H01L21/84
摘要： A method of producing a microelectronic device in a substrate comprising a first semiconductor layer, a dielectric layer and a second semiconductor layer, comprising the following steps: etching a trench through the first semiconductor layer, the dielectric layer and a part of the thickness of the second semiconductor layer, thus defining, in the first semiconductor layer, one active region of the microelectronic device, ionic implantation in one or more side walls of the trench, at the level of the second semiconductor layer, modifying the crystallographic properties and/or the chemical properties of the implanted semiconductor, etching of the implanted semiconductor such that at least a part of the trench extends under a part of the active region, —filling of the trench with a dielectric material, forming an isolation trench surrounding the active region and comprising portions extending under a part of the active region.
摘要翻译：一种在包括第一半导体层，电介质层和第二半导体层的衬底中制造微电子器件的方法，包括以下步骤：通过所述第一半导体层，所述电介质层和所述第一半导体层的厚度的一部分蚀刻沟槽从而在所述第一半导体层中限定所述微电子器件的一个有源区域，在所述沟槽的一个或多个侧壁中的离子注入，在所述第二半导体层的水平处，修改所述晶体学性质和/或所述第二半导体层，注入半导体的化学性质，蚀刻注入的半导体，使得沟槽的至少一部分在有源区的一部分下方延伸，用电介质材料填充沟槽，形成围绕有源区的隔离沟槽，并且包括在有源区域的一部分下延伸的部分。

7. 发明授权

US08460978B2 Method for manufacturing a transistor with parallel semiconductor nanofingers 有权
标题翻译：制造具有并联半导体纳米装置的晶体管的方法
公开(公告)号：US08460978B2
公开(公告)日：2013-06-11
申请号：US12063288
申请日：2006-08-07
申请人： Philippe Coronel , Jessy Bustos , Romain Wacquez
发明人： Philippe Coronel , Jessy Bustos , Romain Wacquez
IPC分类号： H01L21/00 , H01L27/01
CPC分类号： H01L29/785 , H01L29/42392 , H01L29/66772
摘要： A method of producing a transistor having parallel semiconductor nanofingers. The method includes: forming a monocrystalline layer of a semiconductor material on a layer of a subjacent material which can be selectively etched in relation to the monocrystalline layer; etching parallel partitions in the monocrystalline layer and in the subjacent layer and continuing said etching operation in order to hollow out part of the subjacent layer of material; filling the gap between the partitions and the hollowed-out part with a first insulating material; defining a central part of the partitions and removing the first insulating material from around the central part of the monocrystalline layer, thereby forming a finger of semiconductor material; and filling and coating the central part with a conductor material.
摘要翻译：一种制造具有并联半导体纳米装置的晶体管的方法。该方法包括：在可以相对于单晶层选择性地蚀刻的下层材料层上形成半导体材料的单晶层; 蚀刻单晶层和下层中的平行隔板，并继续进行所述蚀刻操作，以便中断部分下层材料; 用第一绝缘材料填充隔板和中空部分之间的间隙; 限定隔板的中心部分，并且从单晶层的中心部分周围去除第一绝缘材料，从而形成半导体材料的手指; 并用导体材料填充和涂覆中心部分。

8. 发明授权

US07803668B2 Transistor and fabrication process 有权
标题翻译：晶体管和制造工艺
公开(公告)号：US07803668B2
公开(公告)日：2010-09-28
申请号：US11710599
申请日：2007-02-23
申请人： Romain Wacquez , Philippe Coronel , Jessy Bustos
发明人： Romain Wacquez , Philippe Coronel , Jessy Bustos
IPC分类号： H01L21/335
CPC分类号： H01L29/42392 , H01L21/28158 , H01L29/42384 , H01L29/66772 , H01L29/78645 , H01L29/78654
摘要： Process for fabricating a transistor, in which an electron-sensitive resist layer lying between at least two semiconductor fingers is formed and said resist lying between at least two wires is converted into a dielectric. For example, in one embodiment of the present disclosure an integrated circuit includes a transistor having an insulating substrate including, for example, based on silicon oxide. Transistor also includes a conducting gate region comprising, for example, TiN or polysilicon, formed on a localized zone of the upper surface of the substrate, and an isolating region, comprising, for example, silicon oxide and surrounding the conducting region. The conducting region is also bounded in the direction normal to the plane of the drawing.
摘要翻译：制造其中形成位于至少两个半导体指状物之间的电子敏感抗蚀剂层并且位于至少两条导线之间的所述抗蚀剂的晶体管的工艺被转换为电介质。例如，在本公开的一个实施例中，集成电路包括具有例如基于氧化硅的绝缘衬底的晶体管。晶体管还包括形成在衬底的上表面的局部区域上的例如TiN或多晶硅的导电栅极区域，以及包括例如氧化硅并且围绕导电区域的隔离区域。导电区域也沿垂直于图面平面的方向界定。

9. 发明申请

US20100184274A1 METHOD FOR MANUFACTURING A TRANSISTOR WITH PARALLEL SEMICONDUCTOR NANOFINGERS 有权
标题翻译：用平行半导体纳米ZnO制造晶体管的方法
公开(公告)号：US20100184274A1
公开(公告)日：2010-07-22
申请号：US12063288
申请日：2006-08-07
申请人： Philippe Coronel , Jessy Bustos , Romain Wacquez
发明人： Philippe Coronel , Jessy Bustos , Romain Wacquez
IPC分类号： H01L21/762
CPC分类号： H01L29/785 , H01L29/42392 , H01L29/66772
摘要： A method of producing a transistor having parallel semiconductor nanofingers. The method includes: forming a monocrystalline layer of a semiconductor material on a layer of a subjacent material which can be selectively etched in relation to the monocrystalline layer; etching parallel partitions in the monocrystalline layer and in the subjacent layer and continuing said etching operation in order to hollow out part of the subjacent layer of material; filling the gap between the partitions and the hollowed-out part with a first insulating material; defining a central part of the partitions and removing the first insulating material from around the central part of the monocrystalline layer, thereby forming a finger of semiconductor material; and filling and coating the central part with a conductor material.
摘要翻译：一种制造具有并联半导体纳米装置的晶体管的方法。该方法包括：在可以相对于单晶层选择性地蚀刻的下层材料层上形成半导体材料的单晶层; 蚀刻单晶层和下层中的平行隔板，并继续进行所述蚀刻操作，以便中断部分下层材料; 用第一绝缘材料填充隔板和中空部分之间的间隙; 限定隔板的中心部分，并且从单晶层的中心部分周围去除第一绝缘材料，从而形成半导体材料的手指; 并用导体材料填充和涂覆中心部分。

10. 发明授权

US09437474B2 Method for fabricating microelectronic devices with isolation trenches partially formed under active regions 有权
标题翻译：用于制造具有在有源区域部分形成的隔离沟槽的微电子器件的方法
公开(公告)号：US09437474B2
公开(公告)日：2016-09-06
申请号：US14425891
申请日：2012-09-05
申请人： Laurent Grenouillet , Yannick Le Tiec , Nicolas Loubet , Maud Vinet , Romain Wacquez
发明人： Laurent Grenouillet , Yannick Le Tiec , Nicolas Loubet , Maud Vinet , Romain Wacquez
IPC分类号： H01L21/76 , H01L21/762 , H01L21/84 , H01L21/3065 , H01L21/308 , H01L21/265 , H01L21/306
CPC分类号： H01L21/76283 , H01L21/26506 , H01L21/26586 , H01L21/30604 , H01L21/3065 , H01L21/3086 , H01L21/76224 , H01L21/76232 , H01L21/84
摘要： A method of producing a microelectronic device in a substrate comprising a first semiconductor layer, a dielectric layer and a second semiconductor layer, comprising the following steps: etching a trench through the first semiconductor layer, the dielectric layer and a part of the thickness of the second semiconductor layer, thus defining, in the first semiconductor layer, one active region of the microelectronic device, ionic implantation in one or more side walls of the trench, at the level of the second semiconductor layer, modifying the crystallographic properties and/or the chemical properties of the implanted semiconductor, etching of the implanted semiconductor such that at least a part of the trench extends under a part of the active region, —filling of the trench with a dielectric material, forming an isolation trench surrounding the active region and comprising portions extending under a part of the active region.
摘要翻译：一种在包括第一半导体层，电介质层和第二半导体层的衬底中制造微电子器件的方法，包括以下步骤：通过所述第一半导体层，所述电介质层和所述第一半导体层的厚度的一部分蚀刻沟槽从而在所述第一半导体层中限定所述微电子器件的一个有源区域，在所述沟槽的一个或多个侧壁中的离子注入，在所述第二半导体层的水平处，修改所述晶体学性质和/或所述第二半导体层，注入半导体的化学性质，蚀刻注入的半导体，使得沟槽的至少一部分在有源区的一部分下方延伸，用电介质材料填充沟槽，形成围绕有源区的隔离沟槽，并且包括在有源区域的一部分下延伸的部分。

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