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1. 发明申请

US20150115769A1 SYSTEM FOR CONVERSING THERMAL ENERGY INTO ELECTRICAL ENERGY 有权
标题翻译：将热能转化为电能的系统
公开(公告)号：US20150115769A1
公开(公告)日：2015-04-30
申请号：US14232092
申请日：2012-07-09
申请人： Guillaume Savelli , Philippe Coronel , Stephane Monfray , Thomas Skotnicki
发明人： Guillaume Savelli , Philippe Coronel , Stephane Monfray , Thomas Skotnicki
IPC分类号： F03G7/06 , H02N2/18
CPC分类号： F03G7/06 , F03G7/065 , H01L41/1136 , H02N2/18 , H02N2/188
摘要： An assembly converting thermal energy into electrical energy including: at least one temperature sensitive bimetallic strip arranged in a space delimited by a hot source and a cold source facing each other, the bimetallic strip extending along a longitudinal axis; at least one suspended element fixed in movement to the sensitive element and extending laterally from the sensitive element and including a free end; and at least one piezoelectric element suspended from a part fixed relative to the sensitive element and vibrated by the suspended element such that it is vibrated when the bimetallic strip changes configuration and the suspended element comes into contact with the piezoelectric element, the piezoelectric element being located outside the space defined between the bimetallic strip and the hot source and outside the space between the bimetallic strip and the cold source.
摘要翻译：一种将热能转换成电能的组件，包括：至少一个温度敏感的双金属条，布置在由热源和相互面对的冷源界定的空间中，双金属条沿着纵轴延伸; 固定在所述敏感元件上并且从所述敏感元件横向延伸并且包括自由端的至少一个悬挂元件; 以及至少一个压电元件，其从相对于所述敏感元件固定的部分悬挂并由所述悬挂元件振动，使得当所述双金属条改变构型并且所述悬挂元件与所述压电元件接触时，所述压电元件被振动，所述压电元件位于在双金属条和热源之间限定的空间之外以及双金属条和冷源之间的空间之外。

2. 发明申请

US20110230020A1 SCHOTTKY-BARRIER MOS TRANSISTOR ON A FULLY-DEPLETED SEMICONDUCTOR FILM AND PROCESS FOR FABRICATING SUCH A TRANSISTOR 审中-公开
标题翻译：全封闭半导体膜上的肖特基栅极MOS晶体管和用于制造这种晶体管的工艺
公开(公告)号：US20110230020A1
公开(公告)日：2011-09-22
申请号：US13150511
申请日：2011-06-01
申请人： Thomas SKOTNICKI , Stéphane MONFRAY
发明人： Thomas SKOTNICKI , Stéphane MONFRAY
IPC分类号： H01L21/336
CPC分类号： H01L29/66636 , H01L21/823418 , H01L29/47 , H01L29/495 , H01L29/66643 , H01L29/7839
摘要： This process for manufacturing a Schottky-barrier MOS transistor on a fully depleted semiconductor film may include depositing a first layer of a first sacrificial material on an active zone of the substrate, forming a silicon layer on top of the first layer of sacrificial material, forming a gate region on top of the silicon layer with interposition of a gate oxide layer, and selective etching of the sacrificial material so as to form a tunnel beneath the gate region. The tunnel is filled with a dielectric second sacrificial material. A controlled lateral etching of the second sacrificial material is performed so as to keep behind a zone of dielectric material beneath the gate region. Silicidation is performed at the location of the source region and drain region and at the location of the etched zone.
摘要翻译：用于在完全耗尽的半导体膜上制造肖特基势垒MOS晶体管的该工艺可以包括在衬底的有源区上沉积第一牺牲材料的第一层，在第一牺牲材料层的顶部上形成硅层，形成在硅层的顶部具有栅极氧化物层的栅极区域，以及选择性蚀刻牺牲材料，以便在栅极区域下方形成隧道。隧道填充有电介质第二牺牲材料。执行第二牺牲材料的受控横向蚀刻，以便保持在栅极区域下方的介电材料区域的后面。在源极区域和漏极区域以及蚀刻区域的位置进行硅化。

3. 发明申请

US20110095655A1 THERMOELECTRIC GENERATOR 有权
标题翻译：热电发生器
公开(公告)号：US20110095655A1
公开(公告)日：2011-04-28
申请号：US12911287
申请日：2010-10-25
申请人： Thomas Skotnicki
发明人： Thomas Skotnicki
IPC分类号： H02N2/18
CPC分类号： H02N2/18
摘要： A thermoelectric generator including, between first and second walls delimiting a tightly closed space, a layer of a piezoelectric material connected to output terminals; a plurality of openings crossing the piezoelectric layer and emerging into first and second cavities close to the first and second walls; and in the tight space, drops of a liquid, the first wall being capable of being in contact with a hot source having a temperature greater than the evaporation temperature of the liquid and the second wall being capable of being in contact with a cold source having a temperature smaller than the evaporation temperature of the liquid.
摘要翻译：一种热电发生器，包括限定紧密封闭空间的第一和第二壁之间，连接到输出端的压电材料层; 多个开口与所述压电层交叉并且出现在靠近所述第一和第二壁的第一和第二空腔中; 并且在紧密的空间中，液滴，第一壁能够与温度大于液体的蒸发温度的热源接触，第二壁能够与具有温度小于液体的蒸发温度。

4. 发明申请

US20110095646A1 DEVICE FOR CONVERTING THERMAL POWER INTO ELECTRICITY 有权
标题翻译：将电力转换为电力的装置
公开(公告)号：US20110095646A1
公开(公告)日：2011-04-28
申请号：US12911267
申请日：2010-10-25
申请人： Thomas Skotnicki
发明人： Thomas Skotnicki
IPC分类号： H02N10/00
CPC分类号： H02N2/18
摘要： A device for converting thermal power into electric power including a plurality of bimetallic strips disposed between a rigid support and a plate of a resilient plastic material; and on the side of the plate of a resilient plastic material opposite to the strips, a layer of a piezoelectric material connected to output terminals, wherein the rigid support is capable of being in contact with a hot source, and the plate of a resilient plastic material is capable of transmitting to the piezoelectric layer the mechanical stress due to the deformations of the bimetallic strips.
摘要翻译：一种用于将热功率转换成电力的装置，包括设置在刚性支撑件和弹性塑料材料板之间的多个双金属条; 并且在与所述条带相反的弹性塑料材料的所述板的一侧上，连接到输出端子的压电材料层，其中所述刚性支撑件能够与热源接触，并且所述弹性塑料板材料能够向压电层传递由于双金属条的变形引起的机械应力。

5. 发明授权

US07892927B2 Transistor with a channel comprising germanium 有权
标题翻译：具有包含锗的通道的晶体管
公开(公告)号：US07892927B2
公开(公告)日：2011-02-22
申请号：US11725160
申请日：2007-03-16
申请人： Stephane Monfray , Thomas Skotnicki , Didier Dutartre , Alexandre Talbot
发明人： Stephane Monfray , Thomas Skotnicki , Didier Dutartre , Alexandre Talbot
IPC分类号： H01L21/336
CPC分类号： H01L29/78684 , H01L29/66628 , H01L29/66772
摘要： A transistor including a germanium-rich channel. The germanium-rich channel is produced by oxidation of the silicon contained in the silicon-germanium intermediate layer starting from the lower surface of the said intermediate layer. The germanium atoms are therefore caused to migrate towards the upper surface of the silicon-germanium intermediate layer, and are stopped by the gate insulating layer. The migration of the atoms during the oxidation step is thus less prejudicial to the performance of the transistor, since the gate insulator of the transistor has already been produced and is not modified during this step. The migration of the germanium atoms towards the gate insulator, which is immobile, leads to a limitation of the surface defects between the channel and the insulator.
摘要翻译：包括富含锗的通道的晶体管。通过从所述中间层的下表面开始的硅 - 锗中间层中包含的硅的氧化产生富锗的通道。因此锗原子迁移到硅 - 锗中间层的上表面，并被栅极绝缘层阻挡。因此，在氧化步骤期间原子的迁移对晶体管的性能的影响较小，因为晶体管的栅极绝缘体已经被制造并且在该步骤期间不被修改。锗原子向固定的栅极绝缘体的迁移导致通道和绝缘体之间的表面缺陷的限制。

6. 发明授权

US07534701B2 Process for transferring a layer of strained semiconductor material 有权
标题翻译：用于转移应变半导体材料层的工艺
公开(公告)号：US07534701B2
公开(公告)日：2009-05-19
申请号：US12040134
申请日：2008-02-29
申请人： Bruno Ghyselen , Daniel Bensahel , Thomas Skotnicki
发明人： Bruno Ghyselen , Daniel Bensahel , Thomas Skotnicki
IPC分类号： H01L21/30
CPC分类号： H01L29/1054 , H01L21/76254 , H01L21/76259 , Y10S438/938
摘要： A process for preparing a semiconductor wafer with a strained layer having an elevated critical thickness. A first wafer having a strained layer of a semiconductor material on a matching layer is provided, with the semiconductor material having a first lattice parameter corresponding to a relaxed state and a first critical thickness corresponding to the first strained state, and the first thickness is less than the first critical thickness, The matching layer has a matching lattice parameter that is sufficiently different than the first lattice parameter to retain the strained layer in the strained state, The strained layer is transferred to a receiving substrate selected to provide the transferred strained layer with a second critical thickness that is greater than the first critical thickness, and additional semiconductor material is grown on the transferred strained layer to provide a second thickness that is greater than the first critical thickness and less than the second critical thickness, The invention also relates to the semiconductor structures that can be produced by the process.
摘要翻译：一种制备具有临界厚度升高的应变层的半导体晶片的方法。提供了在匹配层上具有半导体材料应变层的第一晶片，半导体材料具有对应于松弛状态的第一晶格参数和对应于第一应变状态的第一临界厚度，并且第一厚度较小匹配层具有与第一晶格参数充分不同的匹配晶格参数，以将应变层保持在应变状态。应变层被转移到选择的接收衬底以提供转移的应变层，第二临界厚度大于第一临界厚度，并且附加的半导体材料在转移的应变层上生长以提供大于第一临界厚度并小于第二临界厚度的第二厚度。本发明还涉及可以通过该方法生产的半导体结构。

7. 发明授权

US07078764B2 Method of fabricating a vertical quadruple conduction channel insulated gate transistor, and integrated circuit including this kind of transistor 有权
标题翻译：制造垂直四通导通绝缘栅晶体管的方法，以及包括这种晶体管的集成电路
公开(公告)号：US07078764B2
公开(公告)日：2006-07-18
申请号：US10852057
申请日：2004-05-24
申请人： Thomas Skotnicki , Emmanuel Josse
发明人： Thomas Skotnicki , Emmanuel Josse
IPC分类号： H01L29/76
CPC分类号： H01L29/66666 , H01L29/165 , H01L29/7827
摘要： The vertical insulated gate transistor includes, on a semiconductor substrate, a vertical pillar incorporating one of the source and drain regions at the top, a gate dielectric layer situated on the flanks of the pillar and on the top surface of the substrate, and a semiconductor gate resting on the gate dielectric layer. The other of the source and drain regions is in the bottom part of the pillar PIL and the insulated gate includes an isolated external portion 15 resting on the flanks of the pillar and an isolated internal portion 14 situated inside the pillar between the source and drain regions. The isolated internal portion is separated laterally from the isolated external portion by two connecting semiconductor regions PL1,PL2 extending between the source and drain regions, and forming two very fine pillars.
摘要翻译：垂直绝缘栅晶体管包括在半导体衬底上的垂直柱，其顶部包括源极和漏极区中的一个，位于柱的侧面和衬底顶表面上的栅极电介质层，以及半导体门静置在栅介质层上。源极和漏极区域中的另一个位于柱PIL的底部，并且绝缘栅极包括搁置在柱的侧面上的隔离的外部部分15和位于源极和漏极区域之间的柱内的隔离的内部部分14 。隔离的内部部分通过在源极和漏极区域之间延伸的两个连接半导体区域PL 1，PL 2从隔离的外部部分侧向分离，并形成两个非常细的柱。

8. 发明授权

US07042039B2 Integrated memory circuit for storing a binary datum in a memory cell 有权
标题翻译：用于将二进制数据存储在存储器单元中的集成存储器电路
公开(公告)号：US07042039B2
公开(公告)日：2006-05-09
申请号：US10702066
申请日：2003-11-05
申请人： Pascale Mazoyer , Alexandre Villaret , Thomas Skotnicki
发明人： Pascale Mazoyer , Alexandre Villaret , Thomas Skotnicki
IPC分类号： H01L27/108
CPC分类号： B82Y10/00 , G11C2216/08 , H01L29/788 , H01L29/7881 , H01L29/7888
摘要： An integrated memory circuit includes at least one memory cell formed by a single transistor whose gate (GR) has a lower face insulated from a channel region by an insulation layer containing a succession of potential wells, which are substantially arranged at a distance from the gate and from the channel region in a plane substantially parallel to the lower face of the gate. The potential wells are capable of containing an electric charge which is confined in the plane and can be controlled to move in the plane towards a first confinement region next to the source region or towards a second confinement region next to the drain region so as to define two memory states for the cell.
摘要翻译：集成存储器电路包括由单个晶体管形成的至少一个存储单元，其栅极（GR）具有通过包含一系列势阱的绝缘层与沟道区域绝缘的下表面，绝缘层基本上布置在与栅极相距一定距离处并且从基本上平行于栅极的下表面的平面中的沟道区域开始。势阱能够容纳限制在平面中的电荷，并且可以控制其在平面内朝向源极区域旁边的第一限制区域或靠近漏极区域的第二限制区域移动，以便限定两个单元的内存状态。

9. 发明授权

US07038285B2 Very high sensitivity magnetic sensor 有权
标题翻译：非常高灵敏度的磁传感器
公开(公告)号：US07038285B2
公开(公告)日：2006-05-02
申请号：US10149093
申请日：2000-12-06
申请人： Hervé Jaouen , Thomas Skotnicki , Malgorzata Jurczak
发明人： Hervé Jaouen , Thomas Skotnicki , Malgorzata Jurczak
IPC分类号： H01L29/82
CPC分类号： G10K9/13 , G01D5/242 , G01L9/0042 , Y10T428/1157 , Y10T428/1171 , Y10T428/19
摘要： A magnetic sensor includes a thin deformable membrane made of a conductive material forming a first plate of a capacitor which conducts an electric current therethrough. A second capacitor plate of the capacitor includes a doped region of a semiconductor substrate. A layer of a gaseous dielectric separates the two plates. The membrane deforms due to the effect of the Lorentz force generated by a magnetic field lying in the plane of the membrane and perpendicular to the lines of current being conducted therethrough. In addition, a process for fabricating this magnetic sensor is also provided as well as a device for measuring a magnetic field using the magnetic sensor.
摘要翻译：磁传感器包括由导电材料制成的薄的可变形膜，该导电材料形成电容器的第一板，其导通电流。电容器的第二电容器板包括半导体衬底的掺杂区域。气体介质层分离两个板。由于由位于膜的平面中的磁场产生的洛伦兹力的作用并且垂直于通过其传导的电流线，膜变形。此外，还提供了用于制造该磁传感器的工艺以及使用该磁传感器来测量磁场的装置。

10. 发明申请

US20050255682A1 Process for transferring a layer of strained semiconductor material 有权
标题翻译：用于转移应变半导体材料层的工艺
公开(公告)号：US20050255682A1
公开(公告)日：2005-11-17
申请号：US11165339
申请日：2005-06-24
申请人： Bruno Ghyselen , Daniel Bensahel , Thomas Skotnicki
发明人： Bruno Ghyselen , Daniel Bensahel , Thomas Skotnicki
IPC分类号： H01L21/301 , H01L21/762 , H01L29/10 , C30B1/00 , H01L21/20 , H01L21/36 , H01L21/425
CPC分类号： H01L29/1054 , H01L21/76254 , H01L21/76259 , Y10S438/938
摘要： The invention relates to a process for producing an electronic structure that includes a thin layer of strained semiconductor material from a donor wafer. The donor wafer has a lattice parameter matching layer that includes an upper layer of a semiconductor material having a first lattice parameter and a film of semiconductor material having a second, nominal, lattice parameter that is substantially different from the first lattice parameter and that is strained by the matching layer. This process includes transfer of the film to a receiving substrate. The invention also relates to the semiconductor structures that can be produced by the process.
摘要翻译：本发明涉及一种用于制造电子结构的方法，该电子结构包括来自施主晶片的应变半导体材料的薄层。施主晶片具有晶格参数匹配层，其包括具有第一晶格参数的半导体材料的上层和具有与第一晶格参数基本不同的第二标称晶格参数的半导体材料的膜，并且其被应变由匹配层。该方法包括将膜转移到接收衬底。本发明还涉及可以通过该方法生产的半导体结构。

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