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1. 发明授权

US07844422B2 Method and system for changing a description for a state transition function of a state machine engine 失效
标题翻译：用于改变状态机引擎的状态转换功能的描述的方法和系统
公开(公告)号：US07844422B2
公开(公告)日：2010-11-30
申请号：US11740558
申请日：2007-04-26
申请人： Rolf Fritz , Markus Kaltenbach , Ulrich Mayer , Thomas Pflueger , Cordt Starke , Jan Van Lunteren
发明人： Rolf Fritz , Markus Kaltenbach , Ulrich Mayer , Thomas Pflueger , Cordt Starke , Jan Van Lunteren
IPC分类号： G06F17/10
CPC分类号： G06F17/2247
摘要： The invention relates to a method of optimizing a state transition function specification for a state machine engine based on a probability distribution for the state transitions. For the preferred embodiment of the invention, a B-FSM state machine engine accesses a transition rule memory using a processor cache. The invention allows improving the cache hit rate by exploiting the probability distribution. The N transition rules that comprise a hash table entry will be loaded in a burst mode from the main memory, from which the N transition rules are transferred to the processor cache. Because the comparison of the actual state and input values against each of the transition rules can immediately start after each of these rules has been received, the overall performance is improved as the transition rule that is most likely to be selected is the first to be transferred as part of the burst access.
摘要翻译：本发明涉及一种基于状态转换的概率分布优化状态机引擎的状态转换功能规范的方法。对于本发明的优选实施例，B-FSM状态机引擎使用处理器高速缓存来访问转换规则存储器。本发明允许通过利用概率分布来提高缓存命中率。构成哈希表条目的N个转换规则将以从主存储器的突发模式加载，N个转换规则从该存储器传送到处理器高速缓存。因为实际状态和输入值与每个转换规则的比较可以在接收到每个这些规则之后立即开始，因为最有可能选择的转换规则是首先被转移的整体性能得到改善作为突发访问的一部分。

2. 发明授权

US07703058B2 Method and system for changing a description for a state transition function of a state machine engine 失效
标题翻译：用于改变状态机引擎的状态转换功能的描述的方法和系统
公开(公告)号：US07703058B2
公开(公告)日：2010-04-20
申请号：US11740487
申请日：2007-04-26
申请人： Rolf Fritz , Markus Kaltenbach , Ulrich Mayer , Thomas Pflueger , Cordt Starke , Jan Van Lunteren
发明人： Rolf Fritz , Markus Kaltenbach , Ulrich Mayer , Thomas Pflueger , Cordt Starke , Jan Van Lunteren
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： The invention relates to a method and system for the design and implementation of state machine engines. A first constraints checking step checks a state transition function created by a designer against constraints imposed by the implementation technology in order to detect all portions of the state transition function that are in conflict with the constraints. A subsequent conflict resolution step tries to determine one or more suggested ways to meet the conflicting constraints, by investigating how the original state transition function can be modified such that all constraints are met. A final presentation and selection step provides the designer textual and/or graphically results of the constraints check and suggested modifications. The modifications can be accepted interactively, or the state transition function can be changed manually. In the latter case, the modified state transition function will be processed starting again with the constraints checking step.
摘要翻译：本发明涉及一种用于设计和实施状态机发动机的方法和系统。第一约束检查步骤检查由设计者创建的状态转换函数，以抵制由实施技术施加的约束，以便检测与约束相冲突的状态转换函数的所有部分。随后的冲突解决步骤尝试通过调查如何修改原始状态转换功能以满足所有约束来确定满足冲突约束的一种或多种建议方式。最后的演示和选择步骤为设计者提供了约束检查和建议修改的文本和/或图形结果。可以交互接受修改，也可以手动更改状态转换功能。在后一种情况下，将通过约束检查步骤再次开始处理修改的状态转换功能。

3. 发明申请

US20080052488A1 Method for a Hash Table Lookup and Processor Cache 审中-公开
标题翻译：哈希表查找和处理器缓存的方法
公开(公告)号：US20080052488A1
公开(公告)日：2008-02-28
申请号：US11742718
申请日：2007-05-01
申请人： Rolf Fritz , Markus Kaltenbach , Ulrich Mayer , Thomas Pflueger , Cordt Starke , Jan Van Lunteren
发明人： Rolf Fritz , Markus Kaltenbach , Ulrich Mayer , Thomas Pflueger , Cordt Starke , Jan Van Lunteren
IPC分类号： G06F12/00
CPC分类号： G06F12/0864 , G06F12/0897
摘要： The present, invention improves the hash table lookup operation by using a new processor cache architecture. A speculative processing of entries stored in the cache is combined with a delayed evaluation of cache entries. The speculative processing means that for each cache entry retrieved from main memory in a step of the hash table lookup operation it is assumed that it already contains the selected hash table entry. The delayed evaluation means that certain steps of the lookup operation are performed in parallel with others. In advantageous embodiments the invention can also be used in conjunction with a hierarchy of inclusive caches. The preferred embodiments of the invention involve a new approach for a transition rule cache of a BaRT-FSM controller.
摘要翻译：本发明通过使用新的处理器高速缓存架构来改进哈希表查找操作。存储在缓存中的条目的推测性处理与缓存条目的延迟评估相结合。推测处理意味着对于在哈希表查找操作的步骤中从主存储器检索的每个高速缓存条目，假设它已经包含所选择的哈希表条目。延迟评估意味着查找操作的某些步骤与其他操作并行执行。在有利的实施例中，本发明还可以与包含缓存的层次结构一起使用。本发明的优选实施例涉及用于BaRT-FSM控制器的转换规则高速缓存的新方法。

4. 发明申请

US20070282573A1 Method and System for Changing a Description for a State Transition Function of a State Machine Engine 失效
标题翻译：用于更改状态机引擎的状态转换功能的描述的方法和系统
公开(公告)号：US20070282573A1
公开(公告)日：2007-12-06
申请号：US11740558
申请日：2007-04-26
申请人： Rolf Fritz , Markus Kaltenbach , Ulrich Mayer , Thomas Pflueger , Cordt Starke , Jan Van Lunteren
发明人： Rolf Fritz , Markus Kaltenbach , Ulrich Mayer , Thomas Pflueger , Cordt Starke , Jan Van Lunteren
IPC分类号： G06F17/18
CPC分类号： G06F17/2247
摘要： The invention relates to a method of optimizing a state transition function specification for a state machine engine based on a probability distribution for the state transitions. For the preferred embodiment of the invention, a B-FSM state machine engine accesses a transition rule memory using a processor cache. The invention allows improving the cache hit rate by exploiting the probability distribution. The N transition rules that comprise a hash table entry will be loaded in a burst mode from the main memory, from which the N transition rules are transferred to the processor cache. Because the comparison of the actual state and input values against each of the transition rules can immediately start after each of these rules has been received, the overall performance is improved as the transition rule that is most likely to be selected is the first to be transferred as part of the burst access.
摘要翻译：本发明涉及一种基于状态转换的概率分布优化状态机引擎的状态转换功能规范的方法。对于本发明的优选实施例，B-FSM状态机引擎使用处理器高速缓存来访问转换规则存储器。本发明允许通过利用概率分布来提高缓存命中率。构成哈希表条目的N个转换规则将以从主存储器的突发模式加载，N个转换规则从该存储器传送到处理器高速缓存。因为实际状态和输入值与每个转换规则的比较可以在接收到每个这些规则之后立即开始，因为最有可能被选择的转换规则是首先被转移的整体性能得到改善作为突发访问的一部分。

5. 发明申请

US20070283300A1 Method and System for Changing a Description for a State Transition Function of a State Machine Engine 失效
标题翻译：用于更改状态机引擎的状态转换功能的描述的方法和系统
公开(公告)号：US20070283300A1
公开(公告)日：2007-12-06
申请号：US11740487
申请日：2007-04-26
申请人： Rolf Fritz , Markus Kaltenbach , Ulrich Mayer , Thomas Pflueger , Cordt Starke , Jan Van Lunteren
发明人： Rolf Fritz , Markus Kaltenbach , Ulrich Mayer , Thomas Pflueger , Cordt Starke , Jan Van Lunteren
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： The invention relates to a method and system for the design and implementation of state machine engines. A first constraints checking step checks a state transition function created by a designer against constraints imposed by the implementation technology in order to detect all portions of the state transition function that are in conflict with the constraints. A subsequent conflict resolution step tries to determine one or more suggested ways to meet the conflicting constraints, by investigating how the original state transition function can be modified such that all constraints are met. A final presentation and selection step provides the designer textual and/or graphically results of the constraints check and suggested modifications. The modifications can be accepted interactively, or the state transition function can be changed manually. In the latter case, the modified state transition function will be processed starting again with the constraints checking step.
摘要翻译：本发明涉及一种用于设计和实施状态机发动机的方法和系统。第一约束检查步骤检查由设计者创建的状态转换函数，以抵制由实施技术施加的约束，以便检测与约束相冲突的状态转换函数的所有部分。随后的冲突解决步骤尝试通过调查如何修改原始状态转换功能以满足所有约束来确定满足冲突约束的一种或多种建议方式。最后的演示和选择步骤为设计者提供了约束检查和建议修改的文本和/或图形结果。可以交互接受修改，也可以手动更改状态转换功能。在后一种情况下，将通过约束检查步骤再次开始处理修改的状态转换功能。

6. 发明申请

US20100332798A1 Digital Processor and Method 审中-公开
标题翻译：数字处理器和方法
公开(公告)号：US20100332798A1
公开(公告)日：2010-12-30
申请号：US12825402
申请日：2010-06-29
申请人： Martin Doerr , Hubert Eichner , Markus Kaltenbach , Volker Koch , Ulrich Mayer , Thomas Pflueger , Thomas Schlipf , Cordt Starke , Jan Van Lunteren
发明人： Martin Doerr , Hubert Eichner , Markus Kaltenbach , Volker Koch , Ulrich Mayer , Thomas Pflueger , Thomas Schlipf , Cordt Starke , Jan Van Lunteren
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： G06F9/3012 , G06F9/3828 , G06F9/3891
摘要： A processor subunit for a processor for processing data. The processor subunit includes registers, and at least one functional unit for executing instructions on data. One or more registers of the registers are connected to an input of the at least one functional unit, where each register connected to the input of the at least one functional unit which has an input multiplexer. One or more registers of the registers are connected to an output of the at least one functional unit, where each register connected to the output of the at least one functional unit which has an input multiplexer. At least one output bus is connected to at least one register. At least one input bus is connected to at least one register. The processor subunit may be used in a processor, which may be used in a data streaming accelerator.
摘要翻译：用于处理数据的处理器的处理器子单元。处理器子单元包括寄存器和用于执行数据指令的至少一个功能单元。寄存器的一个或多个寄存器被连接到至少一个功能单元的输入，其中每个寄存器连接到具有输入多路复用器的至少一个功能单元的输入。寄存器的一个或多个寄存器被连接到至少一个功能单元的输出，其中每个寄存器连接到具有输入多路复用器的至少一个功能单元的输出端。至少一个输出总线连接到至少一个寄存器。至少一个输入总线连接到至少一个寄存器。处理器子单元可以用在可以在数据流加速器中使用的处理器中。

7. 发明授权

US08645620B2 Apparatus and method for accessing a memory device 失效
标题翻译：用于访问存储器件的装置和方法
公开(公告)号：US08645620B2
公开(公告)日：2014-02-04
申请号：US12143889
申请日：2008-06-23
申请人： Peter Buchmann , Martin Leo Schmatz , Jan Van Lunteren
发明人： Peter Buchmann , Martin Leo Schmatz , Jan Van Lunteren
IPC分类号： G06F12/00
CPC分类号： G06F12/02 , G06F12/0223 , G11C15/00
摘要： An interfacing apparatus and related method is provided for configuring to couple a plurality of memory devices being addressable by means of an address space to a processing unit. In one embodiment, the apparatus comprises a first memory access unit being adapted for receiving a memory address from said processing unit and for accessing said memory devices accordingly based on the address provided. It also comprises a second memory access unit being adapted for receiving content data from the processing unit and for controlling a search or update function accordingly for the received content data in one or more of the memory devices. In addition, an allocation unit is also provided for allocating a first part of the address space of the memory devices to said first memory access unit and allocating a second part of the address space of said memory devices to the second memory access unit, each of the memory access units being assigned to corresponding memory devices of the plurality of memory devices.
摘要翻译：提供了一种接口装置和相关方法，用于将通过地址空间寻址的多个存储器件耦合到处理单元。在一个实施例中，该装置包括第一存储器存取单元，其适于从所述处理单元接收存储器地址，并根据所提供的地址相应地访问所述存储器件。它还包括第二存储器存取单元，其适于从处理单元接收内容数据，并用于相应地控制一个或多个存储器件中的所接收的内容数据的搜索或更新功能。此外，还提供分配单元，用于将存储器件的地址空间的第一部分分配给所述第一存储器存取单元，并将所述存储器件的地址空间的第二部分分配给第二存储器存取单元，所述存储器访问单元被分配给所述多个存储器件的相应的存储器件。

8. 发明授权

US08635180B2 Multiple hash scheme for use in a pattern matching accelerator 失效
标题翻译：用于模式匹配加速器的多个哈希方案
公开(公告)号：US08635180B2
公开(公告)日：2014-01-21
申请号：US13021757
申请日：2011-02-06
申请人： Giora Biran , Christoph Hagleitner , Timothy Hume Heil , Jan Van Lunteren
发明人： Giora Biran , Christoph Hagleitner , Timothy Hume Heil , Jan Van Lunteren
IPC分类号： G06N5/04
CPC分类号： G06N5/047 , G06N5/025
摘要： A pattern matching accelerator (PMA) for assisting software threads to find the presence and location of strings in an input data stream that match a given pattern. The patterns are defined using regular expressions that are compiled into a data structure comprised of rules subsequently processed by the PMA. The patterns to be searched in the input stream are defined by the user as a set of regular expressions. The patterns to be searched are grouped in pattern context sets. The sets of regular expressions which define the pattern context sets are compiled to generate a rules structure used by the PMA hardware. The rules are compiled before search run time and stored in main memory, in rule cache memory within the PMA or a combination thereof. For each input character, the PMA executes the search and returns the search results.
摘要翻译：模式匹配加速器（PMA），用于帮助软件线程查找匹配给定模式的输入数据流中字符串的存在和位置。使用正则表达式定义模式，该正则表达式被编译成由PMA随后处理的规则组成的数据结构。在输入流中要搜索的模式由用户定义为一组正则表达式。要搜索的模式分组在模式上下文集中。定义模式上下文集的正则表达式集合被编译为生成由PMA硬件使用的规则结构。该规则在搜索运行时间之前被编译并存储在主存储器中，在PMA内的规则高速缓冲存储器中或其组合中。对于每个输入字符，PMA执行搜索并返回搜索结果。

9. 发明授权

US08620968B2 Determination and handling of subexpression overlaps in regular expression decompostions 失效
标题翻译：正则表达式分解中子表达式重叠的确定和处理
公开(公告)号：US08620968B2
公开(公告)日：2013-12-31
申请号：US13571431
申请日：2012-08-10
申请人： Kubilay Atasu , Florian Doerfler , Christoph Hagleitner , Jan Van Lunteren
发明人： Kubilay Atasu , Florian Doerfler , Christoph Hagleitner , Jan Van Lunteren
IPC分类号： G06F17/30
CPC分类号： G06F17/30985
摘要： A computer program product comprising a computer readable storage medium containing computer code that, when executed by a computer, implements a method for transforming a finite state automaton (FSA) of a regular expression, wherein the method includes determining, by a computer, a first subexpression R1 and a second subexpression R2 in the regular expression; calculating an overlap FSA, the overlap FSA configured to determine the existence of a partial overlap or a full overlap between the first subexpression R1 and the second subexpression R2; determining whether the overlap FSA has an accepting state; and in the event the overlap FSA is determined not to have an accepting state, determining that the transformation of the regular expression is safe, and constructing a transformed FSA of the regular expression comprising a first FSA for the first subexpression R1 and a second FSA for the second subexpression R2.
摘要翻译：一种计算机程序产品，包括包含计算机代码的计算机可读存储介质，所述计算机代码当由计算机执行时实现用于转换正则表达式的有限状态自动机（FSA）的方法，其中所述方法包括由计算机确定第一正则表达式中的子表达式R1和第二子表达式R2; 计算重叠FSA，配置为确定第一子表达式R1和第二子表达式R2之间的部分重叠或全部重叠的存在的重叠FSA; 确定重叠FSA是否具有接受状态; 并且在重叠FSA被确定为不具有接受状态的情况下，确定正则表达式的变换是安全的，并且构建包括用于第一子表达式R1的第一FSA和第二FSA的正则表达式的变换FSA，第二个子表达式R2。

10. 发明授权

US08402003B2 Performance monitoring mechanism for use in a pattern matching accelerator 失效
标题翻译：用于模式匹配加速器的性能监视机制
公开(公告)号：US08402003B2
公开(公告)日：2013-03-19
申请号：US13022904
申请日：2011-02-08
申请人： Giora Biran , Christoph Hagleitner , Timothy H. Heil , Jan Van Lunteren
发明人： Giora Biran , Christoph Hagleitner , Timothy H. Heil , Jan Van Lunteren
IPC分类号： G06F17/30
CPC分类号： G06F17/30985
摘要： A pattern matching accelerator (PMA) for assisting software threads to find the presence and location of strings in an input data stream that match a given pattern. The patterns are defined using regular expressions that are compiled into a data structure comprised of rules subsequently processed by the PMA. The patterns to be searched in the input stream are defined by the user as a set of regular expressions. The patterns to be searched are grouped in pattern context sets. The sets of regular expressions which define the pattern context sets are compiled to generate a rules structure used by the PMA hardware. The rules are compiled before search run time and stored in main memory, in rule cache memory within the PMA or a combination thereof. For each input character, the PMA executes the search and returns the search results.
摘要翻译：模式匹配加速器（PMA），用于帮助软件线程查找匹配给定模式的输入数据流中字符串的存在和位置。使用正则表达式定义模式，该正则表达式被编译成由PMA随后处理的规则组成的数据结构。在输入流中要搜索的模式由用户定义为一组正则表达式。要搜索的模式分组在模式上下文集中。编译定义模式上下文集的正则表达式集合，以生成PMA硬件使用的规则结构。该规则在搜索运行时间之前被编译并存储在主存储器中，在PMA内的规则高速缓冲存储器中或其组合中。对于每个输入字符，PMA执行搜索并返回搜索结果。

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