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1. 发明授权

US07679459B2 Multiphase signal generator 有权
标题翻译：多相信号发生器
公开(公告)号：US07679459B2
公开(公告)日：2010-03-16
申请号：US11962681
申请日：2007-12-21
申请人： Christian I. Menolfi , Martin Leo Schmatz , Thomas H. Toifl
发明人： Christian I. Menolfi , Martin Leo Schmatz , Thomas H. Toifl
IPC分类号： H03B27/00
CPC分类号： H03L7/0995 , H03L7/085 , H03L7/087 , H03L7/091 , H03L2207/06 , H04L7/033 , H04L7/0337
摘要： A signal generator for generating multiple phases includes a ring oscillator with at least one first adjustable delay stage and at least one second delay stage being serially arranged, wherein an output of the first delay stage is provided for delivering at least one first output phase and an output of the second delay stage is provided for delivering at least one second output phase, and an adjustment circuit for adjusting the delay of the first adjustable delay stage, wherein the adjustment circuit is provided for adjusting the phase relationship between the first output phase and the second output phase by means of setting a first propagation delay for the first delay stage.
摘要翻译：用于产生多相的信号发生器包括具有至少一个第一可调节延迟级的环形振荡器和串行布置的至少一个第二延迟级，其中第一延迟级的输出被提供用于传送至少一个第一输出相位和提供第二延迟级的输出用于传递至少一个第二输出相位和用于调整第一可调延迟级的延迟的调整电路，其中调整电路用于调整第一输出相位与第一输出相位之间的相位关系通过设置第一延迟级的第一传播延迟来实现第二输出相位。

2. 发明申请

US20100061497A1 METHOD AND APPARATUS FOR HANDLING OF CLOCK INFORMATION IN SERIVAL LINK PORTS 有权
标题翻译：在链接端口处理时钟信息的方法和装置
公开(公告)号：US20100061497A1
公开(公告)日：2010-03-11
申请号：US12547342
申请日：2009-08-25
申请人： Peter Buchmann , Martin Leo Schmatz
发明人： Peter Buchmann , Martin Leo Schmatz
IPC分类号： H04L7/00
CPC分类号： G06F13/4291 , H04L7/005 , H04L7/0083
摘要： A receiver for a serial link port that is enhanced by a clock-data-recovery loop connected to the forwarded clock signal lane. The receiver includes a phase interpolation means controlled by a phase position logic which gets its update signal from local phase update signals of the clock-data-recovery loop via a digital low pass filter. The receiver also provides a global phase update source selection logic to control which clock-data-recovery loop is distributing phase update information, and which clock-data-recovery loop is receiving phase update information based on the clock analysis block.
摘要翻译：用于串行链路端口的接收器，其通过连接到转发的时钟信号通道的时钟数据恢复环路来增强。接收机包括由相位位置逻辑控制的相位插值装置，它通过数字低通滤波器从时钟数据恢复环路的本地相位更新信号中获取其更新信号。接收机还提供全局相位更新源选择逻辑，以控制哪个时钟数据恢复环路正在分发相位更新信息，哪个时钟数据恢复环路正在接收基于时钟分析块的相位更新信息。

3. 发明授权

US07646839B2 Unified digital architecture 失效
标题翻译：统一数字架构
公开(公告)号：US07646839B2
公开(公告)日：2010-01-12
申请号：US11249851
申请日：2005-10-13
申请人： Hayden Clavie Cranford, Jr. , Vernon Roberts Norman , Martin Leo Schmatz
发明人： Hayden Clavie Cranford, Jr. , Vernon Roberts Norman , Martin Leo Schmatz
IPC分类号： H03D3/24
CPC分类号： H03L7/08 , H03L7/095 , H03L7/0995 , H03L7/10 , H04L7/0337 , H04L2027/0067
摘要： A unified, unidirectional serial link is described for providing data across wired media, such as a chip-to chip or a card-to-card interconnect. It consists of a transmit section and a receive section that are operated as pairs to allow the serial data communication. The serial link is implemented as part of a VLSI ASIC module and derives its power, data and clocking requirements from the host modules. The logic transmitter portion contains a phase locked loop (PLL), a dibit data register, a finite impulse response (FIR) filter and a transmit data register. The phase locked loop comprises both a digital coarse loop and an analog fine loop. The digital receiver portion contains a PLL, an FIR phase rotator, a phase rotator control state machine, and a clock buffer. The transmitter and the receiver each preferably utilize a pseudo-random bit stream (PRBS) generator and checker.
摘要翻译：描述了统一的单向串行链路，用于通过诸如芯片到芯片或卡到卡互连的有线介质提供数据。它由一个传输部分和一个接收部分组成，它们被成对地运行以允许串行数据通信。串行链路作为VLSI ASIC模块的一部分实现，并从主机模块中获得其功率，数据和时钟要求。逻辑发送器部分包含锁相环（PLL），双位数据寄存器，有限脉冲响应（FIR）滤波器和发送数据寄存器。锁相环包括数字粗回路和模拟精密回路。数字接收机部分包含PLL，FIR相位旋转器，相位旋转器控制状态机和时钟缓冲器。发射机和接收机各自优选地利用伪随机比特流（PRBS）生成器和检查器。

4. 发明授权

US07539243B1 Method and system for low-power integrating decision feedback equalizer with fast switched-capacitor feed forward path 失效
标题翻译：具有快速开关电容器前馈路径的低功率积分判决反馈均衡器的方法和系统
公开(公告)号：US07539243B1
公开(公告)日：2009-05-26
申请号：US12060140
申请日：2008-03-31
申请人： Thomas H. Toifl , Martin Leo Schmatz , Christian I. Menolfi
发明人： Thomas H. Toifl , Martin Leo Schmatz , Christian I. Menolfi
IPC分类号： H03H7/38 , H03K5/01 , H03L5/00
CPC分类号： H04L25/03057 , H04L2025/0349
摘要： A method and system for decision feedback equalization for digital transmission systems is provided. Low-power integrating decision feedback equalization with fast switched-capacitor paths are used, for suppressing intersymbol interference (ISI) due to past data symbols. The decision feedback equalization involves performing current-integrating decision feedback equalization at low-power employing a fast capacitively coupled feed-forward path at the output of a current-integrating buffer and inducing voltage changes by charge redistribution via coupled switching capacitors, and performing a voltage digital-to-analog conversation to determine a feedback coefficient as a coupling voltage. Then switches are reset to a pre-charge coupling voltage in the buffers to eliminate residual ISI caused by signal history, thereby achieving current integrating buffering with switched-capacitor feedback during the integration, and the capacitive switches are triggered by previous symbols.
摘要翻译：提供了一种用于数字传输系统的判决反馈均衡的方法和系统。使用具有快速开关电容路径的低功率积分判决反馈均衡，用于抑制由于过去的数据符号引起的符号间干扰（ISI）。判定反馈均衡涉及在电流积分缓冲器的输出处采用快速电容耦合前馈路径的低功率执行电流积分判决反馈均衡，并通过耦合的开关电容器通过电荷再分配来感应电压变化，并且执行电压数字到模拟对话，以确定反馈系数作为耦合电压。然后，开关被复位到缓冲器中的预充电耦合电压，以消除由信号历史引起的剩余ISI，从而在积分期间实现电流积分缓冲与开关电容器反馈，并且电容开关由先前的符号触发。

5. 发明授权

US07142624B2 Analog unidirectional serial link architecture 有权
公开(公告)号：US07142624B2
公开(公告)日：2006-11-28
申请号：US11225600
申请日：2005-09-13
申请人： Hayden Clavie Cranford, Jr. , Stacy Jean Garvin , Vernon Roberts Norman , Paul Alan Owczarski , Martin Leo Schmatz , Joseph Marsh Stevens
发明人： Hayden Clavie Cranford, Jr. , Stacy Jean Garvin , Vernon Roberts Norman , Paul Alan Owczarski , Martin Leo Schmatz , Joseph Marsh Stevens
IPC分类号： H03D3/24
CPC分类号： H03L7/0995 , H04L7/0004 , H04L7/0337
摘要： The present analog invention is related to a unified digital architecture comprising logic transmitter portions and logic receiver portions. A unified serial link system and method for transmitting digital data across wired media including a transmitter and a receiver portion is provided, one of the transmitter portion and receiver portion comprising a phase locked loop (PLL) circuit. The PLL circuit comprises a voltage control oscillator, a frequency divider, a phase-frequency detector, a charge pump and a multi-pole loop filter. One embodiment comprises a dual loop PLL having a digital coarse loop and an analog fine loop.

6. 发明授权

US06993107B2 Analog unidirectional serial link architecture 有权
公开(公告)号：US06993107B2
公开(公告)日：2006-01-31
申请号：US09996053
申请日：2001-11-28
申请人： Hayden Clavie Cranford, Jr. , Stacy Jean Garvin , Vernon Roberts Norman , Paul Alan Owczarski , Martin Leo Schmatz , Joseph Marsh Stevens
发明人： Hayden Clavie Cranford, Jr. , Stacy Jean Garvin , Vernon Roberts Norman , Paul Alan Owczarski , Martin Leo Schmatz , Joseph Marsh Stevens
IPC分类号： H03D3/24
CPC分类号： H03L7/0995 , H04L7/0004 , H04L7/0337
摘要： A unified serial link system and method for transmitting digital data across wired media including a transmitter and a receiver. The system comprises a phase locked loop (PLL) control circuit, a phase rotator circuit, a phase buffer circuit, and an equalization driver circuit. The phase rotator circuit is configured to acquire a clock phase from the phase locked loop control circuit and modulo shift the clock phase into a desired phase angle. One embodiment comprises a dual loop PLL having a digital coarse loop and an analog fine loop, a multi-stage voltage controlled oscillator, a voltage comparator, a PLL control logic, a digital to analog counter and a low pass filter. The fine loop includes the oscillator, a frequency divider, a phase-frequency detector, a charge pump and a loop filter.

7. 发明申请

US20120133541A1 ANALOG-DIGITAL CONVERTER 失效
标题翻译：模拟数字转换器
公开(公告)号：US20120133541A1
公开(公告)日：2012-05-31
申请号：US13306650
申请日：2011-11-29
申请人： Martin Leo Schmatz , Thomas H. Toifl
发明人： Martin Leo Schmatz , Thomas H. Toifl
IPC分类号： H03M1/12
CPC分类号： H03M1/462 , H03M1/466
摘要： An analog-digital converter includes converter units and a control unit. The converter units each including a comparator for performing a comparison using an input voltage, one or more capacitor ladders each having a signal line connected with first terminals of capacitors and with one input of the comparator, and switches each of which is associated with one of the capacitors, connected to a second terminal of the respective capacitor with a first or a second reference potential, the input voltage being shifted when switching one or more of the switches. The control unit controls the number of converter units, and to set the switching states of the plurality of switches in conversion cycles and to obtain comparison results from each of the comparators in a comparison subsequent to each setting of the switching states.
摘要翻译：模拟数字转换器包括转换器单元和控制单元。每个转换器单元包括用于使用输入电压进行比较的比较器，每个具有与电容器的第一端子连接的信号线和比较器的一个输入端的一个或多个电容器梯形，以及每个电容器梯级与电容器，连接到具有第一或第二参考电位的相应电容器的第二端子，当切换一个或多个开关时，输入电压被移位。控制单元控制转换器单元的数量，并且在转换周期的每个设置之后的比较中，将转换周期中的多个开关的开关状态设置为每个比较器的比较结果。

8. 发明授权

US08149979B2 Method and apparatus for handling of clock information in serial link ports 有权
标题翻译：在串行链路端口处理时钟信息的方法和装置
公开(公告)号：US08149979B2
公开(公告)日：2012-04-03
申请号：US12547342
申请日：2009-08-25
申请人： Peter Buchmann , Martin Leo Schmatz
发明人： Peter Buchmann , Martin Leo Schmatz
IPC分类号： H04L7/00
CPC分类号： G06F13/4291 , H04L7/005 , H04L7/0083
摘要： A receiver for a serial link port that is enhanced by a clock-data-recovery loop connected to the forwarded clock signal lane. The receiver includes a phase interpolation means controlled by a phase position logic which gets its update signal from local phase update signals of the clock-data-recovery loop via a digital low pass filter. The receiver also provides a global phase update source selection logic to control which clock-data-recovery loop is distributing phase update information, and which clock-data-recovery loop is receiving phase update information based on the clock analysis block.
摘要翻译：用于串行链路端口的接收器，其通过连接到转发的时钟信号通道的时钟数据恢复环路来增强。接收机包括由相位位置逻辑控制的相位插值装置，它通过数字低通滤波器从时钟数据恢复环路的本地相位更新信号中获取其更新信号。接收机还提供全局相位更新源选择逻辑，以控制哪个时钟数据恢复环路正在分发相位更新信息，哪个时钟数据恢复环路正在接收基于时钟分析块的相位更新信息。

9. 发明申请

US20090201097A1 CONTINUOUSLY TUNABLE INDUCTOR AND METHOD TO CONTINUOUSLY TUNE AN INDUCTOR 有权
标题翻译：连续电感电感器和连续调谐电感的方法
公开(公告)号：US20090201097A1
公开(公告)日：2009-08-13
申请号：US12369021
申请日：2009-02-11
申请人： Marcel A. Kossel , Thomas E. Morf , Martin Leo Schmatz , Jonas R. Weiss
发明人： Marcel A. Kossel , Thomas E. Morf , Martin Leo Schmatz , Jonas R. Weiss
IPC分类号： H03B5/18
CPC分类号： H03B5/1228 , H03B5/1215 , H03B5/1243 , H03B5/1256 , H03B5/1287 , H03B5/1296 , H03B2201/0216
摘要： A continuously tunable inductor with an inductive-capacitive (LC) voltage controlled oscillator (VCO) having a primary coil. The inductor includes a separate isolated secondary coil, a set of transistors composing a closed loop with the secondary coil, a magnetic coupling between the primary coil of the LC VCO and the secondary coil, an electrical coupling between the LC VCO and the set of transistors composing a closed loop with the secondary coil, and means for electric current injection into the closed loop. Such an inductor can be tuned by modulating a mutual inductance, which is magnetically and electrically coupled with the LC VCO by injection of an electric current (I0).
摘要翻译：具有电感电容（LC）压控振荡器（VCO）的连续可调电感器，具有初级线圈。电感器包括单独的隔离次级线圈，构成与次级线圈的闭环的一组晶体管，LC VCO的初级线圈与次级线圈之间的磁耦合，LC VCO与该组晶体管之间的电耦合与次级线圈组成闭环，以及将电流注入闭环的装置。可以通过调制通过注入电流（I0）与LC VCO磁耦合和电耦合的互感来调谐这种电感器。

10. 发明授权

US07492807B1 Pseudo-random bit sequence (PRBS) synchronization for interconnects with dual-tap scrambling devices and methods 失效
标题翻译：具有双抽头加扰设备和方法的互连的伪随机比特序列（PRBS）同步
公开(公告)号：US07492807B1
公开(公告)日：2009-02-17
申请号：US12098878
申请日：2008-04-07
申请人： Peter Buchmann , Martin Leo Schmatz
发明人： Peter Buchmann , Martin Leo Schmatz
IPC分类号： H04B1/00
CPC分类号： G06F13/4234
摘要： A method for synchronizing interconnects in a link system according to various embodiments can include receiving input data at a transmit side, the transmit side including at least one pseudo-random bit sequence scrambler; scrambling the input data at the transmit side via the pseudo-random bit scrambler with dual tap sequences resulting in scrambled data; transmitting the scrambled data with the dual tap sequences along all lanes of a plurality of lanes to a receive side via a bus interconnecting the plurality of lanes, the receive side including at least one pseudo-random bit sequence descrambler; synchronizing the at least one pseudo-random bit sequence scrambler to the at least one pseudo-random bit sequence descrambler; using an edge detection or transition detection device for synchronization of the descrambler to the scrambler; and de-scrambling the transmitted scrambled data at the receive side resulting in the input data.
摘要翻译：根据各种实施例的用于在链路系统中同步互连的方法可以包括在发送侧接收输入数据，所述发送侧包括至少一个伪随机比特序列加扰器; 经由具有双抽头序列的伪随机比特加扰器在发送侧加扰输入数据，导致加扰数据; 通过经由互连所述多个通道的总线将具有多个通道所有通道的双抽头序列的加扰数据发送到接收侧，所述接收侧包括至少一个伪随机位序列解扰器; 将所述至少一个伪随机比特序列加扰器同步至所述至少一个伪随机比特序列解扰器; 使用边缘检测或转换检测装置来将解扰器同步到扰频器; 并且在接收侧对发送的加扰数据进行去加扰，得到输入数据。

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