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1. 发明授权

US08635180B2 Multiple hash scheme for use in a pattern matching accelerator 失效
标题翻译：用于模式匹配加速器的多个哈希方案
公开(公告)号：US08635180B2
公开(公告)日：2014-01-21
申请号：US13021757
申请日：2011-02-06
申请人： Giora Biran , Christoph Hagleitner , Timothy Hume Heil , Jan Van Lunteren
发明人： Giora Biran , Christoph Hagleitner , Timothy Hume Heil , Jan Van Lunteren
IPC分类号： G06N5/04
CPC分类号： G06N5/047 , G06N5/025
摘要： A pattern matching accelerator (PMA) for assisting software threads to find the presence and location of strings in an input data stream that match a given pattern. The patterns are defined using regular expressions that are compiled into a data structure comprised of rules subsequently processed by the PMA. The patterns to be searched in the input stream are defined by the user as a set of regular expressions. The patterns to be searched are grouped in pattern context sets. The sets of regular expressions which define the pattern context sets are compiled to generate a rules structure used by the PMA hardware. The rules are compiled before search run time and stored in main memory, in rule cache memory within the PMA or a combination thereof. For each input character, the PMA executes the search and returns the search results.
摘要翻译：模式匹配加速器（PMA），用于帮助软件线程查找匹配给定模式的输入数据流中字符串的存在和位置。使用正则表达式定义模式，该正则表达式被编译成由PMA随后处理的规则组成的数据结构。在输入流中要搜索的模式由用户定义为一组正则表达式。要搜索的模式分组在模式上下文集中。定义模式上下文集的正则表达式集合被编译为生成由PMA硬件使用的规则结构。该规则在搜索运行时间之前被编译并存储在主存储器中，在PMA内的规则高速缓冲存储器中或其组合中。对于每个输入字符，PMA执行搜索并返回搜索结果。

2. 发明授权

US08620968B2 Determination and handling of subexpression overlaps in regular expression decompostions 失效
标题翻译：正则表达式分解中子表达式重叠的确定和处理
公开(公告)号：US08620968B2
公开(公告)日：2013-12-31
申请号：US13571431
申请日：2012-08-10
申请人： Kubilay Atasu , Florian Doerfler , Christoph Hagleitner , Jan Van Lunteren
发明人： Kubilay Atasu , Florian Doerfler , Christoph Hagleitner , Jan Van Lunteren
IPC分类号： G06F17/30
CPC分类号： G06F17/30985
摘要： A computer program product comprising a computer readable storage medium containing computer code that, when executed by a computer, implements a method for transforming a finite state automaton (FSA) of a regular expression, wherein the method includes determining, by a computer, a first subexpression R1 and a second subexpression R2 in the regular expression; calculating an overlap FSA, the overlap FSA configured to determine the existence of a partial overlap or a full overlap between the first subexpression R1 and the second subexpression R2; determining whether the overlap FSA has an accepting state; and in the event the overlap FSA is determined not to have an accepting state, determining that the transformation of the regular expression is safe, and constructing a transformed FSA of the regular expression comprising a first FSA for the first subexpression R1 and a second FSA for the second subexpression R2.
摘要翻译：一种计算机程序产品，包括包含计算机代码的计算机可读存储介质，所述计算机代码当由计算机执行时实现用于转换正则表达式的有限状态自动机（FSA）的方法，其中所述方法包括由计算机确定第一正则表达式中的子表达式R1和第二子表达式R2; 计算重叠FSA，配置为确定第一子表达式R1和第二子表达式R2之间的部分重叠或全部重叠的存在的重叠FSA; 确定重叠FSA是否具有接受状态; 并且在重叠FSA被确定为不具有接受状态的情况下，确定正则表达式的变换是安全的，并且构建包括用于第一子表达式R1的第一FSA和第二FSA的正则表达式的变换FSA，第二个子表达式R2。

3. 发明授权

US08402003B2 Performance monitoring mechanism for use in a pattern matching accelerator 失效
标题翻译：用于模式匹配加速器的性能监视机制
公开(公告)号：US08402003B2
公开(公告)日：2013-03-19
申请号：US13022904
申请日：2011-02-08
申请人： Giora Biran , Christoph Hagleitner , Timothy H. Heil , Jan Van Lunteren
发明人： Giora Biran , Christoph Hagleitner , Timothy H. Heil , Jan Van Lunteren
IPC分类号： G06F17/30
CPC分类号： G06F17/30985
摘要： A pattern matching accelerator (PMA) for assisting software threads to find the presence and location of strings in an input data stream that match a given pattern. The patterns are defined using regular expressions that are compiled into a data structure comprised of rules subsequently processed by the PMA. The patterns to be searched in the input stream are defined by the user as a set of regular expressions. The patterns to be searched are grouped in pattern context sets. The sets of regular expressions which define the pattern context sets are compiled to generate a rules structure used by the PMA hardware. The rules are compiled before search run time and stored in main memory, in rule cache memory within the PMA or a combination thereof. For each input character, the PMA executes the search and returns the search results.
摘要翻译：模式匹配加速器（PMA），用于帮助软件线程查找匹配给定模式的输入数据流中字符串的存在和位置。使用正则表达式定义模式，该正则表达式被编译成由PMA随后处理的规则组成的数据结构。在输入流中要搜索的模式由用户定义为一组正则表达式。要搜索的模式分组在模式上下文集中。编译定义模式上下文集的正则表达式集合，以生成PMA硬件使用的规则结构。该规则在搜索运行时间之前被编译并存储在主存储器中，在PMA内的规则高速缓冲存储器中或其组合中。对于每个输入字符，PMA执行搜索并返回搜索结果。

4. 发明申请

US20120314481A1 CELL-STATE MEASUREMENT IN RESISTIVE MEMORY 审中-公开
公开(公告)号：US20120314481A1
公开(公告)日：2012-12-13
申请号：US13591828
申请日：2012-08-22
申请人： Gael Close , Christoph Hagleitner , Angeliki Pantazi , Nikolaos Papandreou , Charalampos Pozidis , Abu Sebastian
发明人： Gael Close , Christoph Hagleitner , Angeliki Pantazi , Nikolaos Papandreou , Charalampos Pozidis , Abu Sebastian
IPC分类号： G11C11/00
CPC分类号： G11C5/147 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C13/0061 , G11C2211/5645
摘要： Apparatus and method for measuring the state of a resistive memory cell. A bias voltage controller applies a bias voltage to the cell and controls the level of the bias voltage. A feedback signal generator senses cell current due to the bias voltage and generates a feedback signal (SFB) dependent on the difference between the cell current and a predetermined target current. The bias voltage controller controls the bias voltage level in dependence on the feedback signal (SFB) such that the cell current converges on the target current. An output is provided indicative of the bias voltage level at which the cell current corresponds to the target current, thus providing a voltage-based metric for cell-state.

5. 发明申请

US20120198213A1 PACKET HANDLER INCLUDING PLURALITY OF PARALLEL ACTION MACHINES 审中-公开
标题翻译：包装处理器，包括平行动作机械的多样性
公开(公告)号：US20120198213A1
公开(公告)日：2012-08-02
申请号：US13017949
申请日：2011-01-31
申请人： Francois Abel , Jean Calvignac , Christoph Hagleitner , Fabrice Verplanken
发明人： Francois Abel , Jean Calvignac , Christoph Hagleitner , Fabrice Verplanken
IPC分类号： G06F9/30
CPC分类号： G06F9/3853 , G06F9/3016 , G06F9/3889
摘要： A packet handler for a packet processing system includes a plurality of parallel action machines, each of the plurality of parallel action machines being configured to perform a respective packet processing function; and a plurality of action machine input registers, wherein each of the plurality of parallel action machines is associated with one or more of the plurality of action machine input registers, and wherein an action machine of the plurality of parallel action machines is automatically triggered to perform its respective packet processing function in the event that data sufficient to perform the actions machine's respective packet processing function is written into the action machine's one or more respective action machine input registers.
摘要翻译：用于分组处理系统的分组处理器包括多个并行动作机器，所述多个并行动作机器中的每一个被配置为执行相应的分组处理功能; 以及多个动作机械输入寄存器，其中，所述多个并行动作机器中的每一个与所述多个动作机械输入寄存器中的一个或多个相关联，并且其中，所述多个并行动作机器的动作机器被自动触发以执行在足以执行动作机器相应的分组处理功能的数据被写入动作机器的一个或多个相应动作机器输入寄存器的情况下，其各自的分组处理功能。

6. 发明申请

US20050157575A1 Storage device and method 审中-公开
标题翻译：存储设备和方法
公开(公告)号：US20050157575A1
公开(公告)日：2005-07-21
申请号：US10999351
申请日：2004-11-30
申请人： Gerd Binnig , Evangelos Eleftheriou , Christoph Hagleitner
发明人： Gerd Binnig , Evangelos Eleftheriou , Christoph Hagleitner
IPC分类号： G11B9/00 , G11B11/00 , G11C7/00
CPC分类号： G11B9/149 , B82Y10/00 , G11B11/007
摘要： A storage device is provided, comprising of a storage surface having perturbations representative of information stored in the storage device; a lever having at least one tip facing the storage surface and movable substantially parallel thereto; and a variable capacitor having a first plate and a second plate, the first plate being integral to the storage surface and the second plate being integral to the lever, wherein movement of the lever relative to the surface produces variation in the capacitance of the variable capacitor in response to the tip scanning across the perturbations of the surface.
摘要翻译：提供了一种存储装置，包括具有表示存储在存储装置中的信息的扰动的存储表面; 杠杆，其具有面向所述存储表面并且可基本上平行于其移动的至少一个尖端; 以及具有第一板和第二板的可变电容器，所述第一板与所述存储表面成一体并且所述第二板与所述杠杆成一体，其中所述杠杆相对于所述表面的运动产生所述可变电容器的电容变化响应于穿过表面扰动的尖端扫描。

7. 发明授权

US08799188B2 Algorithm engine for use in a pattern matching accelerator 有权
标题翻译：用于模式匹配加速器的算法引擎
公开(公告)号：US08799188B2
公开(公告)日：2014-08-05
申请号：US13023003
申请日：2011-02-08
申请人： Giora Biran , Christoph Hagleitner , Timothy H. Heil , Russell D. Hoover , Jan Van Lunteren
发明人： Giora Biran , Christoph Hagleitner , Timothy H. Heil , Russell D. Hoover , Jan Van Lunteren
IPC分类号： G06F15/18
CPC分类号： G06N5/025
摘要： A pattern matching accelerator (PMA) for assisting software threads to find the presence and location of strings in an input data stream that match a given pattern. The patterns are defined using regular expressions that are compiled into a data structure comprised of rules subsequently processed by the PMA. The patterns to be searched in the input stream are defined by the user as a set of regular expressions. The patterns to be searched are grouped in pattern context sets. The sets of regular expressions which define the pattern context sets are compiled to generate a rules structure used by the PMA hardware. The rules are compiled before search run time and stored in main memory, in rule cache memory within the PMA or a combination thereof. For each input character, the PMA executes the search and returns the search results.
摘要翻译：模式匹配加速器（PMA），用于帮助软件线程查找匹配给定模式的输入数据流中字符串的存在和位置。使用正则表达式定义模式，该正则表达式被编译成由PMA随后处理的规则组成的数据结构。在输入流中要搜索的模式由用户定义为一组正则表达式。要搜索的模式分组在模式上下文集中。编译定义模式上下文集的正则表达式集合，以生成PMA硬件使用的规则结构。该规则在搜索运行时间之前被编译并存储在主存储器中，在PMA内的规则高速缓冲存储器中或其组合中。对于每个输入字符，PMA执行搜索并返回搜索结果。

8. 发明授权

US08681819B2 Programmable multifield parser packet 失效
标题翻译：可编程多字段解析器包
公开(公告)号：US08681819B2
公开(公告)日：2014-03-25
申请号：US13017963
申请日：2011-01-31
申请人： Francois Abel , Jean Calvignac , Christoph Hagleitner , Jan van Lunteren , Fabrice Verplanken
发明人： Francois Abel , Jean Calvignac , Christoph Hagleitner , Jan van Lunteren , Fabrice Verplanken
IPC分类号： G01R31/08 , H04J3/24
CPC分类号： H04L69/22
摘要： A method of operating a packet parser in a computing system includes providing a configurable packet pointer by the packet parser, the packet pointer configured to index a configurable number of atomic parsing elements, the atomic parsing elements having a configurable size, in a data stream received by the computing system for extraction, wherein the indexed atomic parsing elements are non-contiguous in the data stream; and receiving the extracted indexed atomic parsing elements from the data stream by the packet parser.
摘要翻译：一种在计算系统中操作分组解析器的方法包括：由分组解析器提供可配置的分组指针，所述分组指针被配置为在接收的数据流中索引可配置数量的原子解析元素（所述原子解析元素具有可配置大小）由所述计算系统提取，其中所述索引的原子解析元素在所述数据流中不连续; 以及由分组解析器从数据流接收提取的索引原子解析元素。

9. 发明授权

US08447749B2 Local results processor for use in a pattern matching accelerator 失效
标题翻译：本地结果处理器用于模式匹配加速器
公开(公告)号：US08447749B2
公开(公告)日：2013-05-21
申请号：US13022967
申请日：2011-02-08
申请人： Giora Biran , Christoph Hagleitner , Timothy H. Heil , Jan Van Lunteren
发明人： Giora Biran , Christoph Hagleitner , Timothy H. Heil , Jan Van Lunteren
IPC分类号： G06F17/30
CPC分类号： G06F17/30985 , G06F11/1402
摘要： A pattern matching accelerator (PMA) for assisting software threads to find the presence and location of strings in an input data stream that match a given pattern. The patterns are defined using regular expressions that are compiled into a data structure comprised of rules subsequently processed by the PMA. The patterns to be searched in the input stream are defined by the user as a set of regular expressions. The patterns to be searched are grouped in pattern context sets. The sets of regular expressions which define the pattern context sets are compiled to generate a rules structure used by the PMA hardware. The rules are compiled before search run time and stored in main memory, in rule cache memory within the PMA or a combination thereof. For each input character, the PMA executes the search and returns the search results.
摘要翻译：模式匹配加速器（PMA），用于帮助软件线程查找匹配给定模式的输入数据流中字符串的存在和位置。使用正则表达式定义模式，该正则表达式被编译成由PMA随后处理的规则组成的数据结构。在输入流中要搜索的模式由用户定义为一组正则表达式。要搜索的模式分组在模式上下文集中。编译定义模式上下文集的正则表达式集合，以生成PMA硬件使用的规则结构。该规则在搜索运行时间之前被编译并存储在主存储器中，在PMA内的规则高速缓冲存储器中或其组合中。对于每个输入字符，PMA执行搜索并返回搜索结果。

10. 发明申请

US20120284222A1 COMPILING PATTERN CONTEXTS TO SCAN LANES UNDER INSTRUCTION EXECUTION CONSTRAINTS 有权
标题翻译：根据指令执行规则编写模式到扫描范围
公开(公告)号：US20120284222A1
公开(公告)日：2012-11-08
申请号：US13098772
申请日：2011-05-02
申请人： Kubilay Atasu , Florian Dorfler , Christoph Hagleitner , Jan Van Lunteren
发明人： Kubilay Atasu , Florian Dorfler , Christoph Hagleitner , Jan Van Lunteren
IPC分类号： G06N5/02
CPC分类号： H04L63/1408
摘要： A technique for determining scan lanes is provided. For a set of patterns, a number of scan lanes is estimated to be utilized on an accelerator. The number of the scan lanes estimated for the set of patterns is iteratively incremented to optimize a throughput of the accelerator. The set of patterns is distributed to the number of the scan lanes as a distribution, and each one of the scan lanes has a predetermined number of engines. A size of a memory space is evaluated that is needed for the distribution to distribute the set of patterns onto the number of scan lanes.
摘要翻译：提供了一种用于确定扫描通道的技术。对于一组模式，估计在加速器上使用多个扫描通道。针对该组模式估计的扫描通道的数量被迭代地增加以优化加速器的吞吐量。该组图案被分配到扫描通道的数量作为分布，并且每个扫描通道具有预定数量的引擎。评估存储器空间的大小，以便将该组图案分配到扫描通道数上。

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