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    • 1. 发明授权
    • Determining chargeable duration at the home agent for a prepaid MIP session
    • 确定预付费MIP会话的归属代理的计费期限
    • US07366136B1
    • 2008-04-29
    • US11138343
    • 2005-05-27
    • Rohit S. KalbagRobert EphraimBen Chen
    • Rohit S. KalbagRobert EphraimBen Chen
    • H04Q7/00
    • H04L12/14H04L12/1439H04L29/12311H04L61/2084H04W80/04
    • Duration based accounting for a packet data service, for example offered as a prepaid mobile IP (MIP) service through a public mobile wireless communication network, uses last detected user activity to determine the end of each session for accounting purposes. The accounting policy or algorithm defines user activity so as to include receipt of signaling related to the MIP session, such as signaling related to a termination by the user or the user's mobile station, in addition to packet data routed for the mobile station. If a session ends due to a network termination, e.g. binding expires or the network disconnects upon prepaid quota exhaustion, then the last user activity used for accounting purposes is the last data packet communication to/from the mobile station or the last received MIP session-related signaling message. For example, if MIP signaling terminates the session, then the session duration runs until receipt of that signaling.
    • 对于例如通过公共移动无线通信网络提供为预付费移动IP(MIP)服务的分组数据服务的基于持续时间的计费使用最后检测到的用户活动来确定用于会计目的的每个会话的结束。 计费策略或算法定义用户活动,以便包括与MIP会话相关的信令的接收,诸如与用户或用户的移动台的终止相关的信令,以及为移动台路由的分组数据。 如果会话由于网络终止而结束,例如, 绑定到期或网络在预付配额耗尽时断开连接,则用于会计目的的最后一个用户活动是到/从移动台或最后接收的MIP会话相关信令消息的最后一个数据分组通信。 例如,如果MIP信令终止会话,那么会话持续时间将持续到接收到该信令。
    • 3. 发明申请
    • Method And System For Providing A Modular Server On USB Flash Storage
    • 在USB闪存上提供模块化服务器的方法和系统
    • US20070250564A1
    • 2007-10-25
    • US11757955
    • 2007-06-04
    • Ben Chen
    • Ben Chen
    • G06F15/16
    • G06F9/44573G06F9/4401
    • A method and system for providing a modular server-on-a-USB-flash-storage is disclosed. The server-on-a-USB-flash-storage is installed on a computing device. The method and system include providing USB interface logic, USB Local Control Program, a flash memory and a set of control button connectors, light emitting diodes (LED) connectors and a liquid crystal display (LCD) connector. The USB Local Control Program is coupled with the USB interface logic and the flash memory. The USB interface logic interacts with the computing device and allows computing device to detect the server board. The USB Local Control Program boots up the server and prepares the computing device for use as the server. The flash memory stores a server image for the server, which is provided to the computing device using the USB Local Control Program. The control button connectors allow the server to be turned on, shut down gracefully, or restored to its initial state, by a single press of buttons connected to these connectors. The LED and LCD connectors allow the system status to be displayed or shown.
    • 公开了一种用于在USB闪存存储器上提供模块化服务器的方法和系统。 服务器上的USB闪存存储器安装在计算设备上。 该方法和系统包括提供USB接口逻辑,USB本地控制程序,闪存和一组控制按钮连接器,发光二极管(LED)连接器和液晶显示器(LCD)连接器。 USB本地控制程序与USB接口逻辑和闪存耦合。 USB接口逻辑与计算设备交互,允许计算设备检测服务器主板。 USB本地控制程序启动服务器并准备用作服务器的计算设备。 闪存存储服务器的服务器映像,该服务器映像使用USB本地控制程序提供给计算设备。 控制按钮连接器可以通过连接到这些连接器的一个按钮打开服务器,正常关闭或恢复到初始状态。 LED和LCD连接器可以显示或显示系统状态。
    • 4. 发明授权
    • Method for probing the error of energy and dosage in the high-energy ion
implantation
    • 探测高能离子注入能量和剂量误差的方法
    • US5882947A
    • 1999-03-16
    • US906085
    • 1997-08-05
    • Jen-Tsung LinBen ChenEddie Chen
    • Jen-Tsung LinBen ChenEddie Chen
    • H01J37/317G01R31/26H01L21/66
    • H01J37/3171H01J2237/30433H01J2237/31703
    • A method for probing the error of energy or dosage in the high-energy ion implantation is disclosed herein. The error source that is from either the energy of ion implantation or the dosage of ion implantation non-normal is decided via the thermal signal value and the thickness of the remained oxidation layer after etching step. The error source can be decided by using different decision standards for phosphorous ion implantation or boron ion implantation. The method comprises the steps as follow: a semiconductor silicon wafer is provided as a test wafer, and an oxidation layer is then formed over the test wafer. A high-energy ion implantation, such as phosphorous ion implantation or boron ion implantation is performed. The oxidation layer is etched via an etching process in a fixing etching time. The thickness of the remained oxidation layer after the etching process is probed. A thermal probe is applied to probe the thermal wave signal from the ion-implant-induced damage. Afterward, the thermal wave signal value and the remained oxidation thickness of the high-energy ion implantation are compared with that of a preceding standard group. Then, the different decision standards created from the thermal wave signal value and the remained oxidation thickness for the high-energy phosphorous or boron ion implantation process are submitted. The error source that is from either the energy of ion implantation or the dosage of ion implantation in non-normal state can be decided via the different decision standards.
    • 本文公开了一种用于探测高能离子注入中能量或剂量误差的方法。 通过离子注入的能量或离子注入非正常的剂量的误差源通过热信号值和蚀刻步骤后剩余的氧化层的厚度来确定。 误差源可以通过使用磷离子注入或硼离子注入的不同决策标准来决定。 该方法包括以下步骤:提供半导体硅晶片作为测试晶片,然后在测试晶片上形成氧化层。 进行高能离子注入,例如磷离子注入或硼离子注入。 在定影蚀刻时刻通过蚀刻工艺蚀刻氧化层。 探测蚀刻后剩余氧化层的厚度。 应用热探针来探测离子植入物引起的损伤的热波信号。 之后,将高能离子注入的热波信号值和剩余的氧化厚度与前面的标准组进行比较。 然后,提出了从高能磷或硼离子注入工艺的热波信号值和剩余氧化厚度产生的不同决定标准。 离子注入的能量或非正常状态下离子注入剂量的误差源可以通过不同的决策标准来决定。
    • 6. 发明授权
    • VLSI process with global planarization
    • VLSI过程与全局平面化
    • US5366911A
    • 1994-11-22
    • US240572
    • 1994-05-11
    • Water LurBen Chen
    • Water LurBen Chen
    • H01L21/336H01L21/768H01L21/335H01L21/265
    • H01L21/76888H01L21/76801H01L29/66621H01L23/5329H01L23/53295H01L2924/0002
    • A method of fabricating an integrated circuit which maintains global planarization throughout the process flow is achieved. Trenched isolation regions are formed within a silicon substrate. Trenched polysilicon gate electrodes are formed within the silicon substrate and within the trenched isolation regions. Source and drain regions are formed within the silicon substrate wherein the top surfaces of the trenched isolation regions, the trenched polysilicon gate electrodes, and source and drain regions form a planarized top surface of the silicon substrate. A pre-metal dielectric layer is deposited over the planarized top surface. Contact openings are formed by etching through the dielectric to the trenched polysilicon gate electrodes and to the source and drain regions. The contact openings are filled with tungsten plugs wherein the top surfaces of the pre-metal dielectric and the tungsten plugs form a planarized top surface of the silicon substrate. A first metal layer is deposited over the planarized top surface. Oxygen ions are implanted into the first metal layer whereby the first metal layer is transformed into an insulator layer except where the layer is covered by photoresist wherein the top surface of the first metal layer forms a planarized top surface of the silicon substrate. The inter-metal dielectric layer and second metal layer are deposited, patterned, and planarized .
    • 实现了在整个工艺流程中保持全局平坦化的集成电路的制造方法。 沟槽隔离区形成在硅衬底内。 在硅衬底内并且在沟槽隔离区域内形成有沟槽状多晶硅栅电极。 源极和漏极区域形成在硅衬底内,其中沟槽隔离区的顶表面,沟槽多晶硅栅极电极和源极和漏极区域形成硅衬底的平坦化顶表面。 在平坦化的顶表面上沉积预金属介电层。 通过电介质蚀刻到沟槽多晶硅栅极电极和源极和漏极区域形成接触开口。 接触开口填充有钨插塞,其中前金属电介质和钨插塞的顶表面形成硅衬底的平坦化顶表面。 第一金属层沉积在平坦化的顶表面上。 将氧离子注入到第一金属层中,由此第一金属层转变成绝缘体层,除了其上被光致抗蚀剂覆盖的区域之外,其中第一金属层的顶表面形成硅衬底的平坦化顶表面。 金属间介电层和第二金属层被沉积​​,图案化和平坦化。
    • 8. 发明申请
    • Method for molding a small form factor digital memory card
    • 用于成型小型数字存储卡的方法
    • US20060281229A1
    • 2006-12-14
    • US11148999
    • 2005-06-10
    • Wei KohBen ChenDavid Chen
    • Wei KohBen ChenDavid Chen
    • H01L21/00
    • H05K3/284B29C45/14647B29C45/14655B29C45/14836B29C45/2708H01L21/565H01L2924/0002H05K1/117H05K2201/10159H05K2201/10689H05K2201/10734H05K2203/1311H05K2203/1316H05K2203/304H01L2924/00
    • A method for molding digital storage memory cards such as, for example, multimedia cards (MMC), secure digital cards (SD), and similar small form factor digital memory cards. A PCA subassembly including, for example, a leadframe (TSOP) package for enclosing a flash IC and a (e.g., land grad array) controller package for enclosing a controller IC are mounted on a printed wiring board within a mold cavity. A high melt flow index resin is injected into the mold cavity to form an integral, solid body within which to completely encapsulate the flash IC and controller packages and form a cover over top the flash IC package so as to maintain the required memory card height tolerance. In one embodiment, the resin material is injected downwardly into the mold cavity from locations above the respective rows of leads of the flash IC package. In another embodiment, the resin material is injected laterally into the mold body from locations at opposite sides thereof adjacent the respective rows of leads of the flash IC package.
    • 一种用于模制数字存储存储卡的方法,例如多媒体卡(MMC),安全数字卡(SD)和类似的小尺寸数字存储卡。 包括例如用于封装闪存IC的引线框架(TSOP)封装和用于封闭控制器IC的(例如,平台梯度阵列)控制器封装件的PCA子组件安装在模具腔内的印刷线路板上。 将高熔体流动指数树脂注入到模腔中以形成整体的固体,其中完全封装闪存IC和控制器封装,并在闪存IC封装之上形成盖子,以便保持所需的存储卡高度公差 。 在一个实施例中,将树脂材料从闪存IC封装的相应引线行上方的位置向下注入模腔中。 在另一个实施例中,树脂材料从相邻于闪光IC封装的引线行的相对侧的位置侧向注入模具体。
    • 9. 发明申请
    • Configurable flash memory controller and method of use
    • 可配置的闪存控制器和使用方法
    • US20060184721A1
    • 2006-08-17
    • US11060649
    • 2005-02-16
    • Ben Chen
    • Ben Chen
    • G06F12/00
    • G06F13/1694
    • A FLASH memory controller is disclosed. The controller comprises a microcontroller. The microcontroller including firmware for providing different mappings for different types of FLASH memory chips. The controller also includes FLASH control logic for communicating with the microcontroller and adapted to communicate via a FLASH data bus to at least one FLASH memory chip. The FLASH control logic including mapping logic for configuring the FLASH data bus based upon the type of FLASH memory chip coupled thereto. A method and system in accordance with the present invention provides the following advantages: Configurable data bus on the FLASH memory controller through software to simplify routing complexity. Configurable chip select and control bus for flexibility of FLASH memory placement. Elimination of external resistor network for layout simplicity. A scalable architecture for higher data bus bandwidth support. Auto-detection of FLASH memory type and capacity configuration.
    • 公开了一种闪速存储器控制器。 控制器包括微控制器。 微控制器包括用于为不同类型的闪速存储器芯片提供不同映射的固件。 控制器还包括用于与微控制器进行通信并适于经由FLASH数据总线与至少一个闪速存储器芯片通信的FLASH控制逻辑。 FLASH控制逻辑包括用于基于与其耦合的闪速存储器芯片的类型配置FLASH数据总线的映射逻辑。 根据本发明的方法和系统提供以下优点:通过软件在FLASH存储器控制器上配置数据总线,以简化路由复杂度。 可配置芯片选择和控制总线,实现闪存放置的灵活性。 消除外部电阻网络进行布局简化。 用于更高数据总线带宽支持的可扩展架构。 自动检测闪存类型和容量配置。