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    • 2. 发明授权
      US5665632A Stress relaxation in dielectric before metalization 失效
    • Stress relaxation in dielectric before metalization
    • 金属化前电介质的应力松弛
    • US5665632A
    • 1997-09-09
    • US608071
    • 1996-02-28
    • Water Lur , Edward Houn
    • Water Lur , Edward Houn
    • H01L21/308 , H01L21/311 , H01L21/336 , H01L21/762 , H01L21/763 , H01L21/31 , H01L21/764
    • H01L29/6659 , H01L21/3086 , H01L21/31144 , H01L21/76229 , H01L21/763 , H01L29/6656 , Y10S148/073 , Y10S257/90 , Y10S438/938
    • A new method of trench isolation incorporating thermal stress releasing voids is described. Two sets of narrow trenches are etched into the silicon substrate not covered by a photoresist mask wherein the second set of trenches alternate with the first set of trenches. The first set of trenches is filled with an insulating layer. A second insulating layer is deposited over the surface of the substrate and within the second set of trenches wherein said insulating layer has step coverage such that voids are formed and are completely enclosed within the second set of trenches completing the thermal stress releasing device isolation of the integrated circuit. The method of forming thermal stress released polysilicon gate spacers in an integrated circuit is described. Polysilicon gate electrodes are formed on the surface of the semiconductor substrate. Sucessive sidewalls are formed on the gate electrodes of thin silicon dioxide, silicon nitride, and silicon dioxide. The silicon nitride spacers are removed leaving trenches between the thin silicon dioxide sidewalls and the silicon dioxide spacers. A thin insulating material is deposited over the surface of the gate electrodes and the sidewalls with a step coverage such that the trenches between the thin oxidation and the silicon dioxide spacers are not filled by the thin insulating layer but are covered by the thin insulating layer leaving voids which complete the thermal stress released polysilicon gate spacer formation in the fabrication of an integrated circuit.
    • 描述了一种结合热应力释放空隙的新型沟槽隔离方法。 将两组窄沟槽蚀刻到未被光致抗蚀剂掩模覆盖的硅衬底中，其中第二组沟槽与第一组沟槽交替。 第一组沟槽填充有绝缘层。 第二绝缘层沉积在衬底的表面上并在第二组沟槽内，其中所述绝缘层具有阶梯覆盖，使得形成空隙并完全封闭在第二组沟槽内，从而完成热应力释放装置的隔离 集成电路。 描述了在集成电路中形成热应力释放多晶硅栅极间隔物的方法。 多晶硅栅电极形成在半导体衬底的表面上。 在薄二氧化硅，氮化硅和二氧化硅的栅电极上形成过多的侧壁。 去除氮化硅间隔物，留下薄二氧化硅侧壁和二氧化硅间隔物之间​​的沟槽。 薄的绝缘材料沉积在栅电极和侧壁的表面上，具有台阶覆盖，使得薄氧化物和二氧化硅间隔物之间​​的沟槽不被薄绝缘层填充，但被薄绝缘层覆盖，离开 完成热应力的空隙在集成电路的制造中释放多晶硅栅极间隔物的形成。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 5. 发明授权
      US5516720A Stress relaxation in dielectric before metallization 失效
    • Stress relaxation in dielectric before metallization
    • 金属化前电介质的应力松弛
    • US5516720A
    • 1996-05-14
    • US195090
    • 1994-02-14
    • Water Lur , Edward Houn
    • Water Lur , Edward Houn
    • H01L21/308 , H01L21/311 , H01L21/336 , H01L21/762 , H01L21/763 , H01L21/31
    • H01L29/6659 , H01L21/3086 , H01L21/31144 , H01L21/76229 , H01L21/763 , H01L29/6656 , Y10S148/073 , Y10S257/90 , Y10S438/938
    • A new method of trench isolation incorporating thermal stress releasing voids is described. Two sets of narrow trenches are etched into the silicon substrate not covered by a photoresist mask wherein the second set of trenches alternate with the first set of trenches. The first set of trenches is filled with an insulating layer. A second insulating layer is deposited over the surface of the substrate and within the second set of trenches wherein said insulating layer has step coverage such that voids are formed and are completely enclosed within the second set of trenches completing the thermal stress releasing device isolation of the integrated circuit. The method of forming thermal stress released polysilicon gate spacers in an integrated circuit is described. Polysilicon gate electrodes are formed on the surface of the semiconductor substrate. Successive sidewalls are formed on the gate electrodes of thin silicon dioxide, silicon nitride, and silicon dioxide. The silicon nitride spacers are removed leaving trenches between the thin silicon dioxide sidewalls and the silicon dioxide spacers. A thin insulating material is deposited over the surface of the gate electrodes and the sidewalls with a step coverage such that the trenches between the thin oxidation and the silicon dioxide spacers are not filled by the thin insulating layer but are covered by the thin insulating layer leaving voids which complete the thermal stress released polysilicon gate spacer formation in the fabrication of an integrated circuit.
    • 描述了一种结合热应力释放空隙的新型沟槽隔离方法。 将两组窄沟槽蚀刻到未被光致抗蚀剂掩模覆盖的硅衬底中，其中第二组沟槽与第一组沟槽交替。 第一组沟槽填充有绝缘层。 第二绝缘层沉积在衬底的表面上并在第二组沟槽内，其中所述绝缘层具有阶梯覆盖，使得形成空隙并完全封闭在第二组沟槽内，从而完成热应力释放装置的隔离 集成电路。 描述了在集成电路中形成热应力释放多晶硅栅极间隔物的方法。 多晶硅栅电极形成在半导体衬底的表面上。 在薄二氧化硅，氮化硅和二氧化硅的栅电极上形成连续的侧壁。 去除氮化硅间隔物，留下薄二氧化硅侧壁和二氧化硅间隔物之间​​的沟槽。 薄的绝缘材料沉积在栅电极和侧壁的表面上，具有台阶覆盖，使得薄氧化物和二氧化硅间隔物之间​​的沟槽不被薄绝缘层填充，但被薄绝缘层覆盖，离开 完成热应力的空隙在集成电路的制造中释放多晶硅栅极间隔物的形成。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 7. 发明授权
      US5661049A Stress relaxation in dielectric before metallization 失效
    • Stress relaxation in dielectric before metallization
    • 金属化前电介质的应力松弛
    • US5661049A
    • 1997-08-26
    • US609256
    • 1996-02-29
    • Water Lur , Edward Houn
    • Water Lur , Edward Houn
    • H01L21/308 , H01L21/311 , H01L21/336 , H01L21/762 , H01L21/763
    • H01L29/6659 , H01L21/3086 , H01L21/31144 , H01L21/76229 , H01L21/763 , H01L29/6656 , Y10S148/073 , Y10S257/90 , Y10S438/938
    • A new method of trench isolation incorporating thermal stress releasing voids is described. Two sets of narrow trenches are etched into the silicon substrate not covered by a photoresist mask wherein the second set of trenches alternate with the first set of trenches. The first set of trenches is filled with an insulating layer. A second insulating layer is deposited over the surface of the substrate and within the second set of trenches wherein said insulating layer has step coverage such that voids are formed and are completely enclosed within the second set of trenches completing the thermal stress releasing device isolation of the integrated circuit. The method of forming thermal stress released polysilicon gate spacers in an integrated circuit is described. Polysilicon gate electrodes are formed on the surface of the semiconductor substrate. Sucessive sidewalls are formed on the gate electrodes of thin silicon dioxide, silicon nitride, and silicon dioxide. The silicon nitride spacers are removed leaving trenches between the thin silicon dioxide sidewalls and the silicon dioxide spacers. A thin insulating material is deposited over the surface of the gate electrodes and the sidewalls with a step coverage such that the trenches between the thin oxidation and the silicon dioxide spacers are not filled by the thin insulating layer but are covered by the thin insulating layer leaving voids which complete the thermal stress released polysilicon gate spacer formation in the fabrication of an integrated circuit.
    • 描述了一种结合热应力释放空隙的新型沟槽隔离方法。 将两组窄沟槽蚀刻到未被光致抗蚀剂掩模覆盖的硅衬底中，其中第二组沟槽与第一组沟槽交替。 第一组沟槽填充有绝缘层。 第二绝缘层沉积在衬底的表面上并在第二组沟槽内，其中所述绝缘层具有阶梯覆盖，使得形成空隙并完全封闭在第二组沟槽内，从而完成热应力释放装置的隔离 集成电路。 描述了在集成电路中形成热应力释放多晶硅栅极间隔物的方法。 多晶硅栅电极形成在半导体衬底的表面上。 在薄二氧化硅，氮化硅和二氧化硅的栅电极上形成过多的侧壁。 去除氮化硅间隔物，留下薄二氧化硅侧壁和二氧化硅间隔物之间​​的沟槽。 薄的绝缘材料沉积在栅电极和侧壁的表面上，具有台阶覆盖，使得薄氧化物和二氧化硅间隔物之间​​的沟槽不被薄绝缘层填充，但被薄绝缘层覆盖，离开 完成热应力的空隙在集成电路的制造中释放多晶硅栅极间隔物的形成。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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