专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09952879B2 Application pre-layout in byte-addressable persistent random access memory 有权
公开(公告)号：US09952879B2
公开(公告)日：2018-04-24
申请号：US13598616
申请日：2012-08-30
申请人： Edmund Nightingale , Ky Srinivasan
发明人： Edmund Nightingale , Ky Srinivasan
IPC分类号： G06F9/00 , G06F9/24 , G06F15/177 , G06F9/44 , G06F9/445
CPC分类号： G06F9/4406 , G06F9/44573
摘要： A software layout system is described herein that speeds up computer system boot time and/or application initialization time by moving constant data and executable code into byte-addressable, persistent random access memory (BPRAM). The system determines which components and aspects of the operating system or application change infrequently. From this information, the system builds a high performance BPRAM cache to provide faster access to these frequently used components, including the kernel. The result is that kernel or application code and data structures have a high performance access and execution time with regard to memory fetches. Thus, the software layout system provides a faster way to prepare operating systems and applications for normal operation and reduces the time spent on initialization.

2. 发明授权

US08954660B2 Execute-in-place mode configuration for serial non-volatile memory 有权
标题翻译：串行非易失性存储器的就地模式配置
公开(公告)号：US08954660B2
公开(公告)日：2015-02-10
申请号：US14149624
申请日：2014-01-07
申请人： Micron Technology, Inc.
发明人： Paolo Rolandi , Sandra Lospalluti , Raffaele Bufano , Stefano Andreoli , Tommaso Zerilli
IPC分类号： G06F12/00 , G06F12/02 , G11C16/26
CPC分类号： G06F12/0246 , G06F9/30098 , G06F9/44573 , G06F2212/72 , G06F2212/7206 , G11C16/26 , G11C2216/30
摘要： Example embodiments for configuring a serial non-volatile memory device for an execute-in-place mode may comprise a non-volatile configuration register to store an execute-in-place mode value that may be read at least in part in response to power being applied to the memory device.
摘要翻译：用于配置用于就地执行模式的串行非易失性存储器件的示例性实施例可以包括非易失性配置寄存器，用于存储至少部分地响应于功率而被读取的就地执行模式值应用于存储器件。

3. 发明授权

US08626990B2 Non-volatile configuration for serial non-volatile memory 有权
标题翻译：用于串行非易失性存储器的非易失性配置
公开(公告)号：US08626990B2
公开(公告)日：2014-01-07
申请号：US13143075
申请日：2008-12-30
申请人： Paolo Rolandi , Sandra Lospalluti , Raffaele Bufano , Stefano Andreoli , Tommaso Zerilli
发明人： Paolo Rolandi , Sandra Lospalluti , Raffaele Bufano , Stefano Andreoli , Tommaso Zerilli
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F9/44573 , G06F2212/72 , G11C16/10 , G11C16/20
摘要： Example embodiments for configuring a serial non-volatile memory device may comprise a non-volatile configuration register to store a configuration value received from the processor, the configuration value to specify one or more attributes of a memory access operation. The configuration value may be read at least in part in response to power being applied to the memory device.
摘要翻译：用于配置串行非易失性存储器设备的示例性实施例可以包括用于存储从处理器接收的配置值的非易失性配置寄存器，该配置值指定存储器访问操作的一个或多个属性。至少部分地响应于施加到存储器件的功率来读取配置值。

4. 发明申请

US20130275659A1 ELECTRONIC DEVICES 有权
标题翻译：电子设备
公开(公告)号：US20130275659A1
公开(公告)日：2013-10-17
申请号：US13819304
申请日：2011-08-26
申请人： Thomas Langas , Asbjorn Djupdal , Borgar Ljosland , Torstein Hernes Dybdahl
发明人： Thomas Langas , Asbjorn Djupdal , Borgar Ljosland , Torstein Hernes Dybdahl
IPC分类号： G06F3/06
CPC分类号： H04L67/1097 , G06F3/0605 , G06F3/061 , G06F3/0643 , G06F3/0655 , G06F3/0664 , G06F3/0667 , G06F3/0671 , G06F3/0679 , G06F3/0688 , G06F9/44573 , G06F9/44584 , G06F9/547 , G06F13/10 , G06F13/102 , G06F13/28 , G06F13/364 , G06F13/385 , G06F13/4282 , G06F21/575 , G06F21/6218 , H04L29/08549 , H04L67/42 , Y02D10/14 , Y02D10/151
摘要： A storage device (3), such as an SD card, that is coupled to a host device (2), such as a mobile phone, includes a computing environment (8). The computing environment (8) includes an application processing part (6), and a separate interface processing part (7). The application processing part (6) of the computing environment 8 is operable to execute one or more applications on the storage device (3). The interface processing part (7) of the computing environment 8 includes an interface processor that interfaces between a communications protocol used between the host device (2) and the storage device (3), and a communications protocol used by the application processor in the application processing part (6) of the storage device (3). The interface processor communicates with the application processor via interrupts and a shared memory (9).
摘要翻译：耦合到诸如移动电话的主机设备（2）的诸如SD卡的存储设备（3）包括计算环境（8）。计算环境（8）包括应用处理部分（6）和单独的接口处理部分（7）。计算环境8的应用处理部分（6）可操作以在存储设备（3）上执行一个或多个应用。计算环境8的接口处理部分（7）包括在主机设备（2）和存储设备（3）之间使用的通信协议之间进行接口的接口处理器和应用处理器在应用中使用的通信协议处理部分（6）。接口处理器经由中断和共享存储器（9）与应用处理器通信。

5. 发明授权

US08065563B2 System for booting from a non-XIP memory utilizing a boot engine that does not have ECC capabilities during booting 有权
标题翻译：使用在引导期间不具有ECC能力的引导引擎从非XIP内存引导的系统
公开(公告)号：US08065563B2
公开(公告)日：2011-11-22
申请号：US12470487
申请日：2009-05-22
申请人： Ming-Shiang Lai
发明人： Ming-Shiang Lai
IPC分类号： G06F11/00
CPC分类号： G06F9/4401 , G06F9/44573 , G06F11/1417 , G06F11/1666
摘要： A booting system includes: a non-XIP memory, for storing a plurality of booting images, wherein the booting images comprise a source image and a plurality of duplicates of the source image; an XIP memory, coupled to the non-XIP memory; and a code shadowing module, coupled to the non-XIP memory and the XIP memory, for shadowing a specific booting image to the XIP memory if no errors are detected when carrying out error detection (EDC) checking on the specific booting image; wherein if at least a specific part of a booting image does not pass EDC checking, the code shadowing module shadows error-free parts of the booting image to the XIP memory, carries out EDC checking on at least a duplicate of the specific part, and then shadows an error-free part corresponding to the specific part to the XIP memory.
摘要翻译：引导系统包括：非XIP存储器，用于存储多个启动图像，其中引导图像包括源图像和源图像的多个重复; 耦合到非XIP存储器的XIP存储器; 以及耦合到非XIP存储器和XIP存储器的代码阴影模块，用于在对特定引导映像进行错误检测（EDC）检查时没有检测到错误时将特定引导映像遮蔽到XIP存储器; 其中如果引导图像的至少特定部分没有通过EDC检查，则代码阴影模块将引导图像的无错误部分影响到XIP存储器，对至少特定部分的副本执行EDC检查，以及然后将对应于XIP存储器的特定部分的无错误部分影像。

6. 发明授权

US07904897B2 Executing applications from a semiconductor nonvolatile memory 有权
标题翻译：从半导体非易失性存储器执行应用程序
公开(公告)号：US07904897B2
公开(公告)日：2011-03-08
申请号：US10215549
申请日：2002-08-08
申请人： John C. Rudelic
发明人： John C. Rudelic
IPC分类号： G06F9/44
CPC分类号： G06F9/44573
摘要： A processor-based device (e.g., a wireless device) may include a processor and a semiconductor nonvolatile memory to directly execute an application (e.g., an execute-in-place application) using an associated database. Within a flash memory, in one embodiment, an executable program may be separately stored in a non-fragmented manner from a resident database that includes program management information for use in an execution that does not involve a random access memory, saving time and resources.
摘要翻译：基于处理器的设备（例如，无线设备）可以包括处理器和半导体非易失性存储器，以使用相关数据库直接执行应用（例如，就地应用程序）。在闪速存储器中，在一个实施例中，可执行程序可以从包括用于不涉及随机存取存储器的执行中使用的程序管理信息的驻留数据库以非分段方式存储，从而节省时间和资源。

7. 发明申请

US20100318712A1 SYSTEM AND METHOD FOR DISTRIBUTED PERSISTENT COMPUTING PLATFORM 有权
标题翻译：分布式计算平台的系统和方法
公开(公告)号：US20100318712A1
公开(公告)日：2010-12-16
申请号：US12484801
申请日：2009-06-15
申请人： Sergey BOLDYREV , Jarmo ARPONEN , Antti LAPPETELAINEN
发明人： Sergey BOLDYREV , Jarmo ARPONEN , Antti LAPPETELAINEN
IPC分类号： G06F13/28
CPC分类号： G06F9/44573
摘要： Example embodiments of the invention are disclosed for an adaptive computing platform wherein a reader/writer device uses distributed, external memory resources as non-volatile memory blocks to provide distributed execution-in-place capability for the reader/writer device, such as a mobile phone, to enhance the processing power of the device. The execution architecture of the reader/writer device is scalable and adaptive to accommodate variations in the speed, size, and other characteristics of different external memory blocks it uses as it moves from one external memory block to another.
摘要翻译：公开了用于自适应计算平台的自适应计算平台的示例实施例，其中读/写器设备使用分布式外部存储器资源作为非易失性存储器块来为读/写器设备提供分布式执行就绪能力，诸如移动手机，提升设备的处理能力。读/写器设备的执行架构是可扩展的和自适应的，以适应其从一个外部存储器块移动到另一个外部存储器块时使用的不同外部存储器块的速度，大小和其他特性的变化。

8. 发明授权

US07386653B2 Flash memory arrangement 有权
标题翻译：闪存安排
公开(公告)号：US07386653B2
公开(公告)日：2008-06-10
申请号：US09922153
申请日：2001-08-06
申请人： Dov Moran
发明人： Dov Moran
IPC分类号： G06F13/00 , G06F9/445
CPC分类号： G06F9/4406 , G06F9/4403 , G06F9/44573
摘要： A device, a method and a system for direct execution of code from a flash memory arrangement, in which a separate memory component is not required, even if a flash memory component is used which has a restriction on the size of a data block which can be read at one time. Furthermore, the flash memory arrangement is optionally implemented as a “single die” chip or device, which is more efficient for manufacturing and which also results in lower costs.
摘要翻译：即使使用对可对数据块的大小有限制的闪速存储器组件，也不需要单独的存储器组件的用于从闪速存储器装置直接执行代码的装置，方法和系统一次阅读此外，闪速存储器布置可选地被实现为“单芯片”芯片或器件，其对于制造更有效，并且还导致较低的成本。

9. 发明申请

US20080126749A1 USING SHARED MEMORY WITH AN EXECUTE-IN-PLACE PROCESSOR AND A CO-PROCESSOR 有权
标题翻译：使用共享存储器与执行处理器和协处理器
公开(公告)号：US20080126749A1
公开(公告)日：2008-05-29
申请号：US11557439
申请日：2006-11-07
申请人： Joe Y. Tom , Venkat Natarajan
发明人： Joe Y. Tom , Venkat Natarajan
IPC分类号： G06F12/00 , G06F12/02 , G06F9/44
CPC分类号： G06F12/1416 , G06F9/44573 , G06F12/1408 , G06F21/85
摘要： The claimed subject matter provides systems and/or methods that facilitate sharing of a memory, having a single channel of access, between two or more processors. A host processor can be operatively connected to a co-processor and the memory in series. The host processor can execute in place to enable it to execute code directly from the memory, and can arbitrate access to the memory bus and thus the memory, so that the host processor can perform all memory fetches to the memory without interruption by the co-processor. The co-processor can be implemented as a finite state machine, and only accesses the memory during read or write cycles issued by the host processor. Various types of co-processors can be employed to perform various functions, such as cryptography and digital signal processing, for example. The memory can be volatile or non-volatile memory.
摘要翻译：所要求保护的主题提供了便于在两个或多个处理器之间共享具有单一访问通道的存储器的系统和/或方法。主机处理器可以可操作地连接到协处理器和串行存储器。主处理器可以执行到位以使其能够直接从存储器执行代码，并且可以仲裁对存储器总线的访问，从而对存储器进行仲裁，使得主机处理器可以执行所有存储器提取到存储器，处理器。协处理器可以被实现为有限状态机，并且仅在由主处理器发出的读或写周期期间访问存储器。可以使用各种类型的协处理器来执行各种功能，例如密码学和数字信号处理。内存可以是易失性或非易失性存储器。

10. 发明申请

US20070076475A1 SYSTEM AND METHOD FOR EXECUTING BINARY IMAGES 审中-公开
标题翻译：用于执行二进制图像的系统和方法
公开(公告)号：US20070076475A1
公开(公告)日：2007-04-05
申请号：US11539849
申请日：2006-10-09
申请人： Michael Malueg , Larry Morris , Bor-Ming Hsieh , Yadhu Gopalan
发明人： Michael Malueg , Larry Morris , Bor-Ming Hsieh , Yadhu Gopalan
IPC分类号： G11C16/04
CPC分类号： G06F9/44573
摘要： A system that determines where a particular XIP component is stored on a medium and loads the component into RAM for execution, providing the ability to demand page specific components at will from storage media, frees up working RAM on memory constrained devices. A Binary File System uses a generic block driver component that loads the XIP code from a block based storage medium. Features of the file system include the ability to load pre-“fixed up” components from a block based device.. The invention thus allows an operating system to load code that was previously Executed In Place (XIP) from a block-oriented device.
摘要翻译：确定特定XIP组件在介质上的存储位置并将组件加载到RAM中以执行的系统，提供从存储介质随意请求页面特定组件的能力，释放存储器受限设备上的工作RAM。二进制文件系统使用从基于块的存储介质加载XIP代码的通用块驱动程序组件。文件系统的特征包括从基于块的设备加载预“固定”组件的能力。因此，本发明允许操作系统从面向块的设备加载先前执行的（XIP）的代码。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式