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1. 发明授权

US5461721A System for transferring data between I/O devices and main or expanded storage under dynamic control of independent indirect address words (IDAWs) 失效
标题翻译：用于在独立间接地址字（IDAW）的动态控制下在I / O设备与主或扩展存储之间传输数据的系统
公开(公告)号：US5461721A
公开(公告)日：1995-10-24
申请号：US46679
申请日：1993-04-14
申请人： Roger L. Cormier , Robert J. Dugan , Kenneth J. Fredericks , Peter H. Gum , Moon J. Kim , Allen H. Preston , Richard J. Schmalz, deceased , Charles F. Webb , Leslie W. Wyman
发明人： Roger L. Cormier , Robert J. Dugan , Kenneth J. Fredericks , Peter H. Gum , Moon J. Kim , Allen H. Preston , Richard J. Schmalz, deceased , Charles F. Webb , Leslie W. Wyman
IPC分类号： G06F12/08 , G06F12/10 , G06F13/12
CPC分类号： G06F13/122 , G06F12/08 , G06F12/10
摘要： Enables an I/O channel program to use IDAWs (indirect data address words) to control data transfers from/to an I/O (input/output) device to/from either or both of ES (expanded storage) and/or system MS (main storage), in which data moved to/from ES does not move through MS. ES and MS are plural electronic storage media in a data processing system, and the I/O device is any I/O device selectable by the system. Intermixing of data transfers between ES and MS may be controlled by a single IDAW list accessed by a channel control word (CCW) in a channel program in a data transfer direction indicated in the CCW without any channel mode change.
摘要翻译：启用I / O通道程序以使用IDAW（间接数据地址字）来控制从I / O（输入/输出）设备到/从ES（扩展存储）和/或系统MS之一或两者的数据传输（主存储），其中移动到/从ES的数据不通过MS移动。 ES和MS是数据处理系统中的多个电子存储介质，I / O设备是可由系统选择的任何I / O设备。在ES和MS之间的数据传输的混合可以由在CCW中指示的数据传送方向上的信道程序中由信道控制字（CCW）访问的单个IDAW列表来控制，而没有任何信道模式改变。

2. 发明授权

US5222215A CPU expansive gradation of I/O interruption subclass recognition 失效
标题翻译： CPU扩展I / O中断SUBCLASS识别
公开(公告)号：US5222215A
公开(公告)日：1993-06-22
申请号：US752149
申请日：1991-08-29
申请人： Norman C. Chou , Peter H. Gum , Roger E. Hough , Moon J. Kim , James C. Mazurowski , Donald W. McCauley , Casper A. Scalzi , John F. Scanlon , Leslie W. Wyman
发明人： Norman C. Chou , Peter H. Gum , Roger E. Hough , Moon J. Kim , James C. Mazurowski , Donald W. McCauley , Casper A. Scalzi , John F. Scanlon , Leslie W. Wyman
IPC分类号： G06F9/46 , G06F9/48
CPC分类号： G06F9/4812
摘要： A CPU interface recognizing a large very number of I/O interruption queues in a logically partitioned data processing system. Different partitions may contain different guest operating systems. The CPU interface controls how plural CPUs respond to I/O interruptions put on numerous hardware-controlled queues. A host hypervisor program dispatches the guest operating systems. The guests use the I/O interruptions in controlling the dispatching of their programs on the CPUs in a system. The invention allows the number of guest partitions in the system to exceed the number of I/O interruption subclasses (ISCs) architected in the system, and enables the dispatching controls of each guest operating system to be sensitive to different priorities for plural programs operating under a respective guest. The invention provides CPU controls that support alerting the host to enabled I/O interruptions, and provides CPU controlled pass-through for enabling direct guest handling of the guests I/O interruptions.

3. 发明授权

US4843541A Logical resource partitioning of a data processing system 失效
标题翻译：数据处理系统的逻辑资源划分
公开(公告)号：US4843541A
公开(公告)日：1989-06-27
申请号：US79314
申请日：1987-07-29
申请人： George H. Bean , Terry L. Borden , Mark S. Farrell , Peter H. Gum , Roger E. Hough , Francis E. Johnson , Donald W. McCauley , Mark E. Rakhmilevich , John C. Rathjen , Casper A. Scalzi , John F. Scanlon , Leslie W. Wyman
发明人： George H. Bean , Terry L. Borden , Mark S. Farrell , Peter H. Gum , Roger E. Hough , Francis E. Johnson , Donald W. McCauley , Mark E. Rakhmilevich , John C. Rathjen , Casper A. Scalzi , John F. Scanlon , Leslie W. Wyman
IPC分类号： G06F9/46 , G06F9/48 , G06F9/50 , G06F12/10
CPC分类号： G06F9/4843 , G06F9/5077
摘要： The embodiment discloses a method and means for partitioning the resources in a data processing system into a plurality of logical partitions. Host control code may be embodied in programming, microcode, or by special hardware to enable highly efficient operation of a plurality of preferred guest programming systems in the different partitions of the system. The main storage, expanded storage, the channel, and subchannel resources of a system are assigned to the different logical partitions in the system to enable a plurality of preferred guest programming systems to run simultaneously in the different partitions. This invention automatically relocates the absolute addresses of the I/O channel and subchannel resources in the system to their assigned partitions. Also the absolute and virtual addresses of the different guest programming systems are relocated into, as well as page addresses for any expanded storage, their assigned partitions. The guest programming systems generally will be different operating systems. The logical CPU(s) of the guests are dispatched on one or plural real CPUs in the system using the S/370XA SIE (start interpretive execution) instruction. Special operations are provided, including the CPU alerting of other guests in different partitions using I/O interruption signalling. Interception is provided to handle special circumstances.

4. 发明授权

US5317705A Apparatus and method for TLB purge reduction in a multi-level machine system 失效
标题翻译：用于多级机器系统中TLB吹扫减少的装置和方法
公开(公告)号：US5317705A
公开(公告)日：1994-05-31
申请号：US112174
申请日：1993-08-26
申请人： Patrick M. Gannon , Peter H. Gum , Roger E. Hough , Robert E. Murray
发明人： Patrick M. Gannon , Peter H. Gum , Roger E. Hough , Robert E. Murray
IPC分类号： G06F12/10 , G06F12/02
CPC分类号： G06F12/1036
摘要： A system for reducing purging of a translation lookaside buffer (TLB) to reduce operating system overhead in a system running multiple levels of virtual machines. A system typically must purge TLB entries whenever an underlying page table entry is invalidated due to paging activity on the host machine, or an underlying guest machine. A system for reducing the number of cases in which guest translations are based on host page table entries is provided. Additional logic is supplied to analyze each invalidate page table entry (IPTE) instruction to minimize the extent of purging required as a result of that instruction. When the region relocate facility is in operation, or when no pageable TLB's have been constructed, only the entry corresponding to the page table entry to be invalidated need be purged. This limited purging reduces the overhead by reducing the time spent in purging and the time required in address translation to rebuild the TLB. This time saving results in increased performance in systems with multi-level guests.
摘要翻译：用于减少翻译后备缓冲器（TLB）的清除以减少运行多级虚拟机的系统中的操作系统开销的系统。由于主机或基础客机上的分页活动，每当基础页表项无效时，系统通常必须清除TLB条目。提供了一种用于减少客户转换基于主机页表项的情况的系统。提供附加逻辑来分析每个无效页表项（IPTE）指令，以最小化该指令所需的清除范围。当区域重新定位设施正在运行时，或者当没有构建可页面的TLB时，只需要清除与该页表项对应的条目即可。这种有限的清除通过减少清除时间和地址转换所需的时间来重建TLB来减少开销。节省时间可以提高具有多级客人的系统的性能。

5. 发明授权

US4494189A Method and means for switching system control of CPUs 失效
标题翻译：用于切换CPU系统控制的方法和装置
公开(公告)号：US4494189A
公开(公告)日：1985-01-15
申请号：US371754
申请日：1982-04-26
申请人： George H. Bean , Peter H. Gum
发明人： George H. Bean , Peter H. Gum
IPC分类号： G06F9/46 , G06F9/455 , G06F9/48
CPC分类号： G06F9/4843 , G06F9/45533
摘要： The embodiment obtains rapid switching between system control programs (SCPs) by switching an address in a prefix register in a CPU of a MP or UP data processing system from a guest SCP's PSA (program save area) to a host SCP's PSA by fetching the host prefix value from a predetermined control block in main storage. The prefix register loading changes the control of the CPU from a preferred guest SCP to a host SCP. This SCP switching is done by hardware and/or microcode means in the CPU. It further detects preset states in the CPU that enable a rapid determination of which SCP is to handle a sensed event, permitting the guest SCP to immediately handle events predetermined to belong to the guest. This manner of CPU control obtains for a preferred guest SCP (such as MVS/370) operating under a host SCP (such as VM/370) nearly the efficiency of standalone execution on the CPU by the preferred guest SCP.
摘要翻译：该实施例通过将MP或UP数据处理系统的CPU中的前缀寄存器中的地址从访客SCP的PSA（节目保存区域）切换到主机SCP的PSA，从而获得系统控制程序（SCP）之间的快速切换来自主存储器中的预定控制块的前缀值。前缀寄存器加载将CPU的控制从优选的客户SCP更改为主机SCP。该SCP切换由CPU中的硬件和/或微代码装置完成。它进一步检测CPU中的预设状态，使得能够快速确定哪个SCP处理感测到的事件，从而允许客人SCP立即处理预定属于客人的事件。这种CPU控制的方式获得在主机SCP（例如VM / 370）下操作的优选客户SCP（例如MVS / 370）几乎是优选客户SCP在CPU上独立执行的效率。

6. 发明授权

US5404563A Scheduling normally interchangeable facilities in multiprocessor computer systems 失效
标题翻译：在多处理器计算机系统中安排通常可互换的设施
公开(公告)号：US5404563A
公开(公告)日：1995-04-04
申请号：US181379
申请日：1994-01-14
申请人： Lucina L. Green , Peter H. Gum , Roger E. Hough , Sandra L. Rankin , Stephen J. Schmandt , Ronald M. Smith, Sr. , Vincent A. Spano , Phil C. Yeh , Devon S. Yu
发明人： Lucina L. Green , Peter H. Gum , Roger E. Hough , Sandra L. Rankin , Stephen J. Schmandt , Ronald M. Smith, Sr. , Vincent A. Spano , Phil C. Yeh , Devon S. Yu
IPC分类号： G06F9/48 , G06F9/00 , G06F11/20
CPC分类号： G06F9/4881
摘要： A system and method for dispatching logical central processing units (CPUs) among physical CPUs in a multiprocessor computer system having multiple logical partitions, wherein the cryptographic facilities may not be interchangeable. According to the present invention, the logical CPUs are dispatched among the physical CPUs according to either an affinity, floating, or disabled scheduling method. The affinity scheduling method is used when the crypto facilities are not interchangeable or when non-interchangeable crypto functions are performed. The floating scheduling method is used when the cryptographic facilities are interchangeable and interchangeable crypto functions are performed. The disabled scheduling method is used when the logical CPU is not authorized to issue cryptographic instructions.
摘要翻译：一种用于在具有多个逻辑分区的多处理器计算机系统中的物理CPU之间调度逻辑中央处理单元（CPU）的系统和方法，其中所述密码设施可能不可互换。根据本发明，根据亲和度，浮动或无效调度方法在物理CPU之间分派逻辑CPU。当密码设施不可互换或者当不可互换的密码功能被执行时，使用亲和度调度方法。当加密设施是可互换的并且可互换的密码功能被执行时，使用浮动调度方法。当逻辑CPU没有授权发布加密指令时，使用禁用的调度方法。

7. 发明授权

US5381535A Data processing control of second-level quest virtual machines without host intervention 失效
标题翻译：二级任务虚拟机的数据处理控制，无需主机干预
公开(公告)号：US5381535A
公开(公告)日：1995-01-10
申请号：US150332
申请日：1993-11-09
申请人： Peter H. Gum , Roger E. Hough , Robert E. Murray
发明人： Peter H. Gum , Roger E. Hough , Robert E. Murray
IPC分类号： G06F9/455 , G06F9/48 , G06F12/00
CPC分类号： G06F9/4843 , G06F9/45558 , G06F2009/45566
摘要： A data processing system operated with multiple levels of virtual machine guests under a host control program. The second level of guests are invoked, operated, and terminated without host intervention, as has been required in prior systems, to significantly increase the operating efficiency of the system. Address translation is done by providing machine capability to translate second level guest addresses to real memory addresses taking advantage of the first level guest being located at a simple offset within real memory. Special facilities for second level guests periodically test for timing interruptions for second level guests and update the second level guest timing facilities.
摘要翻译：一个数据处理系统，在主机控制程序下由多级虚拟机客户端操作。如先前的系统所要求，第二层次的客人被调用，操作和终止，无需主机干预，从而显着提高系统的运行效率。地址转换是通过提供机器能力来将二级客户地址转换为实际存储器地址，利用第一层客户端位于实际存储器内的简单偏移处。第二级客人的特别设施定期测试二级客人的时间间隔，并更新二级宾客时间设施。

8. 发明授权

US5426748A Guest/host extended addressing method and means with contiguous access list entries 失效
标题翻译：访客/主机具有连续访问列表条目的扩展寻址方法和方法
公开(公告)号：US5426748A
公开(公告)日：1995-06-20
申请号：US816911
申请日：1992-01-03
申请人： James G. Brenza , Joseph M. Gdaniec , Peter H. Gum , Kathryn M. Jackson , Mark M. Maccabee , Casper A. Scalzi , Bhaskar Sinha
发明人： James G. Brenza , Joseph M. Gdaniec , Peter H. Gum , Kathryn M. Jackson , Mark M. Maccabee , Casper A. Scalzi , Bhaskar Sinha
IPC分类号： G06F12/10 , G06F12/02 , G06F12/08
CPC分类号： G06F12/0292
摘要： An addressing method using large addresses in a guest/host environment within a computer system. The guests are operating-systems, and the host is a hypervisor program. Each guest has a guest real address space (guest RAS) mapped onto a host large real address space (host LRAS) using means disclosed herein. To do this, each guest RAS is first assigned to a contiguous part of a host large virtual address space (LVAS) by assigning each guest RAS to one or more contiguous units of virtual addressing in the host LVAS, each unit having a 2 gigabyte (GB) size. The host LVAS is represented by a sequence of entries (ALEs) in a host access list (AL), in which each ALE represents a 2 GB unit of virtual addressing in the host LVAS. An ALE is selected in the AL by using a high-order part of a host large virtual address (host LVA) representing a guest RA or LRA. A host LVA is generated from a guest RA for obtaining the guest address in host main storage. The host LVA is translated in a number of different ways to a host LRA, depending on the type of guest providing the corresponding guest RA or LRA. The guest types include V=V, V=FC, V=FD and V=R guests, which is indicated in a guest control block (GCB).
摘要翻译：在计算机系统内的访客/主机环境中使用大地址的寻址方法。客人是操作系统，主机是一个管理程序。每个访客都使用本文公开的手段将访客实际地址空间（客户RAS）映射到主机大型实际地址空间（主机LRAS）。为此，每个客户RAS首先通过将每个客户机RAS分配给主机LVAS中的一个或多个连续的虚拟寻址单元来分配给主机大型虚拟地址空间（LVAS）的连续部分，每个单元具有2GB（ GB）尺寸。主机LVAS由主机访问列表（AL）中的一系列条目（ALE）表示，其中每个ALE表示主机LVAS中的2GB虚拟寻址单元。通过使用表示客户RA或LRA的主机大型虚拟地址（主机LVA）的高阶部分，在AL中选择ALE。从客户RA生成主机LVA以获得主机主存储器中的客户地址。主机LVA根据提供相应客户RA或LRA的客户端类型，以多种不同的方式被转换到主机LRA。客人类型包括V = V，V = FC，V = FD和V = R客人，在客人控制块（GCB）中指示。

9. 发明授权

US4779188A Selective guest system purge control 失效
标题翻译：选择性客系统清洗控制
公开(公告)号：US4779188A
公开(公告)日：1988-10-18
申请号：US110620
申请日：1987-10-19
申请人： Peter H. Gum , Roger E. Hough , Peter H. Tallman , Thomas O. Curlee, III
发明人： Peter H. Gum , Roger E. Hough , Peter H. Tallman , Thomas O. Curlee, III
IPC分类号： G06F9/455 , G06F9/48 , G06F12/10 , G06F9/44 , G06F9/32
CPC分类号： G06F9/4843 , G06F12/1027 , G06F9/45558 , G06F2009/45579 , G06F2009/45583 , G06F2212/682
摘要： The embodiments enable address translations for a virtual machine in the TLB (translation lookaside buffer) of a CPU to be retained from exiting a SIE (start interpretive execution) instruction to the next SIE entry to interpretive execution for the same guest (virtual machine CPU). Conditions are defined which determine when guest TLB entries must be invalidated. These conditions require invalidation of guest TLB entries only within and on entry to interpretive execution. A single invalidation of guest TLB entries on entry to interpretive execution is required for any number of conditions recognized while a CPU is not in interpretive execution state. For a guest in a virtual multi-processor (MP) machine, an interlock is provided to allow the use of guest virtual addresses by host instruction simulation and the need for guest TLB invalidation is broadcast to all other real CPUs in a real MP system so that all guest TLBs on all real CPUs can be invalidated to maintain integrity. No broadcast or interlock is needed for a guest in a virtual uni-processor (UP) machine.
摘要翻译：这些实施例使得要保留的待保留的CPU的TLB（转换后备缓冲器）中的虚拟机的地址转换不会从SIE（开始解释执行）指令移除到下一个SIE条目以解释相同来宾（虚拟机CPU）的执行。定义条件是确定何时必须使客户端TLB条目无效。这些条件仅在客户TLB条目中无效，仅在解释执行过程中和之后才进行。在CPU不处于解释执行状态时，对于识别的任何数量的条件，需要对进入解释执行的客户TLB条目单一无效。对于虚拟多处理器（MP）机器中的客人，提供互锁以允许通过主机指令模拟使用来宾虚拟地址，并且将客户TLB无效的需求广播到真实MP系统中的所有其他真实CPU，因此所有实际CPU上的所有客户端TLB都可以无效以保持完整性。虚拟单处理器（UP）机器中的客人不需要广播或互锁。

10. 发明授权

US4598364A Efficient trace method adaptable to multiprocessors 失效
标题翻译：高效跟踪方法适用于多处理器
公开(公告)号：US4598364A
公开(公告)日：1986-07-01
申请号：US509129
申请日：1983-06-29
申请人： Peter H. Gum , Arthur L. Levin , Ronald M. Smith , John H. Wilson
发明人： Peter H. Gum , Arthur L. Levin , Ronald M. Smith , John H. Wilson
IPC分类号： G06F11/28 , G06F11/36 , G06F15/16 , G06F15/177 , G06F11/30
CPC分类号： G06F11/3636
摘要： The disclosure describes a separate trace table for each CPU in an MP to avoid inter-CPU interference in making trace table entries for explicit and implicit tracing instructions enabled by flag bits in a control register (CR). Explicit tracing entries are made for an enabled explicit tracing instruction. Implicit tracing entries are made for predetermined instructions (when enabled for tracing) which do not have tracing as their primary purpose. A storage operand of the trace instruction contains a disablement field and optionally may contain an enablement-controlling class field to improve the integrity of traceable programs. A time stamp and range of general register contents is provided in each trace table entry for a tracing instruction. The time stamp enables all trace tables in an MP system to be later merged into a single trace table whenever required.
摘要翻译：本公开描述了MP中的每个CPU的单独跟踪表，以避免CPU间干扰，从而为通过控制寄存器（CR）中的标志位使能的显式和隐式跟踪指令进行跟踪表条目。显式跟踪条目用于启用的显式跟踪指令。针对不具有追踪作为主要目的的预定指令（当跟踪启用时）进行隐式跟踪条目。跟踪指令的存储操作数包含禁用字段，并且可选地可以包含启用控制类字段以提高可跟踪程序的完整性。在跟踪指令的每个跟踪表条目中提供时间戳和通用寄存器内容的范围。时间戳使MP系统中的所有跟踪表稍后在需要时合并到单个跟踪表中。

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