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1. 发明授权

US5222215A CPU expansive gradation of I/O interruption subclass recognition 失效
标题翻译： CPU扩展I / O中断SUBCLASS识别
公开(公告)号：US5222215A
公开(公告)日：1993-06-22
申请号：US752149
申请日：1991-08-29
申请人： Norman C. Chou , Peter H. Gum , Roger E. Hough , Moon J. Kim , James C. Mazurowski , Donald W. McCauley , Casper A. Scalzi , John F. Scanlon , Leslie W. Wyman
发明人： Norman C. Chou , Peter H. Gum , Roger E. Hough , Moon J. Kim , James C. Mazurowski , Donald W. McCauley , Casper A. Scalzi , John F. Scanlon , Leslie W. Wyman
IPC分类号： G06F9/46 , G06F9/48
CPC分类号： G06F9/4812
摘要： A CPU interface recognizing a large very number of I/O interruption queues in a logically partitioned data processing system. Different partitions may contain different guest operating systems. The CPU interface controls how plural CPUs respond to I/O interruptions put on numerous hardware-controlled queues. A host hypervisor program dispatches the guest operating systems. The guests use the I/O interruptions in controlling the dispatching of their programs on the CPUs in a system. The invention allows the number of guest partitions in the system to exceed the number of I/O interruption subclasses (ISCs) architected in the system, and enables the dispatching controls of each guest operating system to be sensitive to different priorities for plural programs operating under a respective guest. The invention provides CPU controls that support alerting the host to enabled I/O interruptions, and provides CPU controlled pass-through for enabling direct guest handling of the guests I/O interruptions.

2. 发明授权

US07111101B1 Method and system for port numbering in an interconnect device 有权
标题翻译：互连设备中端口编号的方法和系统
公开(公告)号：US07111101B1
公开(公告)日：2006-09-19
申请号：US10431993
申请日：2003-05-07
申请人： Daniel Bourke , Prasad Vajjhala , Norman C. Chou
发明人： Daniel Bourke , Prasad Vajjhala , Norman C. Chou
IPC分类号： G06F13/14
CPC分类号： H04L49/101 , H04L49/201 , H04L49/253 , H04L49/254 , H04L49/3009 , H04L49/358
摘要： A method of port numbering in an interconnect device includes loading a port configuration value from a memory device. One or more ports and subports are enabled according to the configuration value. Contiguous logical port numbers are assigned to the one or more ports and subports included in the interconnect device. A mapping request is received; and a mapped response associated with the mapping request is provided to an entity.
摘要翻译：在互连设备中的端口编号的方法包括从存储设备加载端口配置值。根据配置值启用一个或多个端口和子端口。相邻的逻辑端口号分配给互连设备中包含的一个或多个端口和子端口。接收到映射请求; 并且将与映射请求相关联的映射响应提供给实体。

3. 发明授权

US07043569B1 Method and system for configuring an interconnect device 失效
标题翻译：用于配置互连设备的方法和系统
公开(公告)号：US07043569B1
公开(公告)日：2006-05-09
申请号：US09948924
申请日：2001-09-07
申请人： Norman C. Chou , Prasad Vajjhala , Richard Schober , Laura Randall , Ian G. Collof
发明人： Norman C. Chou , Prasad Vajjhala , Richard Schober , Laura Randall , Ian G. Collof
IPC分类号： G06F3/00
CPC分类号： G06F13/4031
摘要： In one embodiment, a system for configuring an interconnect device includes a non-volatile storage device to store configuration data associated with the interconnect device and a configuration interface to request the configuration data from the non-volatile storage device. Further, the system includes an initialization module to query the configuration interface for the configuration data and to distribute the configuration data provided by the configuration interface to multiple units within the interconnect device.
摘要翻译：在一个实施例中，用于配置互连设备的系统包括用于存储与互连设备相关联的配置数据的非易失性存储设备和用于从非易失性存储设备请求配置数据的配置接口。此外，该系统包括初始化模块，用于向配置界面查询配置数据，并将配置接口提供的配置数据分配给互连设备内的多个单元。

4. 发明授权

US06957312B1 NVRAM control protocol 失效
标题翻译： NVRAM控制协议
公开(公告)号：US06957312B1
公开(公告)日：2005-10-18
申请号：US10431995
申请日：2003-05-07
申请人： Norman C. Chou , Prasad Vajjhala , Daniel Bourke
发明人： Norman C. Chou , Prasad Vajjhala , Daniel Bourke
IPC分类号： G06F12/16
CPC分类号： G11C16/102 , G11C16/105
摘要： In one embodiment, a method for facilitating detection of, and recovery from, data contamination in a non-volatile storage device coupled to an interconnect device includes receiving data to be written to a content area on a non-volatile storage device coupled to an interconnect device, updating a contamination indicator stored in a supplemental area of the non-volatile storage device with a first value indicating potential data contamination in the content area, and transferring the data to the non-volatile storage device for a write to the content area. Further, if a determination is made that the write of the transferred data has completed, the contamination indicator is updated with a second value indicating lack of data contamination in the content area.
摘要翻译：在一个实施例中，一种便于检测和从与互连设备耦合的非易失性存储设备中的数据污染恢复的方法包括接收要写入耦合到互连的非易失性存储设备上的内容区域的数据装置，用存储在所述非易失性存储装置的补充区域中的污染指示符，以指示所述内容区域中的潜在数据污染的第一值进行更新，以及将所述数据传送到所述非易失性存储装置以写入所述内容区域。此外，如果确定所传送的数据的写入已经完成，则污染指示符以指示内容区域中的数据污染不足的第二值更新。

5. 发明授权

US07296096B2 Method and system for configuring an interconnect device 有权
标题翻译：用于配置互连设备的方法和系统
公开(公告)号：US07296096B2
公开(公告)日：2007-11-13
申请号：US11173167
申请日：2005-07-01
申请人： Norman C. Chou , Prasad Vajihala , Richard Schober , Laura Randall , Ian G. Collof
发明人： Norman C. Chou , Prasad Vajihala , Richard Schober , Laura Randall , Ian G. Collof
IPC分类号： G06F3/00
CPC分类号： G06F13/4031
摘要： In one embodiment, a system for configuring an interconnect device includes a non-volatile storage device to store configuration data associated with the interconnect device and a configuration interface to request the configuration data from the non-volatile storage device. Further, the system includes an initialization module to query the configuration interface for the configuration data and to distribute the configuration data provided by the configuration interface to multiple units within the interconnect device.
摘要翻译：在一个实施例中，用于配置互连设备的系统包括用于存储与互连设备相关联的配置数据的非易失性存储设备和用于从非易失性存储设备请求配置数据的配置接口。此外，该系统包括初始化模块，用于向配置界面查询配置数据，并将配置接口提供的配置数据分配给互连设备内的多个单元。

6. 发明授权

US06763418B1 Request bus arbitration 有权
标题翻译：请求总线仲裁
公开(公告)号：US06763418B1
公开(公告)日：2004-07-13
申请号：US09948925
申请日：2001-09-07
申请人： Norman C. Chou , Yolin Lih , Mercedes Gil
发明人： Norman C. Chou , Yolin Lih , Mercedes Gil
IPC分类号： G06F1336
CPC分类号： H04L49/101 , G06F13/362 , H04L47/24 , H04L47/26 , H04L47/50 , H04L49/205 , H04L49/253
摘要： A method and system to arbitrate requests of a plurality of ports of an interconnect device are provided. Every port receives combined pending request data that includes a pending request indicator associated with each of the plurality of ports. Each pending request indicator specifies whether a corresponding port has a pending request that needs to be submitted to a request bus of the interconnect device. Further, at each port, a turn to submit a request to the request bus is allocated to one of the plurality of ports based on the combined pending request data, a set of values stored in a mask register and a priority scheme associated with the plurality of ports.
摘要翻译：提供了一种仲裁互连设备的多个端口的请求的方法和系统。每个端口接收包括与多个端口中的每一个相关联的未决请求指示符的组合待决请求数据。每个未决请求指示符指定相应端口是否具有需要提交到互连设备的请求总线的挂起请求。此外，在每个端口，基于组合的等待请求数据，存储在屏蔽寄存器中的一组值和与多个端口相关联的优先级方案，向请求总线提交请求的转弯被分配给多个端口中的一个的港口。

7. 发明授权

US07526676B2 Slave device having independent error recovery 失效
标题翻译：从设备具有独立的错误恢复
公开(公告)号：US07526676B2
公开(公告)日：2009-04-28
申请号：US10933750
申请日：2004-09-03
申请人： Norman C. Chou , Whitney Li
发明人： Norman C. Chou , Whitney Li
IPC分类号： G06F11/00 , G06F11/07
CPC分类号： G06F11/0793 , G06F11/0745 , G06F11/1471
摘要： A slave device adapted to couple to a master processor and including an error handler and a communication controller. The error handler is configured to detect errors internal to the slave device and, in response to detecting at least one error and independent of the master processor, configured to select an error recovery operation based on the at least one detected error and to initiate and perform the selected error recovery operation. The communication controller is configured to communicate with the master processor according to a master/slave protocol, and configured to maintain the master/slave protocol during performance of the selected error recovery operation by the error handler.
摘要翻译：适于耦合到主处理器并且包括错误处理器和通信控制器的从设备。错误处理器被配置为检测从设备内部的错误，并且响应于检测到至少一个错误并且独立于主处理器，被配置为基于至少一个检测到的错误来选择错误恢复操作并且启动和执行所选的错误恢复操作。通信控制器被配置为根据主/从协议与主处理器通信，并且被配置为在由错误处理程序执行所选择的错误恢复操作期间维护主/从协议。

8. 发明授权

US07290277B1 Control of authentication data residing in a network device 有权
标题翻译：控制驻留在网络设备中的认证数据
公开(公告)号：US07290277B1
公开(公告)日：2007-10-30
申请号：US10057159
申请日：2002-01-24
申请人： Norman C. Chou , Olivier Cremel
发明人： Norman C. Chou , Olivier Cremel
IPC分类号： H04L9/32
CPC分类号： H04L63/068 , H04L63/08
摘要： A system for supporting management operations associated with an interconnect device includes a port of the interconnect device to maintain authentication data that facilitates authorization of a management operation and a configuration switch coupled to the port to generate a reset signal in response to an operator's command. The port is operable to reset the authentication data upon receiving the reset signal from the configuration switch.
摘要翻译：用于支持与互连设备相关联的管理操作的系统包括互连设备的端口，用于维护认证数据，其有助于管理操作的授权和耦合到端口的配置开关以响应于操作者的命令生成复位信号。端口可操作以在从配置开关接收到复位信号时复位认证数据。

9. 发明授权

US07054330B1 Mask-based round robin arbitration 有权
标题翻译：基于面罩的循环仲裁
公开(公告)号：US07054330B1
公开(公告)日：2006-05-30
申请号：US09948748
申请日：2001-09-07
申请人： Norman C. Chou , Yolin Lih , Mercedes Gil
发明人： Norman C. Chou , Yolin Lih , Mercedes Gil
IPC分类号： H04J3/02
CPC分类号： H04L47/50
摘要： A method and system to arbitrate between a plurality of resource requests are disclosed. In each arbitration within a current round of arbitration, a winning request is identified based on a priority associated with each requester participating in the arbitration and a set of values stored in a mask register. In response to identifying the winning request, a mask register value corresponding to a requestor of the winning request is updated to disqualify this requestor from further participation in the current round of arbitration. When the current round of arbitration completes, the set of values in the mask register is reset to allow each requestor to participate in the next round of arbitration. The current round of arbitration begins when each requester is qualified to participate in the current round of arbitration and completes when every participating requestor has been disqualified.
摘要翻译：公开了一种在多个资源请求之间进行仲裁的方法和系统。在当前一轮仲裁中的每个仲裁中，基于与参与仲裁的每个请求者相关联的优先级和存储在掩码寄存器中的一组值来识别获胜请求。响应于识别获胜请求，更新对应于获胜请求的请求者的掩码寄存器值，以使该请求者不再进一步参与当前仲裁。当当前一轮仲裁完成时，掩码寄存器中的值集合被重置，以允许每个请求者参与下一轮的仲裁。当每一个请求者有资格参加当前一轮的仲裁并且当每个参与请求者被取消资格时完成，本轮仲裁开始。

10. 发明授权

US5446913A Method and system for nonsequential execution of intermixed scalar and vector instructions in a data processing system utilizing a finish instruction array 失效
标题翻译：在使用完成指令数组的数据处理系统中不相继执行混合标量和向量指令的方法和系统
公开(公告)号：US5446913A
公开(公告)日：1995-08-29
申请号：US991665
申请日：1992-12-16
申请人： Norman C. Chou , Edward J. D'Avignon , James C. Gregerson , James R. Robinson , Michael S. Siegel , Michael A. Smoolca , Albert J. Van Norstrand, Jr.
发明人： Norman C. Chou , Edward J. D'Avignon , James C. Gregerson , James R. Robinson , Michael S. Siegel , Michael A. Smoolca , Albert J. Van Norstrand, Jr.
IPC分类号： G06F9/38 , G06F9/26 , G06F9/30
CPC分类号： G06F9/3885 , G06F9/3836
摘要： A method and system for enhancing processing efficiency in a data processing system which includes multiple scalar instruction processors and a vector instruction processor. An ordered sequence of intermixed scalar and vector instructions is processed in a nonsequential order by coupling those instructions to selected processors. As each instruction is finished an indication of that state is stored within a finish instruction array. The first vector instruction within the ordered sequence is initiated within the vector instruction processor only after an indication that each scalar instruction preceding the first vector instruction is finished. A vector advance signal is generated by the vector instruction processor each time processing of a vector instruction is initiated. A subsequent vector instruction is then initiated when the vector processor assets are available only in response to the presence of the vector advance signal and an indication that all scalar instructions which proceed the subsequent vector instruction within the ordered sequence have finished, without encountering an exception. In this manner, chained processing of vector instructions may be accomplished by initiating processing of a subsequent vector instruction only after possible interruption by a scalar instruction exception is no longer possible.
摘要翻译：一种用于提高包括多个标量指令处理器和向量指令处理器的数据处理系统中的处理效率的方法和系统。通过将这些指令耦合到所选择的处理器，以非顺序的顺序处理混合标量和向量指令的有序序列。当每个指令完成时，该状态的指示被存储在完成指令数组中。只有在第一个向量指令之前的每个标量指令完成的指示之后，才能在向量指令处理器内启动有序序列内的第一个向量指令。每次向量指令的处理开始时，矢量提前信号由矢量指令处理器产生。然后，当向量处理器资产仅在响应于向量提前信号的存在而可用时才启动随后的向量指令，并且指示在序列序列中进行随后的向量指令的所有标量指令已经完成，而不会遇到异常。以这种方式，可以通过仅在通过标量指令异常的可能中断之后启动对后续向量指令的处理来实现向量指令的链接处理。

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