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1. 发明申请

US20080177931A1 BYTE MASK COMMAND FOR MEMORIES 有权
公开(公告)号：US20080177931A1
公开(公告)日：2008-07-24
申请号：US11625158
申请日：2007-01-19
申请人： Roger Isaac , Stephan Rosner , Qamrul Hasan , Jeremy Mah
发明人： Roger Isaac , Stephan Rosner , Qamrul Hasan , Jeremy Mah
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F13/4239
摘要： A system is presented that facilitates masking data in write data bound for a memory device. The system contains a memory controller and a memory array communicatively coupled to the memory controller. The memory controller sends a write command and write data to the memory array and the memory array updates data contained therein based upon the write command and write data. If the write operation requires a byte mask, the controller sends a byte mask command via a command bus linking the controller and the memory array. Accordingly, separate and dedicated byte mask pins or bus is not necessary to convey byte mask information.
摘要翻译：提出了一种有助于屏蔽存储器件写入数据的数据的系统。该系统包含存储器控制器和通信地耦合到存储器控制器的存储器阵列。存储器控制器发送写命令并将数据写入存储器阵列，并且存储器阵列基于写命令和写数据来更新其中包含的数据。如果写操作需要一个字节掩码，则控制器通过链接控制器和存储器阵列的命令总线发送字节掩码命令。因此，不需要单独和专用的字节掩码引脚或总线来传送字节掩码信息。

2. 发明申请

US20070239918A1 Multi media card with high storage capacity 有权
标题翻译：具有高存储容量的多媒体卡
公开(公告)号：US20070239918A1
公开(公告)日：2007-10-11
申请号：US11400902
申请日：2006-04-10
申请人： Qamrul Hasan , Jeremy Mah , Stephan Rosner , Roger Isaac
发明人： Qamrul Hasan , Jeremy Mah , Stephan Rosner , Roger Isaac
IPC分类号： H05K7/10 , G06F12/00
CPC分类号： G06F12/0623 , G06F2212/2022
摘要： A multi media card includes a plurality of memory modules and an extraneous command decoder. The extraneous command decoder decodes a predetermined command for determining a selected memory module to be accessed from the plurality of memory modules, when a predetermined bit of the predetermined command is set to a predetermined logic level.
摘要翻译：多媒体卡包括多个存储器模块和外部命令解码器。当预定命令的预定位被设置为预定逻辑电平时，无关命令解码器解码用于确定要从多个存储器模块访问的所选存储器模块的预定命令。

3. 发明授权

US08230154B2 Fully associative banking for memory 有权
标题翻译：充分结合银行记忆
公开(公告)号：US08230154B2
公开(公告)日：2012-07-24
申请号：US11625150
申请日：2007-01-19
申请人： Roger Isaac , Stephan Rosner , Qamrul Hasan , Jeremy Mah
发明人： Roger Isaac , Stephan Rosner , Qamrul Hasan , Jeremy Mah
IPC分类号： G06F12/06
CPC分类号： G06F9/5016 , G11C15/00 , G11C16/26
摘要： A system is provided that facilitates read access in a memory device. The system comprises a plurality of row addresses buffers that store high order addresses associated with one or more software threads. The system further comprises a plurality of row data buffers. The row data buffers are each associated with at least one row address buffer and store row data within the range of the high order addresses of the row address buffers. The system increase memory device performance by limiting the latency associated with context switching. The plurality of row address buffers and row data buffers enables software threads to associate with one or more buffers and maintain efficient subsequent memory accesses despite context switching.
摘要翻译：提供了一种促进存储器件中的读取访问的系统。该系统包括存储与一个或多个软件线程相关联的高阶地址的多个行地址缓冲器。系统还包括多个行数据缓冲器。行数据缓冲器各自与至少一个行地址缓冲器相关联，并且在行地址缓冲器的高位地址的范围内存储行数据。该系统通过限制与上下文切换相关的延迟来增加存储器件性能。多个行地址缓冲器和行数据缓冲器使得软件线程能够与一个或多个缓冲器相关联，并且尽管上下文切换来维持有效的后续存储器访问。

4. 发明申请

US20080177930A1 FULLY ASSOCIATIVE BANKING FOR MEMORY 有权
标题翻译：全面的联想银行记忆
公开(公告)号：US20080177930A1
公开(公告)日：2008-07-24
申请号：US11625150
申请日：2007-01-19
申请人： Roger Isaac , Stephan Rosner , Qamrul Hasan , Jeremy Mah
发明人： Roger Isaac , Stephan Rosner , Qamrul Hasan , Jeremy Mah
IPC分类号： G06F12/02
CPC分类号： G06F9/5016 , G11C15/00 , G11C16/26
摘要： A system is provided that facilitates read access in a memory device. The system comprises a plurality of row addresses buffers that store high order addresses associated with one or more software threads. The system further comprises a plurality of row data buffers. The row data buffers are each associated with at least one row address buffer and store row data within the range of the high order addresses of the row address buffers. The system increase memory device performance by limiting the latency associated with context switching. The plurality of row address buffers and row data buffers enables software threads to associate with one or more buffers and maintain efficient subsequent memory accesses despite context switching.
摘要翻译：提供了一种促进存储器件中的读取访问的系统。该系统包括存储与一个或多个软件线程相关联的高阶地址的多个行地址缓冲器。系统还包括多个行数据缓冲器。行数据缓冲器各自与至少一个行地址缓冲器相关联，并且在行地址缓冲器的高位地址的范围内存储行数据。该系统通过限制与上下文切换相关的延迟来增加存储器件性能。多个行地址缓冲器和行数据缓冲器使得软件线程能够与一个或多个缓冲器相关联，并且尽管上下文切换来维持有效的后续存储器访问。

5. 发明授权

US08239637B2 Byte mask command for memories 有权
标题翻译：用于记忆的字节掩码命令
公开(公告)号：US08239637B2
公开(公告)日：2012-08-07
申请号：US11625158
申请日：2007-01-19
申请人： Roger Isaac , Stephan Rosner , Qamrul Hasan , Jeremy Mah
发明人： Roger Isaac , Stephan Rosner , Qamrul Hasan , Jeremy Mah
IPC分类号： G06F12/00
CPC分类号： G06F13/4239
摘要： A system is presented that facilitates masking data in write data bound for a memory device. The system contains a memory controller and a memory array communicatively coupled to the memory controller. The memory controller sends a write command and write data to the memory array and the memory array updates data contained therein based upon the write command and write data. If the write operation requires a byte mask, the controller sends a byte mask command via a command bus linking the controller and the memory array. Accordingly, separate and dedicated byte mask pins or bus is not necessary to convey byte mask information.
摘要翻译：提出了一种有助于屏蔽存储器件写入数据的数据的系统。该系统包含存储器控制器和通信地耦合到存储器控制器的存储器阵列。存储器控制器发送写命令并将数据写入存储器阵列，并且存储器阵列基于写命令和写数据来更新其中包含的数据。如果写操作需要一个字节掩码，则控制器通过链接控制器和存储器阵列的命令总线发送字节掩码命令。因此，不需要单独和专用的字节掩码引脚或总线来传送字节掩码信息。

6. 发明授权

US07639768B1 Method for improving performance in a mobile device 有权
标题翻译：提高移动设备性能的方法
公开(公告)号：US07639768B1
公开(公告)日：2009-12-29
申请号：US11414845
申请日：2006-05-01
申请人： Qamrul Hasan , Jeremy Mah , Stephan Rosner
发明人： Qamrul Hasan , Jeremy Mah , Stephan Rosner
IPC分类号： H04L7/00 , H04L25/00 , H04L25/40
CPC分类号： G06F13/4243 , G06F13/1657 , Y02D10/14 , Y02D10/151
摘要： In the operation of a mobile device (such as a cellular telephone or a PDA, i.e. Personal Digital Assistant), which mobile device includes a mobile terminal and a memory module, certain operational signals of the mobile device are multiplexed and demultiplexed, resulting in efficient device bus utilization and reduced device pin count.
摘要翻译：在移动设备（例如蜂窝电话或PDA，即个人数字助理）的操作中，哪个移动设备包括移动终端和存储器模块，移动设备的某些操作信号被多路复用和解复用，导致有效器件总线利用率和减少器件引脚数。

7. 发明授权

US07813459B2 Digital data transfer between different clock domains 有权
标题翻译：不同时钟域之间的数字数据传输
公开(公告)号：US07813459B2
公开(公告)日：2010-10-12
申请号：US11242215
申请日：2005-10-03
申请人： Qamrul Hasan , Stephan Rosner , Jeremy Mah
发明人： Qamrul Hasan , Stephan Rosner , Jeremy Mah
IPC分类号： H04L7/00
CPC分类号： H04L7/0012
摘要： One or more aspects of the present invention pertain to transferring digital data between first and second domains, where a first clock of the first domain operates at a first frequency and a second clock of the second domain operates at a second frequency, where the first frequency is higher than the second frequency, and where the first and second clocks have arbitrary phase relationships relative to one another. Techniques employed facilitate efficient digital data transfer between the first and second domains while conserving valuable semiconductor real estate.
摘要翻译：本发明的一个或多个方面涉及在第一和第二域之间传送数字数据，其中第一域的第一时钟以第一频率工作，而第二域的第二时钟以第二频率工作，其中第一频率高于第二频率，并且其中第一和第二时钟相对于彼此具有任意的相位关系。所采用的技术促进了第一和第二域之间的有效数字数据传输，同时节省了有价值的半导体空间。

8. 发明申请

US20070076830A1 Digital data transfer between different clock domains 有权
标题翻译：不同时钟域之间的数字数据传输
公开(公告)号：US20070076830A1
公开(公告)日：2007-04-05
申请号：US11242215
申请日：2005-10-03
申请人： Qamrul Hasan , Stephan Rosner , Jeremy Mah
发明人： Qamrul Hasan , Stephan Rosner , Jeremy Mah
IPC分类号： H04L7/00
CPC分类号： H04L7/0012
摘要： One or more aspects of the present invention pertain to transferring digital data between first and second domains, where a first clock of the first domain operates at a first frequency and a second clock of the second domain operates at a second frequency, where the first frequency is higher than the second frequency, and where the first and second clocks have arbitrary phase relationships relative to one another. Techniques employed facilitate efficient digital data transfer between the first and second domains while conserving valuable semiconductor real estate.
摘要翻译：本发明的一个或多个方面涉及在第一和第二域之间传送数字数据，其中第一域的第一时钟以第一频率工作，而第二域的第二时钟以第二频率工作，其中第一频率高于第二频率，并且其中第一和第二时钟相对于彼此具有任意的相位关系。所采用的技术促进了第一和第二域之间的有效数字数据传输，同时节省了有价值的半导体空间。

9. 发明授权

US08819326B1 Host/client system having a scalable serial bus interface 有权
标题翻译：主机/客户端系统具有可扩展的串行总线接口
公开(公告)号：US08819326B1
公开(公告)日：2014-08-26
申请号：US11638338
申请日：2006-12-12
申请人： Stephan Rosner , Qamrul Hasan , Jeremy Mah
发明人： Stephan Rosner , Qamrul Hasan , Jeremy Mah
IPC分类号： G06F13/36
CPC分类号： G06F13/1678 , G06F13/3625 , G06F13/4247 , G06F13/4282
摘要： According to one exemplary embodiment, a host/client system includes a host module, which includes a CPU coupled to a system bridge. The host/client system further includes at least one client having an integrated interface, where the integrated interface is coupled to the system bridge through a scalable serial bus. The system bridge and the integrated interface enable high bandwidth communication between the CPU and the at least one client through the scalable serial bus, thereby allowing control of bus width between the host module and the client.
摘要翻译：根据一个示例性实施例，主机/客户端系统包括主机模块，其包括耦合到系统桥的CPU。主机/客户端系统还包括至少一个具有集成接口的客户端，其中集成接口通过可伸缩串行总线耦合到系统桥。系统桥接器和集成接口可通过可伸缩串行总线实现CPU与至少一个客户端之间的高带宽通信，从而可以控制主机模块与客户端之间的总线宽度。

10. 发明授权

US07404026B2 Multi media card with high storage capacity 有权
标题翻译：具有高存储容量的多媒体卡
公开(公告)号：US07404026B2
公开(公告)日：2008-07-22
申请号：US11400902
申请日：2006-04-10
申请人： Qamrul Hasan , Jeremy Mah , Stephan Rosner , Roger Dwain Isaac
发明人： Qamrul Hasan , Jeremy Mah , Stephan Rosner , Roger Dwain Isaac
IPC分类号： G06F13/00
CPC分类号： G06F12/0623 , G06F2212/2022
摘要： A multi media card includes a plurality of memory modules and an extraneous command decoder. The extraneous command decoder decodes a predetermined command for determining a selected memory module to be accessed from the plurality of memory modules, when a predetermined bit of the predetermined command is set to a predetermined logic level.
摘要翻译：多媒体卡包括多个存储器模块和外部命令解码器。当预定命令的预定位被设置为预定逻辑电平时，无关命令解码器解码用于确定要从多个存储器模块访问的所选存储器模块的预定命令。

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