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1. 发明授权

US09159396B2 Mechanism for facilitating fine-grained self-refresh control for dynamic memory devices 有权
标题翻译：促进动态存储设备的细粒度自刷新控制的机制
公开(公告)号：US09159396B2
公开(公告)日：2015-10-13
申请号：US13173302
申请日：2011-06-30
申请人： Roger Isaac , Alan Ruberg
发明人： Roger Isaac , Alan Ruberg
IPC分类号： G06F12/00 , G11C11/406
CPC分类号： G11C11/40615 , G11C11/40618 , G11C2211/4061
摘要： A mechanism for facilitating improved refresh schemes for memory devices is described. In one embodiment, an apparatus includes a memory device having refresh logic and memory cells, the memory cells including data cells and supplemental cells, the supplemental cells to be observed. The supplemental cells emulate a decay characteristic of the data cells performing regular refresh operations according to an existing refresh policy. The apparatus may further include the refresh logic to receive, from the supplemental cells, observation data relating to decaying of the supplemental cells, and correlate the observation data to data cell performance. The refresh logic to generate a policy recommendation based on the observation data collected by the supplemental cells.
摘要翻译：描述了一种用于促进用于存储器件的改进刷新方案的机制。在一个实施例中，一种装置包括具有刷新逻辑和存储器单元的存储器件，存储器单元包括数据单元和补充单元，待观察的补充单元。补充单元模拟根据现有刷新策略执行定期刷新操作的数据单元的衰减特性。该装置还可以包括刷新逻辑，用于从补充单元接收与补充单元衰减有关的观测数据，并将观测数据与数据单元性能相关联。基于由补充单元收集的观察数据生成策略推荐的刷新逻辑。

2. 发明授权

US07877558B2 Memory controller prioritization scheme 有权
标题翻译：内存控制器优先级排序方案
公开(公告)号：US07877558B2
公开(公告)日：2011-01-25
申请号：US11837943
申请日：2007-08-13
申请人： William A. Hughes , Vydhyanathan Kalyanasundharam , Philip E. Madrid , Roger Isaac
发明人： William A. Hughes , Vydhyanathan Kalyanasundharam , Philip E. Madrid , Roger Isaac
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F13/1626
摘要： A system includes a processor coupled to a memory through a memory controller. The memory controller includes first and second queues. The memory controller receives memory requests from the processor, assigns a priority to each request, stores each request in the first queue, and schedules processing of the requests based on their priorities. The memory controller changes the priority of a request in the first queue in response to a trigger, sends a next scheduled request from the first queue to the second queue in response to detecting the next scheduled request has the highest priority of any request in the first queue, and sends requests from the second queue to the memory. The memory controller changes the priority of different types of requests in response to different types of triggers. The memory controller maintains a copy of each request sent to the second queue in the first queue.
摘要翻译：系统包括通过存储器控制器耦合到存储器的处理器。存储器控制器包括第一和第二队列。存储器控制器从处理器接收存储器请求，为每个请求分配优先级，将每个请求存储在第一个队列中，并根据其优先级对请求进行调度处理。存储器控制器响应于触发器改变第一队列中的请求的优先级，响应于检测到下一个调度的请求而将下一个调度的请求从第一队列发送到第二队列，该请求具有第一队列中的任何请求的最高优先级队列，并将请求从第二个队列发送到内存。内存控制器根据不同类型的触发器更改不同类型请求的优先级。存储器控制器维护发送到第一队列中的第二队列的每个请求的副本。

3. 发明授权

US07644226B1 System and method for maintaining RAM command timing across phase-shifted time domains 有权
标题翻译：用于在相移时间域上维护RAM命令定时的系统和方法
公开(公告)号：US07644226B1
公开(公告)日：2010-01-05
申请号：US11642412
申请日：2006-12-19
申请人： Roger Isaac , Stephan Rosner , Qamrul Hasan
发明人： Roger Isaac , Stephan Rosner , Qamrul Hasan
IPC分类号： G06F12/00
CPC分类号： G06F13/1668
摘要： According to one exemplary embodiment, a RAM employing system includes a RAM and a RAM controller coupled to the RAM. The RAM employing system further includes a command queue, which is configured to receive time encoded RAM commands from the RAM controller. The RAM is configured to retrieve, decode, and execute each of the time encoded RAM commands in the command queue.
摘要翻译：根据一个示例性实施例，RAM采用系统包括RAM和耦合到RAM的RAM控制器。 RAM采用系统还包括命令队列，其被配置为从RAM控制器接收时间编码的RAM命令。 RAM被配置为在命令队列中检索，解码和执行每个时间编码的RAM命令。

4. 发明申请

US20070239918A1 Multi media card with high storage capacity 有权
标题翻译：具有高存储容量的多媒体卡
公开(公告)号：US20070239918A1
公开(公告)日：2007-10-11
申请号：US11400902
申请日：2006-04-10
申请人： Qamrul Hasan , Jeremy Mah , Stephan Rosner , Roger Isaac
发明人： Qamrul Hasan , Jeremy Mah , Stephan Rosner , Roger Isaac
IPC分类号： H05K7/10 , G06F12/00
CPC分类号： G06F12/0623 , G06F2212/2022
摘要： A multi media card includes a plurality of memory modules and an extraneous command decoder. The extraneous command decoder decodes a predetermined command for determining a selected memory module to be accessed from the plurality of memory modules, when a predetermined bit of the predetermined command is set to a predetermined logic level.
摘要翻译：多媒体卡包括多个存储器模块和外部命令解码器。当预定命令的预定位被设置为预定逻辑电平时，无关命令解码器解码用于确定要从多个存储器模块访问的所选存储器模块的预定命令。

5. 发明申请

US20080177931A1 BYTE MASK COMMAND FOR MEMORIES 有权
公开(公告)号：US20080177931A1
公开(公告)日：2008-07-24
申请号：US11625158
申请日：2007-01-19
申请人： Roger Isaac , Stephan Rosner , Qamrul Hasan , Jeremy Mah
发明人： Roger Isaac , Stephan Rosner , Qamrul Hasan , Jeremy Mah
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F13/4239
摘要： A system is presented that facilitates masking data in write data bound for a memory device. The system contains a memory controller and a memory array communicatively coupled to the memory controller. The memory controller sends a write command and write data to the memory array and the memory array updates data contained therein based upon the write command and write data. If the write operation requires a byte mask, the controller sends a byte mask command via a command bus linking the controller and the memory array. Accordingly, separate and dedicated byte mask pins or bus is not necessary to convey byte mask information.
摘要翻译：提出了一种有助于屏蔽存储器件写入数据的数据的系统。该系统包含存储器控制器和通信地耦合到存储器控制器的存储器阵列。存储器控制器发送写命令并将数据写入存储器阵列，并且存储器阵列基于写命令和写数据来更新其中包含的数据。如果写操作需要一个字节掩码，则控制器通过链接控制器和存储器阵列的命令总线发送字节掩码命令。因此，不需要单独和专用的字节掩码引脚或总线来传送字节掩码信息。

6. 发明授权

US08760188B2 Configurable multi-dimensional driver and receiver 有权
标题翻译：可配置的多维驱动和接收器
公开(公告)号：US08760188B2
公开(公告)日：2014-06-24
申请号：US13174616
申请日：2011-06-30
申请人： Srikanth Gondi , Roger Isaac
发明人： Srikanth Gondi , Roger Isaac
IPC分类号： H03K17/16
CPC分类号： H04L25/03019 , H04L7/0037 , H04L7/0331 , H04L25/0278 , H04L25/028 , H04L25/0292 , H04L25/0298 , H04L25/03012 , H04L25/03343
摘要： Embodiments of the invention are generally directed to a configurable multi-mode driver and receiver. An embodiment of a communication system includes a communication channel, and a first device and a second device coupled with the communication channel. The first device includes a driver apparatus to drive data signals on the communication channel, the driver apparatus including circuits to receive and drive the data signals, where the circuits are configurable for termination resistance of the driver circuit apparatus, and each of the plurality of circuits is comprised of one or more circuit units, the circuit units being configurable for equalization control of the driver apparatus. The second device includes a receiver to receive data signals from the communication channel as an input. Either the first device or the second device includes configurable circuit elements to provide signal reflection control for the system.
摘要翻译：本发明的实施例通常涉及可配置的多模式驱动器和接收器。通信系统的实施例包括通信信道，以及与通信信道耦合的第一设备和第二设备。第一装置包括用于驱动通信信道上的数据信号的驱动器装置，该驱动器装置包括用于接收和驱动数据信号的电路，其中电路可配置为驱动电路装置的终端电阻，并且多个电路中的每一个由一个或多个电路单元组成，电路单元可配置用于驱动器装置的均衡控制。第二装置包括从通信信道接收数据信号作为输入的接收机。第一设备或第二设备包括可配置的电路元件，以为系统提供信号反射控制。

7. 发明申请

US20130007357A1 MECHANISM FOR FACILITATING FINE-GRAINED SELF-REFRESH CONTROL FOR DYNAMIC MEMORY DEVICES 有权
标题翻译：促进动态记忆装置精细自动自动控制的机制
公开(公告)号：US20130007357A1
公开(公告)日：2013-01-03
申请号：US13173302
申请日：2011-06-30
申请人： Roger Isaac , Alan Ruberg
发明人： Roger Isaac , Alan Ruberg
IPC分类号： G06F12/00
CPC分类号： G11C11/40615 , G11C11/40618 , G11C2211/4061
摘要： A mechanism for facilitating improved refresh schemes for memory devices is described. In one embodiment, an apparatus includes a memory device having refresh logic and memory cells, the memory cells including data cells and supplemental cells, the supplemental cells to be observed. The supplemental cells emulate a decay characteristic of the data cells performing regular refresh operations according to an existing refresh policy. The apparatus may further include the refresh logic to receive, from the supplemental cells, observation data relating to decaying of the supplemental cells, and correlate the observation data to data cell performance. The refresh logic to generate a policy recommendation based on the observation data collected by the supplemental cells.
摘要翻译：描述了一种用于促进用于存储器件的改进刷新方案的机制。在一个实施例中，一种装置包括具有刷新逻辑和存储器单元的存储器件，存储器单元包括数据单元和补充单元，待观察的补充单元。补充单元模拟根据现有刷新策略执行定期刷新操作的数据单元的衰减特性。该装置还可以包括刷新逻辑，用于从补充单元接收与补充单元衰减有关的观测数据，并将观测数据与数据单元性能相关联。基于由补充单元收集的观察数据生成策略推荐的刷新逻辑。

8. 发明申请

US20130002290A1 CONFIGURABLE MULTI-DIMENSIONAL DRIVER AND RECEIVER 有权
标题翻译：可配置的多维驱动器和接收器
公开(公告)号：US20130002290A1
公开(公告)日：2013-01-03
申请号：US13174616
申请日：2011-06-30
申请人： Srikanth Gondi , Roger Isaac
发明人： Srikanth Gondi , Roger Isaac
IPC分类号： H03K19/003
CPC分类号： H04L25/03019 , H04L7/0037 , H04L7/0331 , H04L25/0278 , H04L25/028 , H04L25/0292 , H04L25/0298 , H04L25/03012 , H04L25/03343
摘要： Embodiments of the invention are generally directed to a configurable multi-mode driver and receiver. An embodiment of a communication system includes a communication channel, and a first device and a second device coupled with the communication channel. The first device includes a driver apparatus to drive data signals on the communication channel, the driver apparatus including circuits to receive and drive the data signals, where the circuits are configurable for termination resistance of the driver circuit apparatus, and each of the plurality of circuits is comprised of one or more circuit units, the circuit units being configurable for equalization control of the driver apparatus. The second device includes a receiver to receive data signals from the communication channel as an input. Either the first device or the second device includes configurable circuit elements to provide signal reflection control for the system.
摘要翻译：本发明的实施例通常涉及可配置的多模式驱动器和接收器。通信系统的实施例包括通信信道，以及与通信信道耦合的第一设备和第二设备。第一装置包括用于驱动通信信道上的数据信号的驱动器装置，该驱动器装置包括用于接收和驱动数据信号的电路，其中电路可配置为驱动电路装置的终端电阻，并且多个电路中的每一个由一个或多个电路单元组成，电路单元可配置为用于驱动器装置的均衡控制。第二装置包括从通信信道接收数据信号作为输入的接收机。第一设备或第二设备包括可配置的电路元件，以为系统提供信号反射控制。

9. 发明授权

US08230154B2 Fully associative banking for memory 有权
标题翻译：充分结合银行记忆
公开(公告)号：US08230154B2
公开(公告)日：2012-07-24
申请号：US11625150
申请日：2007-01-19
申请人： Roger Isaac , Stephan Rosner , Qamrul Hasan , Jeremy Mah
发明人： Roger Isaac , Stephan Rosner , Qamrul Hasan , Jeremy Mah
IPC分类号： G06F12/06
CPC分类号： G06F9/5016 , G11C15/00 , G11C16/26
摘要： A system is provided that facilitates read access in a memory device. The system comprises a plurality of row addresses buffers that store high order addresses associated with one or more software threads. The system further comprises a plurality of row data buffers. The row data buffers are each associated with at least one row address buffer and store row data within the range of the high order addresses of the row address buffers. The system increase memory device performance by limiting the latency associated with context switching. The plurality of row address buffers and row data buffers enables software threads to associate with one or more buffers and maintain efficient subsequent memory accesses despite context switching.
摘要翻译：提供了一种促进存储器件中的读取访问的系统。该系统包括存储与一个或多个软件线程相关联的高阶地址的多个行地址缓冲器。系统还包括多个行数据缓冲器。行数据缓冲器各自与至少一个行地址缓冲器相关联，并且在行地址缓冲器的高位地址的范围内存储行数据。该系统通过限制与上下文切换相关的延迟来增加存储器件性能。多个行地址缓冲器和行数据缓冲器使得软件线程能够与一个或多个缓冲器相关联，并且尽管上下文切换来维持有效的后续存储器访问。

10. 发明申请

US20080177930A1 FULLY ASSOCIATIVE BANKING FOR MEMORY 有权
标题翻译：全面的联想银行记忆
公开(公告)号：US20080177930A1
公开(公告)日：2008-07-24
申请号：US11625150
申请日：2007-01-19
申请人： Roger Isaac , Stephan Rosner , Qamrul Hasan , Jeremy Mah
发明人： Roger Isaac , Stephan Rosner , Qamrul Hasan , Jeremy Mah
IPC分类号： G06F12/02
CPC分类号： G06F9/5016 , G11C15/00 , G11C16/26
摘要： A system is provided that facilitates read access in a memory device. The system comprises a plurality of row addresses buffers that store high order addresses associated with one or more software threads. The system further comprises a plurality of row data buffers. The row data buffers are each associated with at least one row address buffer and store row data within the range of the high order addresses of the row address buffers. The system increase memory device performance by limiting the latency associated with context switching. The plurality of row address buffers and row data buffers enables software threads to associate with one or more buffers and maintain efficient subsequent memory accesses despite context switching.
摘要翻译：提供了一种促进存储器件中的读取访问的系统。该系统包括存储与一个或多个软件线程相关联的高阶地址的多个行地址缓冲器。系统还包括多个行数据缓冲器。行数据缓冲器各自与至少一个行地址缓冲器相关联，并且在行地址缓冲器的高位地址的范围内存储行数据。该系统通过限制与上下文切换相关的延迟来增加存储器件性能。多个行地址缓冲器和行数据缓冲器使得软件线程能够与一个或多个缓冲器相关联，并且尽管上下文切换来维持有效的后续存储器访问。

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