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1. 发明授权

US6098160A Data pointer for outputting indirect addressing mode addresses within a single cycle and method therefor 失效
标题翻译：用于在单个周期内输出间接寻址模式地址的数据指针及其方法
公开(公告)号：US6098160A
公开(公告)日：2000-08-01
申请号：US959559
申请日：1997-10-28
申请人： Rodney J. Drake , Randy L. Yach , Igor Wojewoda , Joseph W. Triece , Brian Boles , Darrel Johansen
发明人： Rodney J. Drake , Randy L. Yach , Igor Wojewoda , Joseph W. Triece , Brian Boles , Darrel Johansen
IPC分类号： G06F9/35 , G06F12/00
CPC分类号： G06F9/35
摘要： A data pointer for generating an indirect addressing mode address within a single cycle for a selected one of a plurality of multiple indirect addressing modes. The data pointer is used with a processor architecture scheme which allows for encoding of multiple addressing modes. A data pointer register is coupled to the processor architecture scheme for storing a current address of an operand to be used in a simple indirect addressing mode. An incrementer is coupled to the data pointer register for incrementing the current address of an operand to be used in a simple indirect data addressing mode by a set number thereby generating an address of an operand to be used in an indirect addressing mode with auto preincrement. An adder is coupled to the data pointer register for combining the current address of an operand to be used in a simple indirect data addressing mode with an offset number thereby generating an address of an operand to be used in an indirect addressing mode with offset. A multiplexer circuit is coupled to an output of the data pointer register, to an output of the incrementer, and to an output of the adder for selecting a desired indirect addressing mode address.
摘要翻译：一种数据指针，用于在多个间接寻址模式中选定的一个周期内在单个周期内生成间接寻址模式地址。数据指针与处理器架构方案一起使用，该方案允许对多种寻址模式进行编码。数据指针寄存器耦合到处理器架构方案，用于存储要在简单的间接寻址模式中使用的操作数的当前地址。增量器被耦合到数据指针寄存器，用于以简单的间接数据寻址模式递增一个操作数的当前地址一个设定的数字，从而产生要以具有自动预压缩的间接寻址方式使用的操作数的地址。加法器耦合到数据指针寄存器，用于将要在简单间接数据寻址模式中使用的操作数的当前地址与偏移号组合，从而生成要在具有偏移量的间接寻址模式中使用的操作数的地址。多路复用器电路耦合到数据指针寄存器的输出，加法器的输出端和加法器的输出端，用于选择期望的间接寻址模式地址。

2. 发明授权

US06321319B2 Computer system for allowing a two word jump instruction to be executed in the same number of cycles as a single word jump instruction 有权
公开(公告)号：US06321319B2
公开(公告)日：2001-11-20
申请号：US09756304
申请日：2001-01-08
申请人： Rodney J. Drake , Randy L. Yach , Joseph W. Triece , Jennifer Chiao , Igor Wojewoda , Steve Allen
发明人： Rodney J. Drake , Randy L. Yach , Joseph W. Triece , Jennifer Chiao , Igor Wojewoda , Steve Allen
IPC分类号： G06F1202
CPC分类号： G06F9/3802 , G06F9/3816
摘要： A system for allowing a two word jump instruction to be executed in the same number of cycles as a single word jump instruction, thereby allowing a processor system to increase memory space without reducing performance. A first address bus is coupled to the linearized program memory for sending addresses of instructions to be fetched to a linearized program memory. A pointer is coupled to the first address bus for storing an address location of a current instruction in the linearized program memory to be fetched and for placing the address location of the current instruction to be fetched on the first address bus. A second address bus is provided and has one end coupled to the output of the program memory and a second end coupled to the first address bus. The second address bus is used for placing an address of an operand of a second word of the two word jump instruction onto the first address bus after an address of an operand of a first word of the two word jump instruction has been placed on the first address bus. This allows the addresses of the first word and the second word to be combined to provide the full address value of the two word jump instruction in the same number of cycles as a single word jump instruction.

3. 发明授权

US06243798B1 Computer system for allowing a two word jump instruction to be executed in the same number of cycles as a single word jump instruction 失效
标题翻译：用于允许以与单个字跳转指令相同的周期数来执行两个字跳转指令的计算机系统
公开(公告)号：US06243798B1
公开(公告)日：2001-06-05
申请号：US08958940
申请日：1997-10-28
申请人： Rodney J. Drake , Randy L. Yach , Joseph W. Triece , Jennifer Chiao , Igor Wojewoda , Steve Allen
发明人： Rodney J. Drake , Randy L. Yach , Joseph W. Triece , Jennifer Chiao , Igor Wojewoda , Steve Allen
IPC分类号： G06F1202
CPC分类号： G06F9/3802 , G06F9/3816
摘要： A system for allowing a two word jump instruction to be executed in the same number of cycles as a single word jump instruction, thereby allowing a processor system to increase memory space without reducing performance. A first address bus is coupled to the linearized program memory for sending addresses of instructions to be fetched to a linearized program memory. A pointer is coupled to the first address bus for storing an address location of a current instruction in the linearized program memory to be fetched and for placing the address location of the current instruction to be fetched on the first address bus. A second address bus is provided and has one end coupled to the output of the program memory and a second end coupled to the first address bus. The second address bus is used for placing an address of an operand of a second word of the two word jump instruction onto the first address bus after an address of an operand of a first word of the two word jump instruction has been placed on the first address bus. This allows the addresses of the first word and the second word to be combined to provide the full address value of the two word jump instruction in the same number of cycles as a single word jump instruction.
摘要翻译：用于允许以与单个字跳转指令相同的周期数来执行两个字跳转指令的系统，从而允许处理器系统增加存储器空间而不降低性能。第一地址总线耦合到线性化程序存储器，用于发送要获取的指令的地址到线性化程序存储器。指针耦合到第一地址总线，用于存储要获取的线性化程序存储器中的当前指令的地址位置，并将要提取的当前指令的地址位置放置在第一地址总线上。提供第二地址总线，其一端耦合到程序存储器的输出端，第二端耦合到第一地址总线。第二地址总线用于在双字跳转指令的第一字的操作数的地址已经被放置在第一地址总线上之后，将两字跳转指令的第二字的操作数的地址放置在第一地址总线上地址总线这允许将第一个字和第二个字的地址组合起来，以与单个字跳转指令相同的周期数来提供两个字跳转指令的完整地址值。

4. 发明授权

US07603601B2 Enabling special modes within a digital device 有权
标题翻译：在数字设备中启用特殊模式
公开(公告)号：US07603601B2
公开(公告)日：2009-10-13
申请号：US11355619
申请日：2006-02-16
申请人： Cristian P. Masgras , Michael Pyska , Edward Brian Boles , Joseph W. Triece , Igor Wojewoda , Mei-Ling Chen
发明人： Cristian P. Masgras , Michael Pyska , Edward Brian Boles , Joseph W. Triece , Igor Wojewoda , Mei-Ling Chen
IPC分类号： G01R31/3185
CPC分类号： G01R31/31701 , G06F11/273 , G11C29/003 , G11C29/46
摘要： A special mode key match comparison module has N-storage elements and a special mode key match comparator. The N-storage elements accumulate a serial data stream, and then determine whether a digital device should operate in a normal user mode, in a public programming mode, or in a particular private test mode. To reduce the possibility of accidentally decoding a false test or programming mode, the data stream has a sufficiently large number of N-bits to substantially reduce the probability of a false decode. To further reduce the possibility of accidentally decoding a programming or test mode, the special mode key match comparison module may be reset if less or more than N-clocks are detected during the accumulation of the N-bit serial data stream. The special mode key match data patterns may represent a normal user mode, a public programming mode, and particular private manufacturer test modes.
摘要翻译：特殊模式键匹配比较模块具有N存储元件和特殊模式键匹配比较器。 N存储元件累积串行数据流，然后确定数字设备是否应该以普通用户模式，公共编程模式或特定专用测试模式中操作。为了减少意外解码错误测试或编程模式的可能性，数据流具有足够大数量的N位，以显着降低错误解码的概率。为了进一步降低意外解码编程或测试模式的可能性，如果在N位串行数据流的累积期间检测到少于或多于N个时钟，则可以复位特殊模式键匹配比较模块。特殊模式键匹配数据模式可以表示正常的用户模式，公共编程模式和特定的私人制造商测试模式。

5. 发明授权

US06225678B1 Layout technique for a matching capacitor array using a continuous top electrode 有权
标题翻译：使用连续顶部电极的匹配电容器阵列的布局技术
公开(公告)号：US06225678B1
公开(公告)日：2001-05-01
申请号：US09221634
申请日：1998-12-23
申请人： Randy L. Yach , Igor Wojewoda
发明人： Randy L. Yach , Igor Wojewoda
IPC分类号： H01L2900
CPC分类号： H01L27/0805
摘要： A matching capacitor array is implemented on a single, monolithic integrated circuit. The array features a matrix of bottom electrodes and a plurality of continuous top electrode strips, where each continuous top electrode strip spans numerous bottom electrodes. The conductive contacts for each continuous top electrode strip are removed from the capacitor interface to the terminal ends of each of the continuous top electrode strips. The invention seeks to match or control parasitic and fringe capacitance, rather than to eliminate or minimize such capacitances. By creating a matched array, the parasitic and fringe capacitances of each matching capacitor unit cell are incorporated into the total capacitance of the unit cell.
摘要翻译：匹配的电容器阵列在单个单片集成电路上实现。该阵列具有底部电极矩阵和多个连续顶部电极条，其中每个连续顶部电极条跨越多个底部电极。每个连续顶部电极条的导电触点从电容器接口移除到每个连续顶部电极条的末端。本发明寻求匹配或控制寄生和边缘电容，而不是消除或最小化这种电容。通过创建匹配的阵列，每个匹配电容器单元的寄生和边缘电容被并入到单元的总电容中。

6. 发明授权

US06593639B2 Layout technique for a capacitor array using continuous upper electrodes 有权
标题翻译：使用连续上电极的电容器阵列布局技术
公开(公告)号：US06593639B2
公开(公告)日：2003-07-15
申请号：US09846018
申请日：2001-04-30
申请人： Randy L. Yach , Igor Wojewoda
发明人： Randy L. Yach , Igor Wojewoda
IPC分类号： H01L2900
CPC分类号： H01L27/0805
摘要： A matching capacitor array is implemented on a single, monolithic integrated circuit. The array features a matrix of bottom electrodes and a plurality of continuous top electrode strips, where each continuous top electrode strip spans numerous bottom electrodes. The conductive contacts for each continuous top electrode strip are removed from the capacitor interface to the terminal ends of each of the continuous top electrode strips. The invention seeks to match or control parasitic and fringe capacitance, rather than to eliminate or minimize such capacitances. By creating a matched array, the parasitic and fringe capacitances of each matching capacitor unit cell are incorporated into the total capacitance of the unit cell.
摘要翻译：匹配的电容器阵列在单个单片集成电路上实现。该阵列具有底部电极矩阵和多个连续顶部电极条，其中每个连续顶部电极条跨越多个底部电极。每个连续顶部电极条的导电触点从电容器接口移除到每个连续顶部电极条的末端。本发明寻求匹配或控制寄生和边缘电容，而不是消除或最小化这种电容。通过创建匹配的阵列，每个匹配电容器单元的寄生和边缘电容被并入到单元的总电容中。

7. 发明授权

US06230275B1 Circuit for powering down unused configuration bits to minimize power consumption 有权
标题翻译：关闭未使用配置位的电路，以最大限度地降低功耗
公开(公告)号：US06230275B1
公开(公告)日：2001-05-08
申请号：US09232053
申请日：1999-01-15
申请人： Joseph W. Triece , Rodney Drake , Igor Wojewoda
发明人： Joseph W. Triece , Rodney Drake , Igor Wojewoda
IPC分类号： G06F126
CPC分类号： G11C5/14 , G11C7/1045 , H03K19/0016
摘要： A system for powering down configuration circuits to minimize power consumption has at least one first configuration circuit for configuring a peripheral module. A second configuration circuit is coupled to the peripheral module and to the at least one first configuration circuit. The second configuration circuit is used for enabling and disabling the peripheral module. The second configuration circuit is further used to power down the at least one first configuration circuit to minimize current consumption of the at least one first configuration circuit when the peripheral module is disabled.
摘要翻译：用于断电配置电路以最小化功耗的系统具有用于配置外围模块的至少一个第一配置电路。第二配置电路耦合到外围模块和至少一个第一配置电路。第二个配置电路用于启用和禁用外围模块。当外围模块被禁用时，第二配置电路还用于断电至少一个第一配置电路以最小化至少一个第一配置电路的电流消耗。

8. 发明授权

US06463544B2 Method for powering down unused configuration bits to minimize power consumption 有权
标题翻译：关闭未使用配置位以最小化功耗的方法
公开(公告)号：US06463544B2
公开(公告)日：2002-10-08
申请号：US09850214
申请日：2001-05-07
申请人： Joseph W. Triece , Rodney Drake , Igor Wojewoda
发明人： Joseph W. Triece , Rodney Drake , Igor Wojewoda
IPC分类号： G06F126
CPC分类号： G11C5/14 , G11C7/1045 , H03K19/0016
摘要： A system for powering down configuration circuits to minimize power consumption has at least one first configuration circuit for configuring a peripheral module. A second configuration circuit is coupled to the peripheral module and to the at least one first configuration circuit. The second configuration circuit is used for enabling and disabling the peripheral module. The second configuration circuit is further used to power down the at least one first configuration circuit to minimize current consumption of the at least one first configuration circuit when the peripheral module is disabled.
摘要翻译：用于断电配置电路以最小化功耗的系统具有用于配置外围模块的至少一个第一配置电路。第二配置电路耦合到外围模块和至少一个第一配置电路。第二个配置电路用于启用和禁用外围模块。当外围模块被禁用时，第二配置电路还用于断电至少一个第一配置电路以最小化至少一个第一配置电路的电流消耗。

9. 发明授权

US6057705A Programmable pin designation for semiconductor devices 失效
标题翻译：半导体器件的可编程引脚名称
公开(公告)号：US6057705A
公开(公告)日：2000-05-02
申请号：US85826
申请日：1998-05-28
申请人： Igor Wojewoda , Rodney J. Drake , Brian E. Boles
发明人： Igor Wojewoda , Rodney J. Drake , Brian E. Boles
IPC分类号： G06F3/00 , G06F1/22 , G06F15/78 , H03K19/173 , G06F7/38
CPC分类号： G06F1/22 , H03K19/173 , H03K19/1731
摘要： The invention allows the programmer to designate one or more pins on a semiconductor device as either address pins, which are in addition to a predetermined set of address lines or as alternate I/O pins. The object of the invention is to provide the programmer with the capability of defining with preciseness the particular size of the address bus needed for a specific application. The invention is comprised of a programming port, optional programming logic, configuration logic, selection logic and a set of pins that may be configured as per the programmer's requirements. The invention is to exist on a single, monolithic semiconductor device.
摘要翻译：本发明允许编程器将半导体器件上的一个或多个引脚指定为除了预定的一组地址线之外的地址引脚或作为替代的I / O引脚。本发明的目的是为程序员提供精确定义特定应用所需的地址总线的特定大小的能力。本发明由编程端口，可选的编程逻辑，配置逻辑，选择逻辑和可以根据编程器的要求进行配置的一组引脚组成。本发明存在于单个单片半导体器件上。

10. 发明授权

US6029241A Processor architecture scheme having multiple bank address override sources for supplying address values and method therefor 失效
标题翻译：具有用于提供地址值的多个存储体地址覆盖源的处理器架构方案及其方法
公开(公告)号：US6029241A
公开(公告)日：2000-02-22
申请号：US959405
申请日：1997-10-28
申请人： Igor Wojewoda , Sumit Mitra , Rodney J. Drake
发明人： Igor Wojewoda , Sumit Mitra , Rodney J. Drake
IPC分类号： G06F9/34 , G06F9/30 , G06F9/35 , G06F12/06
CPC分类号： G06F9/3012 , G06F9/30098 , G06F9/30138 , G06F9/35
摘要： A processor architecture scheme which allows for encoding multiple addressing modes and which has multiple sources for generating a bank address value. The processor architecture scheme has a Central Processing Unit (CPU) for executing an instruction set. A data memory is coupled to the CPU. The data memory is used for storing and transferring data to and from the CPU. The data memory is divided into a plurality of banks wherein one of the plurality of banks is a dedicated bank for general and special purpose registers. A selection circuit is coupled to the data memory. The selection circuit is used for selecting one of the multiple sources for generating the bank address value. A bank select register is coupled to the selection circuit. The bank select register is used for supplying a bank address value for an instruction to be executed in a direct short addressing mode. An instruction register is coupled to the selection circuit for supplying a bank address values for an instruction to be executed in a direct long addressing mode and for supplying a register address within a bank for the instruction to be executed in a direct short addressing mode.
摘要翻译：一种处理器架构方案，其允许对多个寻址模式进行编码，并且具有用于生成存储体地址值的多个源。处理器架构方案具有用于执行指令集的中央处理单元（CPU）。数据存储器耦合到CPU。数据存储器用于存储和传输数据到和从CPU传输数据。数据存储器被分成多个存储体，其中多个存储体中的一个存储体是用于通用和专用寄存器的专用库。选择电路耦合到数据存储器。选择电路用于选择多个源之一以产生存储体地址值。存储体选择寄存器耦合到选择电路。存储体选择寄存器用于提供要在直接短寻址模式下执行的指令的存储体地址值。指令寄存器耦合到选择电路，用于提供用于以直接长寻址模式执行的指令的存储体地址值，以及用于以直接短寻址模式提供要执行的指令的存储体内的寄存器地址。

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