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1. 发明授权

US07603601B2 Enabling special modes within a digital device 有权
标题翻译：在数字设备中启用特殊模式
公开(公告)号：US07603601B2
公开(公告)日：2009-10-13
申请号：US11355619
申请日：2006-02-16
申请人： Cristian P. Masgras , Michael Pyska , Edward Brian Boles , Joseph W. Triece , Igor Wojewoda , Mei-Ling Chen
发明人： Cristian P. Masgras , Michael Pyska , Edward Brian Boles , Joseph W. Triece , Igor Wojewoda , Mei-Ling Chen
IPC分类号： G01R31/3185
CPC分类号： G01R31/31701 , G06F11/273 , G11C29/003 , G11C29/46
摘要： A special mode key match comparison module has N-storage elements and a special mode key match comparator. The N-storage elements accumulate a serial data stream, and then determine whether a digital device should operate in a normal user mode, in a public programming mode, or in a particular private test mode. To reduce the possibility of accidentally decoding a false test or programming mode, the data stream has a sufficiently large number of N-bits to substantially reduce the probability of a false decode. To further reduce the possibility of accidentally decoding a programming or test mode, the special mode key match comparison module may be reset if less or more than N-clocks are detected during the accumulation of the N-bit serial data stream. The special mode key match data patterns may represent a normal user mode, a public programming mode, and particular private manufacturer test modes.
摘要翻译：特殊模式键匹配比较模块具有N存储元件和特殊模式键匹配比较器。 N存储元件累积串行数据流，然后确定数字设备是否应该以普通用户模式，公共编程模式或特定专用测试模式中操作。为了减少意外解码错误测试或编程模式的可能性，数据流具有足够大数量的N位，以显着降低错误解码的概率。为了进一步降低意外解码编程或测试模式的可能性，如果在N位串行数据流的累积期间检测到少于或多于N个时钟，则可以复位特殊模式键匹配比较模块。特殊模式键匹配数据模式可以表示正常的用户模式，公共编程模式和特定的私人制造商测试模式。

2. 发明申请

US20060190791A1 Enabling special modes within a digital device 有权
公开(公告)号：US20060190791A1
公开(公告)日：2006-08-24
申请号：US11355619
申请日：2006-02-16
申请人： Cristian Masgras , Michael Pyska , Edward Boles , Joseph Triece , Igor Wojewoda , Mei-Ling Chen
发明人： Cristian Masgras , Michael Pyska , Edward Boles , Joseph Triece , Igor Wojewoda , Mei-Ling Chen
IPC分类号： G06F11/00 , G01R31/28
CPC分类号： G01R31/31701 , G06F11/273 , G11C29/003 , G11C29/46
摘要： A special mode key match comparison module has N-storage elements and a special mode key match comparator. The N-storage elements accumulate a serial data stream, and then determine whether a digital device should operate in a normal user mode, in a public programming mode, or in a particular private test mode. To reduce the possibility of accidentally decoding a false test or programming mode, the data stream has a sufficiently large number of N-bits to substantially reduce the probability of a false decode. To further reduce the possibility of accidentally decoding a programming or test mode, the special mode key match comparison module may be reset if less or more than N-clocks are detected during the accumulation of the N-bit serial data stream. The special mode key match data patterns may represent a normal user mode, a public programming mode, and particular private manufacturer test modes.

3. 发明授权

US06601160B2 Dynamically reconfigurable data space 有权
标题翻译：动态可重构数据空间
公开(公告)号：US06601160B2
公开(公告)日：2003-07-29
申请号：US09870448
申请日：2001-06-01
申请人： Michael Catherwood , Joseph W. Triece , Michael Pyska , Joshua M. Conner
发明人： Michael Catherwood , Joseph W. Triece , Michael Pyska , Joshua M. Conner
IPC分类号： G06F1576
CPC分类号： G06F9/342 , G06F9/30185 , G06F9/345 , G06F12/0284 , G06F12/109
摘要： A processor is provided that has a data memory that may be addressed as a dual memory space in one mode and as a single linear memory space in another mode. The memory may permit dual concurrent operand fetches from the data memory when DSP instructions are processed. The memory may then dynamically permit the same memory to be accessed as a single linear memory address space for non-DSP instructions.
摘要翻译：提供了一种处理器，其具有数据存储器，该数据存储器可以以一种模式被寻址为双存储器空间，并且在另一种模式下可以被寻址为单个线性存储器空当处理DSP指令时，存储器可能允许从数据存储器获取双重并发操作数。然后，存储器可以动态地允许相同的存储器作为用于非DSP指令的单个线性存储器地址空间被访问。

4. 发明申请

US20050265378A1 Streaming input-output ports in a digital device 审中-公开
标题翻译：在数字设备中流输入输出端口
公开(公告)号：US20050265378A1
公开(公告)日：2005-12-01
申请号：US11059598
申请日：2005-02-16
申请人： Joseph Julicher , Cristian Masgras , Michael Pyska
发明人： Joseph Julicher , Cristian Masgras , Michael Pyska
IPC分类号： G06F13/38 , H04Q11/00
CPC分类号： G06F13/385
摘要： A digital device comprising a digital processor, a streaming input-output (I/O) port module, and an interface port module having an independent data and control bus may be independently coupled to the streaming I/O port module. The streaming I/O port module may also be coupled to the digital processor, wherein the digital process may control whether the streaming I/O port module is coupled to either the interface port module or the digital processor. The interface port module may also be coupled to the digital processor independently of the streaming I/O port module. The interface port module and the streaming I/O port module may be adapted for parallel and/or serial data transfers. The streaming I/O port may be used to couple an external peripheral device to either the digital processor or to the interface port module.
摘要翻译：包括数字处理器，流输入输出（I / O）端口模块和具有独立数据和控制总线的接口端口模块的数字设备可以独立地耦合到流I / O端口模块。流式I / O端口模块还可以耦合到数字处理器，其中数字处理可以控制流I / O端口模块是否耦合到接口端口模块或数字处理器。接口端口模块也可以独立于流I / O端口模块耦合到数字处理器。接口端口模块和流I / O端口模块可适用于并行和/或串行数据传输。流式I / O端口可用于将外部外围设备耦合到数字处理器或接口端口模块。

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