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1. 发明授权

US06532171B2 Nonvolatile semiconductor memory capable of selectively erasing a plurality of elemental memory units 有权
标题翻译：能够选择性地擦除多个元件存储器单元的非易失性半导体存储器
公开(公告)号：US06532171B2
公开(公告)日：2003-03-11
申请号：US09919789
申请日：2001-07-31
申请人： Roberto Gastaldi , Paolo Cappelletti , Giulio Casagrande , Giovanni Campardo , Rino Micheloni
发明人： Roberto Gastaldi , Paolo Cappelletti , Giulio Casagrande , Giovanni Campardo , Rino Micheloni
IPC分类号： G11C1616
CPC分类号： G11C16/3431 , G11C16/16 , G11C16/34
摘要： A semiconductor memory such as a flash memory, which comprises at least one two-dimensional array of memory cells with a plurality of rows and columns of memory cells grouped in a plurality of packets. The memory cells belonging to the columns of each packet are formed in a respective semiconductor region with a first type of conductivity, this region being distinct from the semiconductor regions with the first type of conductivity in which the memory cells belonging to the columns of the remaining packets are formed. The semiconductor regions with the first type of conductivity divide the set of memory cells belonging to each row into a plurality of subsets of memory cells that constitute elemental memory units which can be modified individually. Thus memory units of very small dimensions can be erased individually, without excessive overhead in terms of area.
摘要翻译：诸如闪速存储器的半导体存储器，其包括具有分组在多个分组中的多个存储单元的行和列的存储器单元的至少一个二维阵列。属于每个分组的列的存储单元形成在具有第一类型导电性的相应半导体区域中，该区域与具有第一类型导电性的半导体区域不同，其中存储单元属于剩余的列形成包。具有第一类型导电性的半导体区域将属于每一行的存储单元集合分成多个存储单元子集，这些存储单元子集构成可单独修改的元素存储单元。因此，可以单独擦除非常小尺寸的存储单元，而在面积方面没有过多的开销。

2. 发明授权

US5612913A Byte erasable EEPROM fully compatible with a single power supply flash-EPROM process 失效
标题翻译：字节可擦除EEPROM完全兼容单电源闪存EPROM过程
公开(公告)号：US5612913A
公开(公告)日：1997-03-18
申请号：US533631
申请日：1995-09-25
申请人： Paolo Cappelletti , Giulio Casagrande
发明人： Paolo Cappelletti , Giulio Casagrande
IPC分类号： G11C17/00 , G11C16/04 , G11C16/16 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C7/00
CPC分类号： H01L27/115 , G11C16/0416 , G11C16/16
摘要： A byte erasable memory with an EEPROM type functionality that can be integrated in a fully compatible way with a standard FLASH process is composed by a matrix of FLASH cells organized in n bytes, each of m bits, addressable through a plurality of wordlines and bitlines. The EEPROM-type memory has an auxiliary selection structure composed of an n number of byte select transistors, a plurality of individually selectable source biasing lines and a plurality of select lines in the same number of the wordlines and selectable in a biunivocal way with the wordlines. The cells of a byte have a common source that is accessed and individually selectable through the respective select transistor. EEPROM functionality is obtained without any modification of the standard FLASH fabrication process by splitting the voltage applied between a control gate and the respective common source region of the cells that compose a certain selected byte about a common ground potential, during a byte erasing phase thus reducing the electrical stress induced on deselected cells.
摘要翻译：具有可以以完全兼容的方式与标准FLASH处理集成的EEPROM类型功能的字节可擦除存储器由以n字节组织的FLASH单元矩阵组成，每个m位可通过多个字线和位线寻址。 EEPROM型存储器具有由n个字节选择晶体管组成的辅助选择结构，多个单独可选择的源极偏置线和相同数量的字线中的多条选择线，并且可以与字线双向地选择。一个字节的单元具有通过相应选择晶体管访问和单独选择的公共源。在字节擦除阶段期间，通过将施加在控制栅极和组成关于公共接地电位的特定选定字节的单元的各个公共源极区域之间施加的电压分开来获得EEPROM功能，从而减少了EEPROM功能。在取消细胞上诱导的电应激。

3. 发明授权

US07012832B1 Magnetic memory cell with plural read transistors 有权
标题翻译：具有多个读取晶体管的磁存储单元
公开(公告)号：US07012832B1
公开(公告)日：2006-03-14
申请号：US10698747
申请日：2003-10-31
申请人： Kyusik Sin , Matthew R. Gibbons , William D. Jensen , Hugh Craig Hiner , Xizeng Stone Shi , Roberto Bez , Giulio Casagrande , Paolo Cappelletti
发明人： Kyusik Sin , Matthew R. Gibbons , William D. Jensen , Hugh Craig Hiner , Xizeng Stone Shi , Roberto Bez , Giulio Casagrande , Paolo Cappelletti
IPC分类号： G11C11/00
CPC分类号： G11C11/16
摘要： A magnetic random access memory (MRAM) device has increased ΔR/R for sensing a state of a pin-dependent tunneling (SDT) device. The MRAM device includes plural transistors connected to a read line for sensing the state of the SDT device. Plural transistors lower an underlying resistance during reading, increasing ΔR/R. The plural transistors can share a source region.
摘要翻译：磁性随机存取存储器（MRAM）器件增加了用于感测引脚依赖隧道（SDT）器件的状态的DeltaR / R。 MRAM器件包括连接到读取线的多个晶体管，用于感测SDT器件的状态。多个晶体管在读取期间降低潜在电阻，增加DeltaR / R。多个晶体管可以共享源极区域。

4. 发明授权

US5757719A Page-mode memory device with multiple-level memory cells 失效
标题翻译：具有多级存储单元的页模式存储器件
公开(公告)号：US5757719A
公开(公告)日：1998-05-26
申请号：US869208
申请日：1997-06-05
申请人： Cristiano Calligaro , Roberto Gastaldi , Alessandro Manstretta , Paolo Cappelletti , Guido Torelli
发明人： Cristiano Calligaro , Roberto Gastaldi , Alessandro Manstretta , Paolo Cappelletti , Guido Torelli
IPC分类号： G11C16/02 , G11C11/56 , G11C13/00
CPC分类号： G11C11/5621 , G11C11/5642 , G11C2211/5632 , G11C2211/5634
摘要： A page-mode semiconductor memory device comprises a matrix of memory cells arranged in rows and columns, each row forming a memory page of the memory device and comprising at least one group of memory cells, memory page selection means for selecting a row of the matrix, and a plurality of sensing circuits each one associated with a respective column of the matrix. The memory cells are multiple-level memory cells which can be programmed in a plurality of c=2b(b>1) programming states to store b information bits, and the sensing circuits are serial-dichotomic sensing circuits capable of determining, in a number b of consecutive approximation steps, the b information bits stored in the memory cells, at each step one of said b information bits being determined, said at least one group of memory cells of a row forming a number b of memory words of a memory page.
摘要翻译：页模式半导体存储器件包括以行和列排列的存储器单元矩阵，每行形成存储器件的存储器页，并且包括至少一组存储器单元，存储器页选择装置，用于选择矩阵的一行，以及多个感测电路，每个感测电路与矩阵的相应列相关联。存储器单元是可以以多个c = 2b（b> 1）编程状态编程以存储b个信息位的多级存储器单元，并且感测电路是能够以数字确定的串行二分感测电路 b个连续近似步骤，存储在存储器单元中的b个信息位，在所确定的所述b个信息位的每个步骤中，所述至少一组形成存储器页的存储器字数b的存储单元组。

5. 发明授权

US5926416A Electrically programmable non-volatile memory cells device for a reduced number of programming cycles 失效
标题翻译：用于减少编程周期数的电可编程非易失性存储单元器件
公开(公告)号：US5926416A
公开(公告)日：1999-07-20
申请号：US807574
申请日：1997-02-27
申请人： Bruno Beverina , Paolo Cappelletti , Roberto Gastaldi
发明人： Bruno Beverina , Paolo Cappelletti , Roberto Gastaldi
IPC分类号： G11C16/12 , G11C16/14 , G11C16/04
CPC分类号： G11C16/14 , G11C16/12
摘要： A device incorporating electrically programmable nonvolatile memory cells for a small number of programming cycles, in which an individual cell is impressed, both during the write step and the erase step, a bias condition such that a charge flow can only occur between the drain region and the gate dielectric, and vice versa.
摘要翻译：在写入步骤和擦除步骤期间，在写入步骤和擦除步骤期间，将电子可编程的非易失性存储单元结合在少量编程周期中，其中单个单元被施加，偏置条件使得电荷流只能在漏区和栅极电介质，反之亦然。

6. 发明申请

US20100155804A1 Shallow Trench Isolation For A Memory 有权
标题翻译：浅沟槽隔离用于记忆
公开(公告)号：US20100155804A1
公开(公告)日：2010-06-24
申请号：US12341002
申请日：2008-12-22
申请人： Alessandro Grossi , Marcello Mariani , Paolo Cappelletti
发明人： Alessandro Grossi , Marcello Mariani , Paolo Cappelletti
IPC分类号： H01L29/788 , H01L21/336 , G11C11/34
CPC分类号： H01L29/788 , H01L27/11521 , H01L29/42324 , H01L29/7881
摘要： In some embodiments, a gate structure with a spacer on its side may be used as a mask to form self-aligned trenches in a microelectronic memory, such as a flash memory. A first portion of the gate structure may be used to form the mask, together with sidewall spacers, in some embodiments. Then, after forming the shallow trench isolations, a second portion of the gate structure may be added to form a mushroom shaped gate structure.
摘要翻译：在一些实施例中，具有在其侧面上的间隔物的栅极结构可以用作掩模以在诸如闪存的微电子存储器中形成自对准沟槽。在一些实施例中，门结构的第一部分可以用于与侧壁间隔物一起形成掩模。然后，在形成浅沟槽隔离物之后，可以添加栅极结构的第二部分以形成蘑菇形门结构。

7. 发明授权

US07304485B2 Analysis of the quality of contacts and vias in multi-metal fabrication processes of semiconductor devices, method and test chip architecture 有权
标题翻译：分析半导体器件多金属制造工艺中的触点和通孔的质量，方法和测试芯片架构
公开(公告)号：US07304485B2
公开(公告)日：2007-12-04
申请号：US10850834
申请日：2004-05-21
申请人： Paolo Cappelletti , Alfonso Maurelli
发明人： Paolo Cappelletti , Alfonso Maurelli
IPC分类号： G01R31/28
CPC分类号： H01L22/34 , G01R31/2853 , G01R31/2884 , G11C29/02 , G11C29/022 , G11C29/025 , H01L2924/0002 , H01L2924/00
摘要： A test chip performs measurements to evaluate the performances of interconnects. In particular, the statistical failure distribution, the electromigration and the leakage current are measured. An algorithm detects a via failure at any of the available n metal layers. The test chip includes a ROM memory array. The vias to be measured are formed in the columns of the array. Via or contact failures are detected by forcing a predetermined current through both an array column and a reference column. The failure analysis is obtained by comparing the resulting voltage drops.
摘要翻译：测试芯片执行测量以评估互连的性能。特别地，测量统计失效分布，电迁移和漏电流。算法检测任何可用的n个金属层的通孔故障。测试芯片包括ROM存储器阵列。要测量的通孔在阵列的列中形成。通过强制通过阵列列和参考列的预定电流来检测通过或接触故障。通过比较所得的电压降来获得故障分析。

8. 发明授权

US5850092A FLASH-EPROM with embedded EEPROM 失效
公开(公告)号：US5850092A
公开(公告)日：1998-12-15
申请号：US833925
申请日：1997-04-10
申请人： Paolo Cappelletti
发明人： Paolo Cappelletti
IPC分类号： G11C17/00 , G11C11/00 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11517 , G11C11/005 , G11C16/0408 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： Cost-efficient integration of a fully-featured EEPROM memory block in a FLASH-EPROM memory device, fabricated according to a low supply voltage and low power consumption FLASH-EPROM process, is made possible by a special structure of the EEPROM cells whereby the capacitive coupling between the floating gate and the control gate of the cell is realized over the field oxide adjacent to the active area of the cell. The process of the invention permits an optimized modulation of the thicknesses of the different tunnel and gate oxides of the FLASH-EPROM and EEPROM cells, as well as of the transistors of the peripheral circuitry of the two memory blocks destined to work with a relatively low supply voltage or with a boosted voltage.

9. 发明授权

US06172908B2 Controlled hot-electron writing method for non-volatile memory cells 有权
标题翻译：用于非易失性存储单元的受控热电子写入方法
公开(公告)号：US06172908B2
公开(公告)日：2001-01-09
申请号：US09169239
申请日：1998-10-08
申请人： Paolo Cappelletti , Bruno Ricco , David Esseni
发明人： Paolo Cappelletti , Bruno Ricco , David Esseni
IPC分类号： G11C1300
CPC分类号： G11C16/10 , G11C11/5621 , G11C11/5628 , G11C16/12
摘要： In order to optimize writing of the cell, the latter is written in a condition of equilibrium between an injection current Ig and the displacement current CppVsl. In this way, during writing, the voltage of the floating gate region Vfl remains constant, as does the drain current and the rise in the threshold voltage. In particular, both for programming and for soft-writing after erasure, the substrate of the cell is biased at a negative voltage Vsb with respect to the source region, and the control gate region of the cell receives a ramp voltage Vcg with a selected predetermined inclination Vsl satisfying an equilibrium condition Vsl
摘要翻译：为了优化电池的写入，后者被写入注入电流Ig和位移电流CppVsl之间的平衡状态。以这种方式，在写入期间，浮栅区域Vfl的电压与漏极电流和阈值电压的上升一样保持恒定。特别地，对于擦除后的编程和软写入，单元的基板相对于源极区域被偏置为负电压Vsb，单元的控制栅极区域接收具有所选预定的斜坡电压Vcg 倾斜度Vs1满足平衡条件Vs1

10. 发明授权

US6147380A Floating gate non-volatile memory cell with low erasing voltage and having different potential barriers 有权
标题翻译：具有低擦除电压并具有不同势垒的浮栅非易失性存储单元
公开(公告)号：US6147380A
公开(公告)日：2000-11-14
申请号：US521867
申请日：2000-03-08
申请人： Paolo Cappelletti
发明人： Paolo Cappelletti
IPC分类号： H01L21/8247 , H01L21/28 , H01L27/115 , H01L29/423 , H01L29/49 , H01L29/51 , H01L29/788 , H01L29/792
CPC分类号： H01L21/28185 , H01L21/28176 , H01L21/28194 , H01L21/28202 , H01L21/2822 , H01L29/42332 , H01L29/42336 , H01L29/49 , H01L29/495 , H01L29/513 , H01L29/518
摘要： A non-volatile memory cell of the type which includes at least one floating gate transistor and which is realized over a semiconductor substrate includes a source region, and a drain region, separated by a channel region which is overlaid by a thin layer of gate oxide. The gate oxide isolates a floating gate region from the substrate. The floating gate region is coupled to a control gate terminal. The floating gate region of the memory cell develops a first potential barrier between the semiconductor substrate and the gate oxide layer, and a second different potential barrier between the floating gate region and the gate oxide.
摘要翻译：包括至少一个浮栅晶体管并且在半导体衬底上实现的类型的非易失性存储单元包括源极区和漏极区，该沟道区由覆盖有栅极氧化物的薄层。栅极氧化物从衬底隔离浮栅区域。浮栅区域耦合到控制栅极端子。存储单元的浮置栅极区域在半导体衬底和栅极氧化物层之间形成第一势垒，并且在浮置栅极区域和栅极氧化物之间形成第二个不同的势垒。

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