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1. 发明申请

US20100155804A1 Shallow Trench Isolation For A Memory 有权
标题翻译：浅沟槽隔离用于记忆
公开(公告)号：US20100155804A1
公开(公告)日：2010-06-24
申请号：US12341002
申请日：2008-12-22
申请人： Alessandro Grossi , Marcello Mariani , Paolo Cappelletti
发明人： Alessandro Grossi , Marcello Mariani , Paolo Cappelletti
IPC分类号： H01L29/788 , H01L21/336 , G11C11/34
CPC分类号： H01L29/788 , H01L27/11521 , H01L29/42324 , H01L29/7881
摘要： In some embodiments, a gate structure with a spacer on its side may be used as a mask to form self-aligned trenches in a microelectronic memory, such as a flash memory. A first portion of the gate structure may be used to form the mask, together with sidewall spacers, in some embodiments. Then, after forming the shallow trench isolations, a second portion of the gate structure may be added to form a mushroom shaped gate structure.
摘要翻译：在一些实施例中，具有在其侧面上的间隔物的栅极结构可以用作掩模以在诸如闪存的微电子存储器中形成自对准沟槽。在一些实施例中，门结构的第一部分可以用于与侧壁间隔物一起形成掩模。然后，在形成浅沟槽隔离物之后，可以添加栅极结构的第二部分以形成蘑菇形门结构。

2. 发明授权

US07304485B2 Analysis of the quality of contacts and vias in multi-metal fabrication processes of semiconductor devices, method and test chip architecture 有权
标题翻译：分析半导体器件多金属制造工艺中的触点和通孔的质量，方法和测试芯片架构
公开(公告)号：US07304485B2
公开(公告)日：2007-12-04
申请号：US10850834
申请日：2004-05-21
申请人： Paolo Cappelletti , Alfonso Maurelli
发明人： Paolo Cappelletti , Alfonso Maurelli
IPC分类号： G01R31/28
CPC分类号： H01L22/34 , G01R31/2853 , G01R31/2884 , G11C29/02 , G11C29/022 , G11C29/025 , H01L2924/0002 , H01L2924/00
摘要： A test chip performs measurements to evaluate the performances of interconnects. In particular, the statistical failure distribution, the electromigration and the leakage current are measured. An algorithm detects a via failure at any of the available n metal layers. The test chip includes a ROM memory array. The vias to be measured are formed in the columns of the array. Via or contact failures are detected by forcing a predetermined current through both an array column and a reference column. The failure analysis is obtained by comparing the resulting voltage drops.
摘要翻译：测试芯片执行测量以评估互连的性能。特别地，测量统计失效分布，电迁移和漏电流。算法检测任何可用的n个金属层的通孔故障。测试芯片包括ROM存储器阵列。要测量的通孔在阵列的列中形成。通过强制通过阵列列和参考列的预定电流来检测通过或接触故障。通过比较所得的电压降来获得故障分析。

3. 发明授权

US5850092A FLASH-EPROM with embedded EEPROM 失效
公开(公告)号：US5850092A
公开(公告)日：1998-12-15
申请号：US833925
申请日：1997-04-10
申请人： Paolo Cappelletti
发明人： Paolo Cappelletti
IPC分类号： G11C17/00 , G11C11/00 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11517 , G11C11/005 , G11C16/0408 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： Cost-efficient integration of a fully-featured EEPROM memory block in a FLASH-EPROM memory device, fabricated according to a low supply voltage and low power consumption FLASH-EPROM process, is made possible by a special structure of the EEPROM cells whereby the capacitive coupling between the floating gate and the control gate of the cell is realized over the field oxide adjacent to the active area of the cell. The process of the invention permits an optimized modulation of the thicknesses of the different tunnel and gate oxides of the FLASH-EPROM and EEPROM cells, as well as of the transistors of the peripheral circuitry of the two memory blocks destined to work with a relatively low supply voltage or with a boosted voltage.

4. 发明授权

US5612913A Byte erasable EEPROM fully compatible with a single power supply flash-EPROM process 失效
标题翻译：字节可擦除EEPROM完全兼容单电源闪存EPROM过程
公开(公告)号：US5612913A
公开(公告)日：1997-03-18
申请号：US533631
申请日：1995-09-25
申请人： Paolo Cappelletti , Giulio Casagrande
发明人： Paolo Cappelletti , Giulio Casagrande
IPC分类号： G11C17/00 , G11C16/04 , G11C16/16 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C7/00
CPC分类号： H01L27/115 , G11C16/0416 , G11C16/16
摘要： A byte erasable memory with an EEPROM type functionality that can be integrated in a fully compatible way with a standard FLASH process is composed by a matrix of FLASH cells organized in n bytes, each of m bits, addressable through a plurality of wordlines and bitlines. The EEPROM-type memory has an auxiliary selection structure composed of an n number of byte select transistors, a plurality of individually selectable source biasing lines and a plurality of select lines in the same number of the wordlines and selectable in a biunivocal way with the wordlines. The cells of a byte have a common source that is accessed and individually selectable through the respective select transistor. EEPROM functionality is obtained without any modification of the standard FLASH fabrication process by splitting the voltage applied between a control gate and the respective common source region of the cells that compose a certain selected byte about a common ground potential, during a byte erasing phase thus reducing the electrical stress induced on deselected cells.
摘要翻译：具有可以以完全兼容的方式与标准FLASH处理集成的EEPROM类型功能的字节可擦除存储器由以n字节组织的FLASH单元矩阵组成，每个m位可通过多个字线和位线寻址。 EEPROM型存储器具有由n个字节选择晶体管组成的辅助选择结构，多个单独可选择的源极偏置线和相同数量的字线中的多条选择线，并且可以与字线双向地选择。一个字节的单元具有通过相应选择晶体管访问和单独选择的公共源。在字节擦除阶段期间，通过将施加在控制栅极和组成关于公共接地电位的特定选定字节的单元的各个公共源极区域之间施加的电压分开来获得EEPROM功能，从而减少了EEPROM功能。在取消细胞上诱导的电应激。

5. 发明授权

US06172908B2 Controlled hot-electron writing method for non-volatile memory cells 有权
标题翻译：用于非易失性存储单元的受控热电子写入方法
公开(公告)号：US06172908B2
公开(公告)日：2001-01-09
申请号：US09169239
申请日：1998-10-08
申请人： Paolo Cappelletti , Bruno Ricco , David Esseni
发明人： Paolo Cappelletti , Bruno Ricco , David Esseni
IPC分类号： G11C1300
CPC分类号： G11C16/10 , G11C11/5621 , G11C11/5628 , G11C16/12
摘要： In order to optimize writing of the cell, the latter is written in a condition of equilibrium between an injection current Ig and the displacement current CppVsl. In this way, during writing, the voltage of the floating gate region Vfl remains constant, as does the drain current and the rise in the threshold voltage. In particular, both for programming and for soft-writing after erasure, the substrate of the cell is biased at a negative voltage Vsb with respect to the source region, and the control gate region of the cell receives a ramp voltage Vcg with a selected predetermined inclination Vsl satisfying an equilibrium condition Vsl
摘要翻译：为了优化电池的写入，后者被写入注入电流Ig和位移电流CppVsl之间的平衡状态。以这种方式，在写入期间，浮栅区域Vfl的电压与漏极电流和阈值电压的上升一样保持恒定。特别地，对于擦除后的编程和软写入，单元的基板相对于源极区域被偏置为负电压Vsb，单元的控制栅极区域接收具有所选预定的斜坡电压Vcg 倾斜度Vs1满足平衡条件Vs1

6. 发明授权

US6147380A Floating gate non-volatile memory cell with low erasing voltage and having different potential barriers 有权
标题翻译：具有低擦除电压并具有不同势垒的浮栅非易失性存储单元
公开(公告)号：US6147380A
公开(公告)日：2000-11-14
申请号：US521867
申请日：2000-03-08
申请人： Paolo Cappelletti
发明人： Paolo Cappelletti
IPC分类号： H01L21/8247 , H01L21/28 , H01L27/115 , H01L29/423 , H01L29/49 , H01L29/51 , H01L29/788 , H01L29/792
CPC分类号： H01L21/28185 , H01L21/28176 , H01L21/28194 , H01L21/28202 , H01L21/2822 , H01L29/42332 , H01L29/42336 , H01L29/49 , H01L29/495 , H01L29/513 , H01L29/518
摘要： A non-volatile memory cell of the type which includes at least one floating gate transistor and which is realized over a semiconductor substrate includes a source region, and a drain region, separated by a channel region which is overlaid by a thin layer of gate oxide. The gate oxide isolates a floating gate region from the substrate. The floating gate region is coupled to a control gate terminal. The floating gate region of the memory cell develops a first potential barrier between the semiconductor substrate and the gate oxide layer, and a second different potential barrier between the floating gate region and the gate oxide.
摘要翻译：包括至少一个浮栅晶体管并且在半导体衬底上实现的类型的非易失性存储单元包括源极区和漏极区，该沟道区由覆盖有栅极氧化物的薄层。栅极氧化物从衬底隔离浮栅区域。浮栅区域耦合到控制栅极端子。存储单元的浮置栅极区域在半导体衬底和栅极氧化物层之间形成第一势垒，并且在浮置栅极区域和栅极氧化物之间形成第二个不同的势垒。

7. 发明授权

US5942004A Device and a method for storing data and corresponding error-correction information 失效
标题翻译：装置和存储数据的方法以及相应的纠错信息
公开(公告)号：US5942004A
公开(公告)日：1999-08-24
申请号：US550557
申请日：1995-10-31
申请人： Paolo Cappelletti
发明人： Paolo Cappelletti
IPC分类号： G06F12/16 , G06F11/10 , G11C7/00 , G11C11/56 , G11C29/42 , G11C29/00
CPC分类号： G06F11/1072 , G11C11/56 , G11C29/00
摘要： The invention relates to a multi-level storage device including: at least a first plurality of cells storing an identical first number (greater than one) of binary data, and at least a corresponding for second plurality of cells for storing a second number of error check and correcting words equal to said first number, said words being respectively associated with sets of binary data, each including at least one binary data for each cell in said first plurality. In this way, many of the known error correction algorithms can be applied to obtain comparable results to those provided by binary memories. In addition, where multi-level cells are used for storing the error check and correcting words, the device dimension requirements can also be comparable.
摘要翻译：本发明涉及一种多级存储设备，包括：至少第一多个单元存储二进制数据的相同的第一数量（大于一个），以及至少相应于用于存储第二数量的错误的第二多个单元检查和纠正等于所述第一号码的字，所述字分别与二进制数据的集合相关联，每个二进制数据包括所述第一多个中的每个小区的至少一个二进制数据。以这种方式，可以应用许多已知的纠错算法来获得与二进制存储器提供的结果相当的结果。另外，当多层单元用于存储错误检查和纠正单词时，设备尺寸要求也可以相当。

8. 发明申请

US20070126064A1 Transistor structure with high input impedance and high current capability and manufacturing process thereof 有权
标题翻译：具有高输入阻抗和高电流能力的晶体管结构及其制造工艺
公开(公告)号：US20070126064A1
公开(公告)日：2007-06-07
申请号：US11605190
申请日：2006-11-27
申请人： Fabio Pellizzer , Paolo Cappelletti
发明人： Fabio Pellizzer , Paolo Cappelletti
IPC分类号： H01L31/00
CPC分类号： H01L27/24 , G11C13/0004 , G11C13/003 , G11C2213/74 , G11C2213/76 , G11C2213/79 , H01L21/8249 , H01L27/0705
摘要： An integrated transistor device is formed in a chip of semiconductor material having an electrical-insulation region delimiting an active area accommodating a bipolar transistor of vertical type and a MOSFET of planar type, contiguous to one another. The active area accommodates a collector region; a bipolar base region contiguous to the collector region; an emitter region within the bipolar base region; a source region, arranged at a distance from the bipolar base region; a drain region; a channel region arranged between the source region and the drain region; and a well region. The drain region and the bipolar base region are contiguous and form a common base structure shared by the bipolar transistor and the MOSFET. Thereby, the integrated transistor device has a high input impedance and is capable of driving high currents, while only requiring a small integration area.
摘要翻译：集成晶体管器件形成在半导体材料的芯片中，其具有限定容纳垂直型双极晶体管的有源区域的电绝缘区域和彼此相邻的平面型MOSFET。活动区域容纳收集区域; 与集电极区域相邻的双极基极区域; 在双极基区内的发射极区; 源极区域，布置在距离双极基极区域一定距离处; 漏区; 布置在源极区域和漏极区域之间的沟道区域; 和一个井区。漏极区域和双极基极区域是连续的，并且形成由双极晶体管和MOSFET共享的公共基极结构。因此，集成晶体管器件具有高输入阻抗并且能够驱动高电流，同时仅需要小的积分面积。

9. 发明授权

US06841445B2 Method of making floating gate non-volatile memory cell with low erasing voltage having double layer gate dielectric 失效
标题翻译：制造具有双层栅电介质的低擦除电压的浮栅非易失性存储单元的方法
公开(公告)号：US06841445B2
公开(公告)日：2005-01-11
申请号：US10792308
申请日：2004-03-03
申请人： Paolo Cappelletti
发明人： Paolo Cappelletti
IPC分类号： H01L21/8247 , H01L21/28 , H01L27/115 , H01L29/423 , H01L29/49 , H01L29/51 , H01L29/788 , H01L29/792 , H01L21/336
CPC分类号： H01L21/28185 , H01L21/28176 , H01L21/28194 , H01L21/28202 , H01L21/2822 , H01L29/42332 , H01L29/42336 , H01L29/49 , H01L29/495 , H01L29/513 , H01L29/518
摘要： A non-volatile memory cell of the type which includes at least one floating gate transistor and which is realized over a semiconductor substrate includes a source region, and a drain region, separated by a channel region which is overlaid by a thin layer of gate oxide. The gate oxide isolates a floating gate region from the substrate. The floating gate region is coupled to a control gate terminal. The floating gate region of the memory cell develops a first potential barrier between the semiconductor substrate and the gate oxide layer, and a second different potential barrier between the floating gate region and the gate oxide.
摘要翻译：包括至少一个浮栅晶体管并且在半导体衬底上实现的类型的非易失性存储单元包括源极区和漏极区，该沟道区由覆盖有栅极氧化物的薄层。栅极氧化物从衬底隔离浮栅区域。浮栅区域耦合到控制栅极端子。存储单元的浮置栅极区域在半导体衬底和栅极氧化物层之间形成第一势垒，并且在浮置栅极区域和栅极氧化物之间形成第二个不同的势垒。

10. 发明授权

US06710394B2 Method of making floating gate non-volatile memory cell with low erasing voltage having double layer gate dielectric 有权
标题翻译：制造具有双层栅电介质的低擦除电压的浮栅非易失性存储单元的方法
公开(公告)号：US06710394B2
公开(公告)日：2004-03-23
申请号：US10158706
申请日：2002-05-30
申请人： Paolo Cappelletti
发明人： Paolo Cappelletti
IPC分类号： H01L2976
CPC分类号： H01L21/28185 , H01L21/28176 , H01L21/28194 , H01L21/28202 , H01L21/2822 , H01L29/42332 , H01L29/42336 , H01L29/49 , H01L29/495 , H01L29/513 , H01L29/518
摘要： A non-volatile memory cell of the type which includes at least one floating gate transistor and which is realized over a semiconductor substrate includes a source region, and a drain region, separated by a channel region which is overlaid by a thin layer of gate oxide. The gate oxide isolates a floating gate region from the substrate. The floating gate region is coupled to a control gate terminal. The floating gate region of the memory cell develops a first potential barrier between the semiconductor substrate and the gate oxide layer, and a second different potential barrier between the floating gate region and the gate oxide.
摘要翻译：包括至少一个浮栅晶体管并且在半导体衬底上实现的类型的非易失性存储单元包括源极区和漏极区，该沟道区由覆盖有栅极氧化物的薄层。栅极氧化物从衬底隔离浮栅区域。浮栅区域耦合到控制栅极端子。存储单元的浮置栅极区域在半导体衬底和栅极氧化物层之间形成第一势垒，并且在浮置栅极区域和栅极氧化物之间形成第二个不同的势垒。

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