专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080255461A1 Real-time optical monitoring system and method for thermal therapy treatment 审中-公开
标题翻译：实时光学监测系统及热疗治疗方法
公开(公告)号：US20080255461A1
公开(公告)日：2008-10-16
申请号：US12079418
申请日：2008-03-26
申请人： Robert Weersink , Lee Chin , John Trachtenberg , Alex Vitkin , William Whelan , Brian C. Wilson
发明人： Robert Weersink , Lee Chin , John Trachtenberg , Alex Vitkin , William Whelan , Brian C. Wilson
IPC分类号： A61B5/00 , A61B18/18
CPC分类号： A61B18/24 , A61B5/0084 , A61B5/0086 , A61B2562/0233 , A61B2562/043 , A61B2562/228
摘要： Multiple site information of light intensity is obtained by application of a multiple-fibre probe in a real-time optical monitoring system. The multiple-fibre probe includes a plurality of optical fibres distributed along the length of the probe. Each optical fibre may be is switchable between the mode for transmitting optical signal into the malignant tissue and the mode for collecting the optical signal from the same tissue. Thus the numbers of the probes can be minimized for collecting multiple site light information and the irritation to the tissue is reduced. A method of using such a probe to determine coagulated boundary in thermal or other treatment is also described.
摘要翻译：通过在实时光学监控系统中应用多光纤探头获得光强度的多个位置信息。多光纤探头包括沿着探头的长度分布的多根光纤。每个光纤可以在用于将光信号发送到恶性组织的模式和从相同组织收集光信号的模式之间切换。因此，可以将探针的数量最小化以收集多个位点光信息，并减少对组织的刺激。还描述了使用这种探针以确定热或其它处理中的凝固边界的方法。

2. 发明申请

US20080285913A1 Method and apparatus for high resolution coherent optical imaging 审中-公开
标题翻译：用于高分辨率相干光学成像的方法和装置
公开(公告)号：US20080285913A1
公开(公告)日：2008-11-20
申请号：US11825008
申请日：2007-07-03
申请人： Victor Xiao Dong Yang , I. Alex Vitkin , Louie M. WongKeeSong , Sharon Katz , Margaret Leslie Gordon , Brian C. Wilson , Alvin Ho Kwan Mok
发明人： Victor Xiao Dong Yang , I. Alex Vitkin , Louie M. WongKeeSong , Sharon Katz , Margaret Leslie Gordon , Brian C. Wilson , Alvin Ho Kwan Mok
IPC分类号： G02B6/28
CPC分类号： A61B5/6852 , A61B1/00096 , A61B1/00172 , A61B1/05 , A61B5/0066 , G01N21/4795
摘要： A method and an apparatus for examining the sub-surface microstructure of a sample are provided. Radiation from a plurality of optical radiation sources travels along a first optical path. In the first optical path, a device focuses the optical radiation from each of the optical sources into a plurality of respective focal points along the first optical path to provide substantially continuous coverage of a selected portion of the first optical path. Then, a sample on the first optical path within the selected length extending into the sample is scanned along said selected portion of the first optical path.
摘要翻译：提供了一种用于检查样品的亚表面微观结构的方法和装置。来自多个光辐射源的辐射沿着第一光路行进。在第一光路中，设备将来自每个光源的光辐射沿着第一光路聚焦到多个相应的焦点中，以提供第一光路的选定部分的基本连续的覆盖。然后，沿着第一光路的所述选定部分扫描延伸到样品中的所选长度内的第一光路上的样品。

3. 发明授权

US07242833B2 Method and apparatus for high resolution coherent optical imaging 有权
标题翻译：用于高分辨率相干光学成像的方法和装置
公开(公告)号：US07242833B2
公开(公告)日：2007-07-10
申请号：US10311358
申请日：2001-07-10
申请人： Victor Xiao Dong Yang , I. Alex Vitkin , Louis M. WongKeeSong , Sharon Katz , Margaret Leslie Gordon , Brian C. Wilson , Alvin Ho Kwan Mok
发明人： Victor Xiao Dong Yang , I. Alex Vitkin , Louis M. WongKeeSong , Sharon Katz , Margaret Leslie Gordon , Brian C. Wilson , Alvin Ho Kwan Mok
IPC分类号： G02B6/04 , A61B1/07
CPC分类号： A61B5/6852 , A61B1/00096 , A61B1/00172 , A61B1/05 , A61B5/0066 , G01N21/4795
摘要： A method and an apparatus for examining the subsurface microstructure of a sample are provided. Radiation from a plurality of optical radiation sources travels along a first optical path. In the first optical path, a device focuses the optical radiati n from each of the optical sources into a plurality of respective focal points along the first optical path to provide substantially continuous coverage of a selected portion of the first optical path. Then, a sample on the first optical path within the selected length extending into the sample is scanned along said selected portion of the first optical path.
摘要翻译：提供了一种用于检查样品的地下微结构的方法和装置。来自多个光辐射源的辐射沿着第一光路行进。在第一光路中，器件将光学辐射从每个光源聚焦到沿着第一光路的多个相应的焦点中，以提供对第一光路的选定部分的基本连续的覆盖。然后，沿着第一光路的所述选定部分扫描延伸到样品中的所选长度内的第一光路上的样品。

4. 发明申请

US20160287211A1 System and Method for Multi-Modal in Vivo Imaging 审中-公开
标题翻译：多模态体内成像的系统和方法
公开(公告)号：US20160287211A1
公开(公告)日：2016-10-06
申请号：US15085380
申请日：2016-03-30
申请人： Ralph S. DaCosta , Brian C. Wilson , Israel Veilleux , Jin Ho Chang , Jeeun Kang , Yangmo Yoo , Tai-Kyong Song
发明人： Ralph S. DaCosta , Brian C. Wilson , Israel Veilleux , Jin Ho Chang , Jeeun Kang , Yangmo Yoo , Tai-Kyong Song
IPC分类号： A61B8/00 , A61B8/08 , A61B8/14
CPC分类号： A61B8/4416 , A61B5/0035 , A61B5/0071 , A61B5/0095 , A61B5/7425 , A61B8/13 , A61B8/14 , A61B8/145 , A61B8/4405 , A61B8/4444 , A61B8/4472 , A61B8/48 , A61B8/5261 , G06T7/0012
摘要： Various embodiments are described herein for a method, apparatus and system for performing multi-modal imaging using a common imaging probe having various modes of operation including a fluorescent (FL) imaging mode and at least one of an ultrasound (US) imaging mode, a photoacoustic (PA) imaging mode and a combined US/PA imaging mode. Molecular/functional information may be obtained from FL and PA imaging and anatomical information may be obtained from ultrasound (US) imaging. The system may be implemented to provide for images from each modality in real time as well as provide for co-registration of these images. Experimental results demonstrate that combining the imaging modalities does not significantly compromise the performance of each of the separate US, PA, and FL imaging techniques, while enabling multi-modality registration.
摘要翻译：在这里描述了用于使用具有各种操作模式的共同成像探头进行多模态成像的方法，装置和系统，包括荧光（FL）成像模式和超声（US）成像模式，光声（PA）成像模式和US / PA成像模式组合。可以从FL和PA成像获得分子/功能信息，并且可以从超声（US）成像获得解剖信息。可以实施该系统以实时地提供来自每个模态的图像，以及提供这些图像的共同配准。实验结果表明，组合成像模式并不会显着损害每个单独的美国，美国和加拿大成像技术的性能，同时实现多模式注册。

5. 发明申请

US20150278963A1 Electronic trading cards and method of use 审中-公开
标题翻译：电子交易卡及使用方法
公开(公告)号：US20150278963A1
公开(公告)日：2015-10-01
申请号：US14671275
申请日：2015-03-27
申请人： Kendall R. Nishimine , Thomas J. Marbois , Brian C. Wilson
发明人： Kendall R. Nishimine , Thomas J. Marbois , Brian C. Wilson
IPC分类号： G06Q50/00 , H04L29/08 , H04W4/02 , G06Q30/02
CPC分类号： G06Q50/01 , G06Q30/0222 , H04L67/1095 , H04L67/18 , H04W4/023
摘要： An electronic trading card is disclosed. The trading card can operate using all the convention social media platforms, and allows for a more personal interaction between celebrities and their fans. The cards can have one or more images, with additional images being available for purchase, through trading, or given away by the star for free or as rewards for fan loyalty. Through the cards, fans and celebrities can exchange messages and videos, and celebrities can allow a fan to follow their daily routine to a greater or lesser extent. Third parties can analyze the data from the star/fan interactions and advise the star on managing his/her public image, and allowing merchandisers to more accurately target their advertising and promotional campaigns.
摘要翻译：披露电子交易卡。交易卡可以使用所有常规的社交媒体平台进行操作，并允许名人和他们的粉丝之间进行更多的个人互动。这些卡可以有一个或多个图像，其他图像可以通过交易进行购买，或者由明星免费提供或作为粉丝忠诚度的奖励。通过卡片，歌迷和名人可以交换信息和视频，名人可以让粉丝或多或少地遵循他们的日常生活。第三方可以分析来自明星/粉丝互动的数据，并在管理他/她的公开形象时告知明星，并允许商家更准确地定位他们的广告和促销活动。

6. 发明授权

US08418108B2 Accuracy pin-slew mode for gate delay calculation 失效
标题翻译：用于门延迟计算的精度针脚转换模式
公开(公告)号：US08418108B2
公开(公告)日：2013-04-09
申请号：US13162806
申请日：2011-06-17
申请人： Charles J. Alpert , Zhuo Li , Gi-Joon Nam , David A. Papa , Chin Ngai Sze , Natarajan Viswanathan , Brian C. Wilson
发明人： Charles J. Alpert , Zhuo Li , Gi-Joon Nam , David A. Papa , Chin Ngai Sze , Natarajan Viswanathan , Brian C. Wilson
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5031 , G06F2217/84
摘要： The input slew at a selected gate of an integrated circuit design is computed by assigning a default slew rate to the output gate of a previous logic stage which is greater than a median slew rate for the design. This default slew rate is propagated through the logic stage to generate an input slew rate at the selected gate. The default slew rate corresponds to a predetermined percentile applied to a limited sample of preliminary slew rates for randomly selected gates in the design. The default slew rate is adjusted as a function of known characteristics of the wirelength from the output gate to a first gate in the second logic stage. The delay of the selected gate is calculated based on the input slew rate. The input slew rate can be stored during one optimization iteration and used as a default slew rate during a later optimization iteration.
摘要翻译：通过将默认转换速率分配给先前逻辑级的输出门，该值大于设计的中间转换速率来计算集成电路设计选定门的输入。该默认转换速率通过逻辑级传播，以在所选择的门产生输入转换速率。默认转换速率对应于应用于设计中随机选择的门的初步压摆率的有限样本的预定百分位数。作为第二逻辑级中从输出门到第一门的线长度的已知特性的函数调整默认转换速率。基于输入转换速率来计算所选择的门的延迟。输入转换速率可以在一次优化迭代期间存储，并在以后的优化迭代中用作默认转换速率。

7. 发明申请

US20110117025A1 DEVICE AND METHOD FOR FLUORESCENCE-BASED IMAGING AND MONITORING 有权
标题翻译：用于基于荧光成像和监测的装置和方法
公开(公告)号：US20110117025A1
公开(公告)日：2011-05-19
申请号：US12992040
申请日：2009-05-20
申请人： Ralph Sebastian Dacosta , Brian C. Wilson , Kai Zhang
发明人： Ralph Sebastian Dacosta , Brian C. Wilson , Kai Zhang
IPC分类号： A61B5/00 , G01N21/64 , C12M1/00 , C12Q1/02 , C12Q1/70 , C12Q1/00 , C12Q1/26 , C12Q1/37 , C12Q1/34 , A61B6/00 , B82Y15/00
CPC分类号： A61B5/0071 , A61B5/0042 , A61B5/0059 , A61B5/01 , A61B5/445 , A61B5/4519 , A61B5/72 , A61B5/742 , A61B10/00 , G01N21/6408 , G01N21/6456 , G01N21/6486 , G01N2021/6421 , G01N2021/6471 , G01N2201/0221 , Y02A90/26
摘要： A device for fluorescence-based imaging and monitoring of a target comprising: a light source emitting light for illuminating the target, the emitted light including at least one wavelength or wavelength band causing at least one biomarker associated with the target to fluoresce; and a light detector for detecting the fluorescence.
摘要翻译：一种用于靶基于荧光的成像和监测的装置，包括：发射用于照射靶的光的光源，包括至少一个波长或波长带的发射光使至少一个与靶相关的生物标志物发荧光; 以及用于检测荧光的光检测器。

8. 外观设计

USD390618S Water board 失效
公开(公告)号：USD390618S
公开(公告)日：1998-02-10
申请号：US72083
申请日：1997-06-18
申请人： Brian C. Wilson
设计人： Brian C. Wilson

9. 发明授权

US08407652B2 Task-based multi-process design synthesis 有权
标题翻译：基于任务的多进程设计综合
公开(公告)号：US08407652B2
公开(公告)日：2013-03-26
申请号：US12972879
申请日：2010-12-20
申请人： Anthony D. Drumm , Jagannathan Narasimhan , Lakshmi N. Reddy , Louise H. Trevillyan , Brian C. Wilson
发明人： Anthony D. Drumm , Jagannathan Narasimhan , Lakshmi N. Reddy , Louise H. Trevillyan , Brian C. Wilson
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A task-based multi-process design synthesis methodology relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. The child processes then notify the parent process of those objects that qualify as candidate objects, so that the parent process only has to perform the transform on the candidate objects, thereby relieving the parent process from the overhead associated with performing the transform on non-candidate objects for which the transform has been determined by the child processes as not being successful.
摘要翻译：基于任务的多进程设计合成方法依赖于多个子进程来辅助父进程对集成电路设计进行优化。来自集成电路设计的对象被分组成子集并被分配给子进程，每个子进程对分配给该子进程的子集中的每个对象执行变换，并且确定该子集中的哪些对象是候选对象变革的表现已经取得成功。然后，子进程通知那些符合候选对象的那些对象的父进程，以便父进程只需对候选对象执行转换，从而将父进程从与非候选对象执行转换相关的开销中解除子进程已将该转换确定为未成功的对象。

10. 发明授权

US08407638B2 Methods and apparatus for boolean equivalency checking in the presence of voting logic 有权
标题翻译：在存在投票逻辑的情况下进行布尔等价检查的方法和装置
公开(公告)号：US08407638B2
公开(公告)日：2013-03-26
申请号：US12355757
申请日：2009-01-16
申请人： Victor A. Acuna , Robert L. Kanzelman , Scott H. Mack , Brian C. Wilson
发明人： Victor A. Acuna , Robert L. Kanzelman , Scott H. Mack , Brian C. Wilson
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G01R31/31835
摘要： In a first aspect, a first method of designing a circuit is provided. The first method includes the steps of (1) providing a model of an original circuit design including a latch; (2) providing a model of a modified version of the original circuit design, wherein the modified version of the original circuit design includes a set of latches associated with the latch of the original circuit design and voting logic having inputs coupled to respective outputs of latches in the latch set; and (3) during Boolean equivalency checking (BEC), injecting an error on at most a largest minority of the inputs of the voting logic to test the voting logic function.
摘要翻译：在第一方面，提供了设计电路的第一种方法。第一种方法包括以下步骤：（1）提供包括闩锁的原始电路设计的模型; （2）提供原始电路设计的修改版本的模型，其中原始电路设计的修改版本包括与原始电路设计的锁存器相关联的一组锁存器和具有耦合到锁存器的相应输出的输入的投票逻辑在锁定组中; 和（3）在布尔等价性检查（BEC）期间，在表决逻辑的最多输入的最多少量输入错误，以测试投票逻辑功能。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式