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1. 发明申请

US20120324409A1 ACCURACY PIN-SLEW MODE FOR GATE DELAY CALCULATION 失效
标题翻译：门锁延迟计算的精度针脚模式
公开(公告)号：US20120324409A1
公开(公告)日：2012-12-20
申请号：US13162806
申请日：2011-06-17
申请人： Charles J. Alpert , Zhuo Li , Gi-Joon Nam , David A. Papa , Chin Ngai Sze , Natarajan Viswanathan , Brian C. Wilson
发明人： Charles J. Alpert , Zhuo Li , Gi-Joon Nam , David A. Papa , Chin Ngai Sze , Natarajan Viswanathan , Brian C. Wilson
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5031 , G06F2217/84
摘要： The input slew at a selected gate of an integrated circuit design is computed by assigning a default slew rate to the output gate of a previous logic stage which is greater than a median slew rate for the design. This default slew rate is propagated through the logic stage to generate an input slew rate at the selected gate. The default slew rate corresponds to a predetermined percentile applied to a limited sample of preliminary slew rates for randomly selected gates in the design. The default slew rate is adjusted as a function of known characteristics of the wirelength from the output gate to a first gate in the second logic stage. The delay of the selected gate is calculated based on the input slew rate. The input slew rate can be stored during one optimization iteration and used as a default slew rate during a later optimization iteration.
摘要翻译：通过将默认转换速率分配给先前逻辑级的输出门，该值大于设计的中间转换速率来计算集成电路设计选定门的输入。该默认转换速率通过逻辑级传播，以在所选择的门产生输入转换速率。默认转换速率对应于应用于设计中随机选择的门的初步压摆率的有限样本的预定百分位数。作为第二逻辑级中从输出门到第一门的线长度已知特性的函数调整默认转换速率。基于输入转换速率来计算所选择的门的延迟。输入转换速率可以在一次优化迭代期间存储，并在以后的优化迭代中用作默认转换速率。

2. 发明授权

US08418108B2 Accuracy pin-slew mode for gate delay calculation 失效
标题翻译：用于门延迟计算的精度针脚转换模式
公开(公告)号：US08418108B2
公开(公告)日：2013-04-09
申请号：US13162806
申请日：2011-06-17
申请人： Charles J. Alpert , Zhuo Li , Gi-Joon Nam , David A. Papa , Chin Ngai Sze , Natarajan Viswanathan , Brian C. Wilson
发明人： Charles J. Alpert , Zhuo Li , Gi-Joon Nam , David A. Papa , Chin Ngai Sze , Natarajan Viswanathan , Brian C. Wilson
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5031 , G06F2217/84
摘要： The input slew at a selected gate of an integrated circuit design is computed by assigning a default slew rate to the output gate of a previous logic stage which is greater than a median slew rate for the design. This default slew rate is propagated through the logic stage to generate an input slew rate at the selected gate. The default slew rate corresponds to a predetermined percentile applied to a limited sample of preliminary slew rates for randomly selected gates in the design. The default slew rate is adjusted as a function of known characteristics of the wirelength from the output gate to a first gate in the second logic stage. The delay of the selected gate is calculated based on the input slew rate. The input slew rate can be stored during one optimization iteration and used as a default slew rate during a later optimization iteration.
摘要翻译：通过将默认转换速率分配给先前逻辑级的输出门，该值大于设计的中间转换速率来计算集成电路设计选定门的输入。该默认转换速率通过逻辑级传播，以在所选择的门产生输入转换速率。默认转换速率对应于应用于设计中随机选择的门的初步压摆率的有限样本的预定百分位数。作为第二逻辑级中从输出门到第一门的线长度的已知特性的函数调整默认转换速率。基于输入转换速率来计算所选择的门的延迟。输入转换速率可以在一次优化迭代期间存储，并在以后的优化迭代中用作默认转换速率。

3. 发明申请

US20120124539A1 Clock Optimization with Local Clock Buffer Control Optimization 有权
标题翻译：时钟优化与本地时钟缓冲区控制优化
公开(公告)号：US20120124539A1
公开(公告)日：2012-05-17
申请号：US12947445
申请日：2010-11-16
申请人： Charles J. Alpert , Zhuo Li , Gi-Joon Nam , David A. Papa , Chin Ngai Sze , Natarajan Viswanathan
发明人： Charles J. Alpert , Zhuo Li , Gi-Joon Nam , David A. Papa , Chin Ngai Sze , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/62
摘要： A physical synthesis tool for dock optimization with local clock buffer control optimization is provided. The physical synthesis flow consists of delaying the exposure of clock routes until after the clock optimization placement stage. The physical synthesis tool clones first local clock buffers. Then, the physical synthesis tool runs timing analysis on the whole design to compute the impact of this necessarily disruptive step. After cloning local clock buffers, the physical synthesis tool adds an extra optimization step to target the control signals that drive the local clock buffers. This optimization step may includes latch cloning, timing-driven placement, buffer insertion, and repowering. The flow alleviates high-fanout nets and produces significantly better timing going into clock optimization placement. After placement, the physical synthesis tool fixes latches and local clock buffers in place, inserts clock routes, and repowers local clock buffers.
摘要翻译：提供了一种用于通过本地时钟缓冲器控制优化进行码头优化的物理综合工具。物理合成流程包括延迟时钟路由的曝光，直到时钟优化放置阶段为止。物理综合工具克隆了第一个本地时钟缓冲区。然后，物理综合工具对整个设计运行时序分析，以计算这一必然破坏性步骤的影响。在克隆本地时钟缓冲器之后，物理综合工具增加了一个额外的优化步骤来对驱动本地时钟缓冲器的控制信号进行目标。该优化步骤可以包括锁存克隆，定时驱动放置，缓冲器插入和重新供电。该流程减轻了高扇出网络，并显着提高了进入时钟优化布局的时间。放置后，物理综合工具将锁存器和本地时钟缓冲器固定到位，插入时钟路由并释放本地时钟缓冲区。

4. 发明授权

US08667441B2 Clock optimization with local clock buffer control optimization 有权
标题翻译：时钟优化与本地时钟缓冲控制优化
公开(公告)号：US08667441B2
公开(公告)日：2014-03-04
申请号：US12947445
申请日：2010-11-16
申请人： Charles J. Alpert , Zhuo Li , Gi-Joon Nam , David A. Papa , Chin Ngai Sze , Natarajan Viswanathan
发明人： Charles J. Alpert , Zhuo Li , Gi-Joon Nam , David A. Papa , Chin Ngai Sze , Natarajan Viswanathan
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/505 , G06F2217/62
摘要： A physical synthesis tool for dock optimization with local clock buffer control optimization is provided. The physical synthesis flow consists of delaying the exposure of clock routes until after the clock optimization placement stage. The physical synthesis tool clones first local clock buffers. Then, the physical synthesis tool runs timing analysis on the whole design to compute the impact of this necessarily disruptive step. After cloning local clock buffers, the physical synthesis tool adds an extra optimization step to target the control signals that drive the local clock buffers. This optimization step may includes latch cloning, timing-driven placement, buffer insertion, and repowering. The flow alleviates high-fanout nets and produces significantly better timing going into clock optimization placement. After placement, the physical synthesis tool fixes latches and local clock buffers in place, inserts clock routes, and repowers local clock buffers.
摘要翻译：提供了一种用于通过本地时钟缓冲器控制优化进行码头优化的物理综合工具。物理合成流程包括延迟时钟路由的曝光，直到时钟优化放置阶段为止。物理综合工具克隆了第一个本地时钟缓冲区。然后，物理综合工具对整个设计运行时序分析，以计算这一必然破坏性步骤的影响。在克隆本地时钟缓冲器之后，物理综合工具增加了一个额外的优化步骤来对驱动本地时钟缓冲器的控制信号进行目标。该优化步骤可以包括锁存克隆，定时驱动放置，缓冲器插入和重新供电。该流程减轻了高扇出网络，并显着提高了进入时钟优化布局的时间。放置后，物理综合工具将锁存器和本地时钟缓冲器固定到位，插入时钟路由并释放本地时钟缓冲区。

5. 发明申请

US20130326455A1 ELEMENT PLACEMENT IN CIRCUIT DESIGN BASED ON PREFERRED LOCATION 有权
标题翻译：基于优选位置的电路设计中的元件放置
公开(公告)号：US20130326455A1
公开(公告)日：2013-12-05
申请号：US13485828
申请日：2012-05-31
申请人： Charles J. Alpert , Gi-Joon Nam , Chin Ngai Sze , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles J. Alpert , Gi-Joon Nam , Chin Ngai Sze , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5068 , G06F17/5081
摘要： An improved circuit design system may include a computer processor to perform a placement for a circuit by physical synthesis. The system may also include a controller to compute a preferred location of at least one selected element of the circuit, and to calculate placement constraints for each selected element. The system may further include an updated design for the circuit generated by performing another round of physical synthesis with the placement constraints.
摘要翻译：改进的电路设计系统可以包括计算机处理器，以通过物理合成来执行电路的放置。该系统还可以包括控制器，用于计算电路的至少一个选定元件的优选位置，并且计算每个选定元件的放置约束。该系统可以进一步包括通过用放置约束执行另一轮物理合成而产生的电路的更新设计。

6. 发明授权

US09524363B2 Element placement in circuit design based on preferred location 有权
标题翻译：基于优选位置的电路设计元素放置
公开(公告)号：US09524363B2
公开(公告)日：2016-12-20
申请号：US13485828
申请日：2012-05-31
申请人： Charles J. Alpert , Gi-Joon Nam , Chin Ngai Sze , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles J. Alpert , Gi-Joon Nam , Chin Ngai Sze , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5068 , G06F17/5081
摘要： An improved circuit design system may include a computer processor to perform a placement for a circuit by physical synthesis. The system may also include a controller to compute a preferred location of at least one selected element of the circuit, and to calculate placement constraints for each selected element. The system may further include an updated design for the circuit generated by performing another round of physical synthesis with the placement constraints.
摘要翻译：改进的电路设计系统可以包括计算机处理器，以通过物理合成来执行电路的放置。该系统还可以包括控制器，用于计算电路的至少一个选定元件的优选位置，并且计算每个选定元件的放置约束。该系统可以进一步包括通过用放置约束执行另一轮物理合成而产生的电路的更新设计。

7. 发明授权

US07761832B2 Method for incremental, timing-driven, physical-synthesis optimization under a linear delay model 有权
标题翻译：线性延迟模型下增量，时序驱动，物理综合优化的方法
公开(公告)号：US07761832B2
公开(公告)日：2010-07-20
申请号：US11941418
申请日：2007-11-16
申请人： Charles J. Alpert , Zhuo Li , Tao Luo , David A. Papa , Chin Ngai Sze
发明人： Charles J. Alpert , Zhuo Li , Tao Luo , David A. Papa , Chin Ngai Sze
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method, data processing system and computer program product for optimizing the placement of logic gates of a subcircuit in a physical synthesis flow. A Pyramids utility identifies and selects movable gate(s) for timing-driven optimization. A delay pyramid and a required arrival time (RAT) surface are generated for each net in the selected subcircuit. A slack pyramid for each net is generated from the difference between the RAT surface and delay pyramid of each net. The slack pyramids are grown and tested using test points to generate a worst-case slack region based on a plurality of slack pyramids in the selected subcircuit. The worst-case slack region is mapped on a placement region and a set of coordinates representing the optimal locations of the movable element(s) in the placement region are determined and outputted.
摘要翻译：一种用于优化物理合成流中子电路的逻辑门的布置的方法，数据处理系统和计算机程序产品。金字塔实用程序识别并选择可移动门以进行时序优化。为所选择的子电路中的每个网络生成延迟金字塔和所需的到达时间（RAT）表面。从每个网络的RAT表面和延迟金字塔之间的差异产生每个网络的松散金字塔。使用测试点生长和测试松散的金字塔，以基于所选择的子电路中的多个松散金字塔产生最差情况的松弛区域。最坏情况的松弛区域映射在放置区域上，并且确定并输出表示放置区域中的可移动元件的最佳位置的坐标系。

8. 发明授权

US08015532B2 Optimal timing-driven cloning under linear delay model 有权
标题翻译：线性延迟模型下最优时序驱动克隆
公开(公告)号：US08015532B2
公开(公告)日：2011-09-06
申请号：US11938824
申请日：2007-11-13
申请人： Charles J. Alpert , Zhuo Li , David A. Papa , Chin Ngai Sze
发明人： Charles J. Alpert , Zhuo Li , David A. Papa , Chin Ngai Sze
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A timing-driven cloning method iteratively partitions sinks of the net into different sets of clusters and for each set computes a figure of merit for a cloned gate location which optimizes timing based on linear delay, that is, a delay proportional to the distance between the cloned gate location and the sinks. The set having the highest figure of merit is selected as the best solution. The original gate may also be moved to a timing-optimized location. The sinks are advantageously partitioned using boundaries of Voronoi polygons defined by a diamond region surrounding the original gate, or vice versa. The figure of merit may be for example worst slack, a sum of slacks at the sinks in the second cluster, or a linear combination of worst slack and sum of the slacks.
摘要翻译：定时驱动的克隆方法将网络的宿迭代地分成不同的群集，并且对于每个集合来计算克隆的门位置的品质因数，其优化基于线性延迟的定时，即，与克隆门位置和汇。选择具有最高品质因数的集合作为最佳解决方案。原始门也可以移动到定时优化的位置。有利地使用由围绕原始门的金刚石区域定义的Voronoi多边形的边界来划分水槽，反之亦然。品质因数可以是例如最差的松弛度，第二组中的汇的松弛度的总和，或者最差的松弛和松弛的总和的线性组合。

9. 发明申请

US20090089721A1 METHOD FOR INCREMENTAL, TIMING-DRIVEN, PHYSICAL-SYNTHESIS OPTIMIZATION 审中-公开
标题翻译：增量，时序驱动，物理综合优化的方法
公开(公告)号：US20090089721A1
公开(公告)日：2009-04-02
申请号：US11866231
申请日：2007-10-02
申请人： Charles J. Alpert , Arvind K. Karandikar , Zhuo Li , Gijoon Nam , David A. Papa , Chin Ngai Sze
发明人： Charles J. Alpert , Arvind K. Karandikar , Zhuo Li , Gijoon Nam , David A. Papa , Chin Ngai Sze
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method, data processing system and computer program product for optimizing the placement of logic gates of a subcircuit in a physical synthesis flow. A Rip Up and Move Boxes with Linear Evaluation (RUMBLE) utility identifies movable gate(s) for timing-driven optimization. The RUMBLE utility isolates an original subcircuit corresponding to the movable gate(s) and builds an unbuffered model of the original subcircuit. Notably, a new optimized placement of the movable gate is yielded to optimize the timing (i.e., maximize the minimum slack) of the original subcircuit, while accounting for future interconnect optimizations. The new subcircuit containing the new optimized gate placement and interconnect optimization is evaluated as to whether a timing degradation exists in the new subcircuit. If a timing degradation exists in the new subcircuit, the RUMBLE utility can restore an original subcircuit and a timing state associated with the original subcircuit.
摘要翻译：一种用于优化物理合成流中子电路的逻辑门的布置的方法，数据处理系统和计算机程序产品。具有线性评估（RUMBLE）功能的移动和移动盒识别用于定时驱动优化的可移动门。 RUMBLE实用程序隔离与可移动门对应的原始子电路，并构建原始子电路的无缓冲模型。值得注意的是，产生了可移动门的新优化布置，以优化原始子电路的定时（即，最大化最小松弛），同时考虑到将来的互连优化。评估包含新优化的栅极布局和互连优化的新子电路是否存在新的子电路中的定时劣化。如果新的子电路中存在定时降级，则RUMBLE实用程序可以恢复原始子电路和与原始子电路相关联的定时状态。

10. 发明申请

US20090125859A1 Methods for Optimal Timing-Driven Cloning Under Linear Delay Model 有权
标题翻译：线性延迟模型下最优时序驱动克隆的方法
公开(公告)号：US20090125859A1
公开(公告)日：2009-05-14
申请号：US11938824
申请日：2007-11-13
申请人： Charles J. Alpert , Zhuo Li , David A. Papa , Chin Ngai Sze
发明人： Charles J. Alpert , Zhuo Li , David A. Papa , Chin Ngai Sze
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A timing-driven cloning method iteratively partitions sinks of the net into different sets of clusters and for each set computes a figure of merit for a cloned gate location which optimizes timing based on linear delay, that is, a delay proportional to the distance between the cloned gate location and the sinks. The set having the highest figure of merit is selected as the best solution. The original gate may also be moved to a timing-optimized location. The sinks are advantageously partitioned using boundaries of Voronoi polygons defined by a diamond region surrounding the original gate, or vice versa. The figure of merit may be for example worst slack, a sum of slacks at the sinks in the second cluster, or a linear combination of worst slack and sum of the slacks.
摘要翻译：定时驱动的克隆方法将网络的宿迭代地分成不同的群集，并且对于每个集合来计算克隆的门位置的品质因数，其优化基于线性延迟的定时，即，与克隆门位置和汇。选择具有最高品质因数的集合作为最佳解决方案。原始门也可以移动到定时优化的位置。有利地使用由围绕原始门的金刚石区域定义的Voronoi多边形的边界来划分水槽，反之亦然。品质因数可以是例如最差的松弛度，第二组中的汇的松弛度的总和，或者最差的松弛和松弛的总和的线性组合。

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