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1. 发明授权

US08407652B2 Task-based multi-process design synthesis 有权
标题翻译：基于任务的多进程设计综合
公开(公告)号：US08407652B2
公开(公告)日：2013-03-26
申请号：US12972879
申请日：2010-12-20
申请人： Anthony D. Drumm , Jagannathan Narasimhan , Lakshmi N. Reddy , Louise H. Trevillyan , Brian C. Wilson
发明人： Anthony D. Drumm , Jagannathan Narasimhan , Lakshmi N. Reddy , Louise H. Trevillyan , Brian C. Wilson
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A task-based multi-process design synthesis methodology relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. The child processes then notify the parent process of those objects that qualify as candidate objects, so that the parent process only has to perform the transform on the candidate objects, thereby relieving the parent process from the overhead associated with performing the transform on non-candidate objects for which the transform has been determined by the child processes as not being successful.
摘要翻译：基于任务的多进程设计合成方法依赖于多个子进程来辅助父进程对集成电路设计进行优化。来自集成电路设计的对象被分组成子集并被分配给子进程，每个子进程对分配给该子进程的子集中的每个对象执行变换，并且确定该子集中的哪些对象是候选对象变革的表现已经取得成功。然后，子进程通知那些符合候选对象的那些对象的父进程，以便父进程只需对候选对象执行转换，从而将父进程从与非候选对象执行转换相关的开销中解除子进程已将该转换确定为未成功的对象。

2. 发明申请

US20120159417A1 TASK-BASED MULTI-PROCESS DESIGN SYNTHESIS 有权
标题翻译：基于任务的多进程设计合成
公开(公告)号：US20120159417A1
公开(公告)日：2012-06-21
申请号：US12972879
申请日：2010-12-20
申请人： Anthony D. Drumm , Jagannathan Narasimhan , Lakshmi N. Reddy , Louise H. Trevillyan , Brian C. Wilson
发明人： Anthony D. Drumm , Jagannathan Narasimhan , Lakshmi N. Reddy , Louise H. Trevillyan , Brian C. Wilson
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A task-based multi-process design synthesis methodology relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. The child processes then notify the parent process of those objects that qualify as candidate objects, so that the parent process only has to perform the transform on the candidate objects, thereby relieving the parent process from the overhead associated with performing the transform on non-candidate objects for which the transform has been determined by the child processes as not being successful.
摘要翻译：基于任务的多进程设计合成方法依赖于多个子进程来辅助父进程对集成电路设计进行优化。来自集成电路设计的对象被分组成子集并被分配给子进程，每个子进程对分配给该子进程的子集中的每个对象执行变换，并且确定该子集中的哪些对象是候选对象变革的表现已经取得成功。然后，子进程通知那些符合候选对象的那些对象的父进程，以便父进程只需对候选对象执行转换，从而将父进程从与非候选对象执行转换相关的开销中解除子进程已将该转换确定为未成功的对象。

3. 发明申请

US20120159406A1 TASK-BASED MULTI-PROCESS DESIGN SYNTHESIS WITH REPRODUCIBLE TRANSFORMS 有权
标题翻译：基于任务的多进程设计与可重构变换的合成
公开(公告)号：US20120159406A1
公开(公告)日：2012-06-21
申请号：US12972980
申请日：2010-12-20
申请人： Anthony D. Drumm , Jagannathan Narasimhan , Lakshmi N. Reddy , Louise H. Trevillyan
发明人： Anthony D. Drumm , Jagannathan Narasimhan , Lakshmi N. Reddy , Louise H. Trevillyan
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A task-based multi-process design synthesis methodology is reproducible, and relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. Each child process also undoes the transform performed for each object such that the same initial state of the integrated circuit design is used to perform each transform. In addition, the parent process tracks the results of performing the transform by each child process, and applies successful transforms in a controlled sequence.
摘要翻译：基于任务的多进程设计合成方法是可重复的，并且依赖于多个子进程来辅助父进程对集成电路设计进行优化。来自集成电路设计的对象被分组成子集并被分配给子进程，每个子进程对分配给该子进程的子集中的每个对象执行变换，并且确定该子集中的哪些对象是候选对象变革的表现已经取得成功。每个子进程还撤消对每个对象执行的变换，使得集成电路设计的相同初始状态被用于执行每个变换。此外，父进程跟踪每个子进程执行变换的结果，并以受控序列应用成功的转换。

4. 发明授权

US08341565B2 Task-based multi-process design synthesis with reproducible transforms 有权
标题翻译：基于任务的多进程设计合成与可重现的转换
公开(公告)号：US08341565B2
公开(公告)日：2012-12-25
申请号：US12972980
申请日：2010-12-20
申请人： Anthony D. Drumm , Jagannathan Narasimhan , Lakshmi N. Reddy , Louise H. Trevillyan
发明人： Anthony D. Drumm , Jagannathan Narasimhan , Lakshmi N. Reddy , Louise H. Trevillyan
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A task-based multi-process design synthesis methodology is reproducible, and relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. Each child process also undoes the transform performed for each object such that the same initial state of the integrated circuit design is used to perform each transform. In addition, the parent process tracks the results of performing the transform by each child process, and applies successful transforms in a controlled sequence.
摘要翻译：基于任务的多进程设计合成方法是可重复的，并且依赖于多个子进程来辅助父进程对集成电路设计进行优化。来自集成电路设计的对象被分组成子集并被分配给子进程，每个子进程对分配给该子进程的子集中的每个对象执行变换，并且确定该子集中的哪些对象是候选对象变革的表现已经取得成功。每个子进程还撤消对每个对象执行的变换，使得集成电路设计的相同初始状态被用于执行每个变换。此外，父进程跟踪每个子进程执行变换的结果，并以受控序列应用成功的转换。

5. 发明授权

US08392866B2 Task-based multi-process design synthesis with notification of transform signatures 有权
标题翻译：基于任务的多进程设计综合与转换签名通知
公开(公告)号：US08392866B2
公开(公告)日：2013-03-05
申请号：US12972934
申请日：2010-12-20
申请人： Anthony D. Drumm , Frank J. Musante , Jagannathan Narasimhan , Louise H. Trevillyan
发明人： Anthony D. Drumm , Frank J. Musante , Jagannathan Narasimhan , Louise H. Trevillyan
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A task-based multi-process design synthesis methodology relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. Each child process also provides result data to the parent process for each candidate object to reduce the overhead of the parent process when performing the transform on the candidate object. The result data, which may include, for example, a set of instructions or hints, may allow a parent process to take advantage of the efforts of the child process in performing the transform.
摘要翻译：基于任务的多进程设计合成方法依赖于多个子进程来辅助父进程对集成电路设计进行优化。来自集成电路设计的对象被分组成子集并被分配给子进程，每个子进程对分配给该子进程的子集中的每个对象执行变换，并且确定该子集中的哪些对象是候选对象变革的表现已经取得成功。每个子进程还将结果数据提供给每个候选对象的父进程，以便在对候选对象执行变换时减少父进程的开销。可以包括例如一组指令或提示的结果数据可以允许父进程利用子进程执行变换的努力。

6. 发明申请

US20120159418A1 TASK-BASED MULTI-PROCESS DESIGN SYNTHESIS WITH NOTIFICATION OF TRANSFORM SIGNATURES 有权
标题翻译：基于任务的多进程设计合成与变换签名的通知
公开(公告)号：US20120159418A1
公开(公告)日：2012-06-21
申请号：US12972934
申请日：2010-12-20
申请人： Anthony D. Drumm , Frank J. Musante , Jagannathan Narasimhan , Louise H. Trevillyan
发明人： Anthony D. Drumm , Frank J. Musante , Jagannathan Narasimhan , Louise H. Trevillyan
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A task-based multi-process design synthesis methodology relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. Each child process also provides result data to the parent process for each candidate object to reduce the overhead of the parent process when performing the transform on the candidate object. The result data, which may include, for example, a set of instructions or hints, may allow a parent process to take advantage of the efforts of the child process in performing the transform.
摘要翻译：基于任务的多进程设计合成方法依赖于多个子进程来辅助父进程对集成电路设计进行优化。来自集成电路设计的对象被分组成子集并被分配给子进程，每个子进程对分配给该子进程的子集中的每个对象执行变换，并且确定该子集中的哪些对象是候选对象变革的表现已经取得成功。每个子进程还将结果数据提供给每个候选对象的父进程，以便在对候选对象执行变换时减少父进程的开销。可以包括例如一组指令或提示的结果数据可以允许父进程利用子进程执行变换的努力。

7. 发明授权

US06425110B1 Incremental design tuning and decision mediator 失效
标题翻译：增量设计调整和决策调解器
公开(公告)号：US06425110B1
公开(公告)日：2002-07-23
申请号：US09213675
申请日：1998-12-17
申请人： David J. Hathaway , Anthony D. Drumm , Peter J. Osler
发明人： David J. Hathaway , Anthony D. Drumm , Peter J. Osler
IPC分类号： G06F1750
CPC分类号： G06F17/505
摘要： A method for analyzing and optimizing a design, such as a circuit design, which relates to the application of at least one optimization procedure, evaluating the benefit and net cost of the optimization procedure and then through the checkpoint manager, recording and reversing changes of the design. The execution and reversal of multiple optimizations may occur in a trial mode followed by evaluation of the executed and reversed designs and then the reinstatement of the best optimization.
摘要翻译：一种用于分析和优化诸如电路设计的设计的方法，其涉及应用至少一个优化过程，评估优化过程的益处和净成本，然后通过检查点管理器，记录和反转变化设计。多个优化的执行和反转可能发生在试用模式中，之后是执行和反向设计的评估，然后恢复最佳优化。

8. 发明授权

US5508937A Incremental timing analysis 失效
标题翻译：增量时序分析
公开(公告)号：US5508937A
公开(公告)日：1996-04-16
申请号：US49699
申请日：1993-04-16
申请人： Richard P. Abato , Anthony D. Drumm , David J. Hathaway , Lukas P. P. P. van Ginneken
发明人： Richard P. Abato , Anthony D. Drumm , David J. Hathaway , Lukas P. P. P. van Ginneken
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： Incremental timing analyzer for selectively performing timing analysis on a revised electronic circuit design resulting from one or more modifications to an initial electronic circuit design having input nodes, output nodes, and active elements electrically connected therebetween in a set of signal paths interconnected by a plurality of nodes. Each signal path has a timing delay associated therewith. Data is recorded representative of the modification's affect on relative timing values for a set of signals propagated through the circuit design. The recorded data includes a leftmost frontier of change in relative timing values and a rightmost frontier of change in relative timing values. Upon presentation of a specific timing analysis request, incremental timing analysis on the selected portion of the modified electronic circuit design is conducted employing the recorded frontiers of change to limit the timing value analysis. The concepts presented may be used for incremental recalculation of any signal value propagated forward or backward through a logic network.
摘要翻译：增量定时分析器，用于选择性地对经修改的电子电路设计进行定时分析，所述修正的电子电路设计是由具有输入节点，输出节点和电连接在其间的有源元件的初始电子电路设计的一个或多个修改而导致的，节点。每个信号路径具有与之相关的定时延迟。记录数据表示修改对通过电路设计传播的一组信号的相对定时值的影响。所记录的数据包括相对定时值变化的最左边界和相对定时值的最右边改变的边界。在呈现特定的时间分析请求时，利用所记录的改变的边界进行修改的电子电路设计的所选部分的增量定时分析，以限制时序值分析。所呈现的概念可用于对通过逻辑网络向前或向后传播的任何信号值的增量重新计算。

9. 发明授权

US5537330A Method for mapping in logic synthesis by logic classification 失效
标题翻译：逻辑分类逻辑综合映射方法
公开(公告)号：US5537330A
公开(公告)日：1996-07-16
申请号：US258314
申请日：1994-06-10
申请人： Robert F. Damiano , Anthony D. Drumm , Michael K. Edwards , Robert L. Kanzelman , Kathy M. McCarthy
发明人： Robert F. Damiano , Anthony D. Drumm , Michael K. Edwards , Robert L. Kanzelman , Kathy M. McCarthy
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method within a logic synthesis system provides for using tags attached to the nodes in a parse string generated from an abstract description of a logic design to classify portions of a heterogeneous design as open control, structure dominant, or direct map. The classification is then used to govern the amount of optimization allowed during logic synthesis. The classification is further used to seed or bypass the covering algorithms to produce the technology implementation desired by the designer. Structure dominance is a technique for "seeding" patterns by a designer which best fit the structure to the technology, which implies that the structural representation of the design as entered by the designer dominates the patterns located by the covering algorithm. However, other pattern matching functions are allowed to find better matches, if they exist, and the covering algorithm is allowed the final choice. Direct map processing bypasses optimization and covering altogether to implement the structural representation exactly as written, if possible, using the available elements in the target technology library. In the event that direct map is not possible, the node is processed as structure dominant.
摘要翻译：逻辑综合系统中的方法提供使用从逻辑设计的抽象描述生成的解析字符串中的节点附加标签，以将异构设计的部分分类为开放控制，结构主导或直接映射。然后，分类用于管理在逻辑合成期间允许的优化量。分类进一步用于种子或绕过覆盖算法以产生设计者期望的技术实现。结构优势是一种设计人员将“结构化”模式最适合于技术结构的技术，这意味着由设计者输入的设计结构表示主导了覆盖算法所定位的模式。然而，其他模式匹配函数可以找到更好的匹配，如果它们存在，并且允许覆盖算法是最终选择。如果可能，使用目标技术库中的可用元素，直接映射处理将绕过优化和覆盖，以完全实现结构化表示。在直接映射不可能的情况下，节点被处理为结构主导。

10. 发明授权

US5029102A Logical synthesis 失效
标题翻译：逻辑综合
公开(公告)号：US5029102A
公开(公告)日：1991-07-02
申请号：US59651
申请日：1987-06-08
申请人： Anthony D. Drumm , Charles P. Sweet
发明人： Anthony D. Drumm , Charles P. Sweet
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： The present invention provides a logic synthesis method and system which begins with a set of register transfer statements describing the desired logic. These statements are converted to expressions in prefix form. Next, logic reduction is performed on the individual expressions. The modified expressions are then converted to a set of logical function blocks, some of which may not be primitive blocks. Logical reduction is performed on the global set of any remaining primitives. The output of the above process is then used to synthesize the logic circuit. Included in the invention are novel techniques for performing logic reduction on the individual expressions.

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