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1. 发明申请

US20090217227A1 METHOD AND APPARATUS FOR PARALLEL PROCESSING OF SEMICONDUCTOR CHIP DESIGNS 有权
标题翻译：半导体芯片设计的并行处理方法与装置
公开(公告)号：US20090217227A1
公开(公告)日：2009-08-27
申请号：US12035950
申请日：2008-02-22
申请人： MICHAEL W. DOTSON , Anthony DeGroff Drumm , Dazhuang J. Ma , Ruchir Puri , Louise H. Trevillyan
发明人： MICHAEL W. DOTSON , Anthony DeGroff Drumm , Dazhuang J. Ma , Ruchir Puri , Louise H. Trevillyan
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： In one embodiment, the invention is a method and apparatus for parallel processing of semiconductor chip designs. One embodiment of a method for processing a semiconductor chip design includes flattening a netlist corresponding to the semiconductor chip design, performing logic clustering on one or more logic elements incorporated in the flattened netlist to generate one or more clusters, partitioning the semiconductor chip design in accordance with the one or more clusters, and designing the individual partitions in parallel.
摘要翻译：在一个实施例中，本发明是用于半导体芯片设计的并行处理的方法和装置。用于处理半导体芯片设计的方法的一个实施例包括平坦化对应于半导体芯片设计的网表，对并入在扁平化网表中的一个或多个逻辑元件执行逻辑聚类以生成一个或多个簇，根据该划分半导体芯片设计使用一个或多个集群，并且并行设计各个分区。

2. 发明申请

US20090019415A1 STAGE MITIGATION OF INTERCONNECT VARIABILITY 有权
标题翻译：互联不稳定性阶段缓解
公开(公告)号：US20090019415A1
公开(公告)日：2009-01-15
申请号：US12237246
申请日：2008-09-24
申请人： Mark A. Lavin , Ruchir Puri , Louise H. Trevillyan , Hua Xiang
发明人： Mark A. Lavin , Ruchir Puri , Louise H. Trevillyan , Hua Xiang
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： The present invention provides a method, system and program product for mitigating effects of interconnect variability during a design stage of a chip. Under the technique of the present invention, a global and detailed routing of interconnects of the chip are determined. Thereafter, a dummy fill estimation and a grid based metal density estimation are performed. Then, based on a CMP model, a variable map of metal thicknesses is obtained. Based on the variable map, wiring nets of the chip that are sensitive to metal variability (e.g., that fail to meet timing closure due to metal thickness loss/gain in the CMP process) are identified. These wiring nets are then re-routed for optimization of the chip.
摘要翻译：本发明提供了一种用于在芯片的设计阶段减轻互连变化的影响的方法，系统和程序产品。在本发明的技术下，确定了芯片互连的全局和详细路由。此后，执行虚拟填充估计和网格基金属密度估计。然后，基于CMP模型，获得金属厚度的可变图。基于可变图，识别对金属变化敏感的芯片的接线网（例如，由于CMP过程中的金属厚度损失/增益而不能满足定时闭合）。然后将这些接线网重新布线以优化芯片。

3. 发明授权

US07448014B2 Design stage mitigation of interconnect variability 有权
标题翻译：设计阶段缓解互连变异性
公开(公告)号：US07448014B2
公开(公告)日：2008-11-04
申请号：US11370538
申请日：2006-03-08
申请人： Mark A. Lavin , Ruchir Puri , Louise H. Trevillyan , Hua Xiang
发明人： Mark A. Lavin , Ruchir Puri , Louise H. Trevillyan , Hua Xiang
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： The present invention provides a method, system and program product for mitigating effects of interconnect variability during a design stage of a chip. Under the technique of the present invention, a global and detailed routing of interconnects of the chip are determined. Thereafter, a dummy fill estimation and a grid based metal density estimation are performed. Then, based on a CMP model, a variable map of metal thicknesses is obtained. Based on the variable map, wiring nets of the chip that are sensitive to metal variability (e.g., that fail to meet timing closure due to metal thickness loss/gain in the CMP process) are identified. These wiring nets are then re-routed for optimization of the chip.
摘要翻译：本发明提供了一种用于在芯片的设计阶段减轻互连变化的影响的方法，系统和程序产品。在本发明的技术下，确定了芯片互连的全局和详细路由。此后，执行虚拟填充估计和网格基金属密度估计。然后，基于CMP模型，获得金属厚度的可变图。基于可变图，识别对金属变化敏感的芯片的接线网（例如，由于CMP过程中的金属厚度损失/增益而不能满足定时闭合）。然后将这些接线网重新布线以优化芯片。

4. 发明申请

US20120159418A1 TASK-BASED MULTI-PROCESS DESIGN SYNTHESIS WITH NOTIFICATION OF TRANSFORM SIGNATURES 有权
标题翻译：基于任务的多进程设计合成与变换签名的通知
公开(公告)号：US20120159418A1
公开(公告)日：2012-06-21
申请号：US12972934
申请日：2010-12-20
申请人： Anthony D. Drumm , Frank J. Musante , Jagannathan Narasimhan , Louise H. Trevillyan
发明人： Anthony D. Drumm , Frank J. Musante , Jagannathan Narasimhan , Louise H. Trevillyan
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A task-based multi-process design synthesis methodology relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. Each child process also provides result data to the parent process for each candidate object to reduce the overhead of the parent process when performing the transform on the candidate object. The result data, which may include, for example, a set of instructions or hints, may allow a parent process to take advantage of the efforts of the child process in performing the transform.
摘要翻译：基于任务的多进程设计合成方法依赖于多个子进程来辅助父进程对集成电路设计进行优化。来自集成电路设计的对象被分组成子集并被分配给子进程，每个子进程对分配给该子进程的子集中的每个对象执行变换，并且确定该子集中的哪些对象是候选对象变革的表现已经取得成功。每个子进程还将结果数据提供给每个候选对象的父进程，以便在对候选对象执行变换时减少父进程的开销。可以包括例如一组指令或提示的结果数据可以允许父进程利用子进程执行变换的努力。

5. 发明申请

US20120159406A1 TASK-BASED MULTI-PROCESS DESIGN SYNTHESIS WITH REPRODUCIBLE TRANSFORMS 有权
标题翻译：基于任务的多进程设计与可重构变换的合成
公开(公告)号：US20120159406A1
公开(公告)日：2012-06-21
申请号：US12972980
申请日：2010-12-20
申请人： Anthony D. Drumm , Jagannathan Narasimhan , Lakshmi N. Reddy , Louise H. Trevillyan
发明人： Anthony D. Drumm , Jagannathan Narasimhan , Lakshmi N. Reddy , Louise H. Trevillyan
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A task-based multi-process design synthesis methodology is reproducible, and relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. Each child process also undoes the transform performed for each object such that the same initial state of the integrated circuit design is used to perform each transform. In addition, the parent process tracks the results of performing the transform by each child process, and applies successful transforms in a controlled sequence.
摘要翻译：基于任务的多进程设计合成方法是可重复的，并且依赖于多个子进程来辅助父进程对集成电路设计进行优化。来自集成电路设计的对象被分组成子集并被分配给子进程，每个子进程对分配给该子进程的子集中的每个对象执行变换，并且确定该子集中的哪些对象是候选对象变革的表现已经取得成功。每个子进程还撤消对每个对象执行的变换，使得集成电路设计的相同初始状态被用于执行每个变换。此外，父进程跟踪每个子进程执行变换的结果，并以受控序列应用成功的转换。

6. 发明授权

US07895556B2 Method for optimizing an unrouted design to reduce the probability of timing problems due to coupling and long wire routes 有权
标题翻译：用于优化未路由设计以减少由于耦合和长线路引起的定时问题的概率的方法
公开(公告)号：US07895556B2
公开(公告)日：2011-02-22
申请号：US11942990
申请日：2007-11-20
申请人： Pooja M. Kotecha , David J. Hathaway , Louise H. Trevillyan
发明人： Pooja M. Kotecha , David J. Hathaway , Louise H. Trevillyan
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： A method and a system is described to predict effects of coupling on timing by estimating the delta delay and delta slack that can occur due to coupling on any net, for optimization to minimize the sensitivity of slack to potential coupling violations. The invention protects against other unexpected increases in effective load capacitance, such as those due to unexpectedly long wire routes. It also estimates the delay impact of a single ‘fault’ or ‘event’, such as a coupling event or unexpectedly long wires routes, including the impact of slew propagation.
摘要翻译：描述了一种方法和系统，以通过估计由于任何网络上的耦合而可能发生的增量延迟和增量松弛来预测耦合对定时的影响，以便优化以使松弛对潜在耦合违规的灵敏度最小化。本发明可防止有效负载电容的其他意外增加，例如由于意外长的电线路由引起的负载电容。它还估计单个“故障”或“事件”的延迟影响，例如耦合事件或意外长电线路由，包括转换传播的影响。

7. 发明申请

US20090132982A1 METHOD FOR OPTIMIZING AN UNROUTED DESIGN TO REDUCE THE PROBABILITY OF TIMING PROBLEMS DUE TO COUPLING AND LONG WIRE ROUTES 有权
标题翻译：优化设计的方法，以减少因耦合和长途径导致的时序问题的可行性
公开(公告)号：US20090132982A1
公开(公告)日：2009-05-21
申请号：US11942990
申请日：2007-11-20
申请人： Pooja M. Kotecha , David J. Hathaway , Louise H. Trevillyan
发明人： Pooja M. Kotecha , David J. Hathaway , Louise H. Trevillyan
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： A method and a system is described to predict effects of coupling on timing by estimating the delta delay and delta slack that can occur due to coupling on any net, for optimization to minimize the sensitivity of slack to potential coupling violations. The invention protects against other unexpected increases in effective load capacitance, such as those due to unexpectedly long wire routes. It also estimates the delay impact of a single ‘fault’ or ‘event’, such as a coupling event or unexpectedly long wires routes, including the impact of slew propagation.
摘要翻译：描述了一种方法和系统，以通过估计由于任何网络上的耦合而可能发生的增量延迟和增量松弛来预测耦合对定时的影响，以便优化以使松弛对潜在耦合违规的灵敏度最小化。本发明可防止有效负载电容的其他意外增加，例如由于意外长的电线路由引起的负载电容。它还估计单个“故障”或“事件”的延迟影响，例如耦合事件或意外长电线路由，包括转换传播的影响。

8. 发明申请

US20080256502A1 SYSTEM AND METHOD FOR GLOBAL CIRCUIT ROUTING INCORPORATING ESTIMATION OF CRITICAL AREA ESTIMATE METRICS 失效
标题翻译：全球电路路由系统与方法，适用于关键领域估算的估计
公开(公告)号：US20080256502A1
公开(公告)日：2008-10-16
申请号：US11733795
申请日：2007-04-11
申请人： Evanthia Papadopoulou , Ruchir Puri , Mervyn Y. Tan , Louise H. Trevillyan , Hua Xiang
发明人： Evanthia Papadopoulou , Ruchir Puri , Mervyn Y. Tan , Louise H. Trevillyan , Hua Xiang
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： An electronic circuit layout refinement method and system. A grid of equally sized tiles is defined on a circuit layout area. Each tile of the grid has a respective critical area estimate metric associated with critical area estimates for a circuit to be placed on the circuit layout area. A global circuit routing for a circuit to be placed within a plurality of tiles of the grid is performed. An estimation of critical area estimate metrics that are assigned to respective tiles of the grid is performed prior to performing a detailed circuit routing for the circuit. The global circuit routing is adjusted, after estimating the critical area estimate metrics, in order to improve a respective critical area estimate metric assigned to at least one tile of the grid. The adjusted global circuit routing is then produced.
摘要翻译：电子电路布局细化方法和系统。在电路布局区域上定义了一个大小相同的瓷砖网格。电网的每个瓦片具有与放置在电路布局区域上的电路的关键面积估计相关联的相应临界面积估计量度。执行用于放置在电网的多个瓦片内的电路的全局电路布线。在对电路执行详细的电路布线之前执行分配给电网的各个瓦片的关键面积估计度量的估计。在估计关键区域估计度量之后，调整全局电路路由，以便改进分配给网格的至少一个瓦片的相应临界区域估计度量。然后生成经调整的全局电路布线。

9. 发明申请

US20080209376A1 SYSTEM AND METHOD FOR SIGN-OFF TIMING CLOSURE OF A VLSI CHIP 失效
标题翻译： VLSI芯片的关闭时序关闭的系统和方法
公开(公告)号：US20080209376A1
公开(公告)日：2008-08-28
申请号：US11680110
申请日：2007-02-28
申请人： Michael A. Kazda , Pooja M. Kotecha , Adam P. Matheny , Lakshmi Reddy , Louise H. Trevillyan , Paul G. Villarrubia
发明人： Michael A. Kazda , Pooja M. Kotecha , Adam P. Matheny , Lakshmi Reddy , Louise H. Trevillyan , Paul G. Villarrubia
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/84
摘要： A method for performing timing optimization of a detail routed netlist, incorporating statistical variability information, common path pessimism reduction, and capacitative coupling information, in a tightly coupled, incremental manner with minimal perturbations to the placement, routing, and asserted parasitic information. The method corrects violations in a placed and routed design of a VLSI circuit chip, where the design is represented by a netlist describing logical and physical characteristics of the design and by a corresponding timing graph, the method including the steps of: identifying violations in the design; iteratively eliminating the violations by incrementally transforming the logical and the physical characteristics of the design, incorporating in the design only legal placements and routes; and applying incremental timing to evaluate the transformations, and updating the existing timing graphs to reflect changes consisting of the legal placements and routes.
摘要翻译：一种用于以紧密耦合的递增方式对细节路由网表执行定时优化的方法，其以最小的扰动对放置，路由和断言的寄生信息进行并入，并入统计变异信息，公共路径悲观度降低和电容耦合信息。该方法校正了VLSI电路芯片的放置和路由设计中的违规，其中设计由描述设计的逻辑和物理特性的网表以及对应的时序图表示，该方法包括以下步骤：识别设计; 通过逐步改变设计的逻辑和物理特征，迭代地消除违规行为，仅在设计中纳入合法的布局和路线; 并应用增量时间来评估变革，并更新现有的时间图，以反映由法定刊登位置和路线组成的变更。

10. 发明授权

US08020134B2 Method and apparatus for parallel processing of semiconductor chip designs 有权
标题翻译：半导体芯片设计的并行处理方法和装置
公开(公告)号：US08020134B2
公开(公告)日：2011-09-13
申请号：US12035950
申请日：2008-02-22
申请人： Michael W. Dotson , Anthony DeGroff Drumm , Dazhuang J. Ma , Ruchir Puri , Louise H. Trevillyan
发明人： Michael W. Dotson , Anthony DeGroff Drumm , Dazhuang J. Ma , Ruchir Puri , Louise H. Trevillyan
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： In one embodiment, the invention is a method and apparatus for parallel processing of semiconductor chip designs. One embodiment of a method for processing a semiconductor chip design includes flattening a netlist corresponding to the semiconductor chip design, performing logic clustering on one or more logic elements incorporated in the flattened netlist to generate one or more clusters, partitioning the semiconductor chip design in accordance with the one or more clusters, and designing the individual partitions in parallel.
摘要翻译：在一个实施例中，本发明是用于半导体芯片设计的并行处理的方法和装置。用于处理半导体芯片设计的方法的一个实施例包括平坦化对应于半导体芯片设计的网表，对并入在扁平化网表中的一个或多个逻辑元件执行逻辑聚类以生成一个或多个簇，根据该划分半导体芯片设计使用一个或多个集群，并且并行设计各个分区。

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