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1. 发明授权

US08283960B2 Minimal bubble voltage regulator 有权
标题翻译：最小气泡电压调节器
公开(公告)号：US08283960B2
公开(公告)日：2012-10-09
申请号：US12430829
申请日：2009-04-27
申请人： Hanh-Phuc Le , Robert P. Masleid , David Greenhill
发明人： Hanh-Phuc Le , Robert P. Masleid , David Greenhill
IPC分类号： H03H11/26
CPC分类号： G05F1/46
摘要： A digital voltage regulator including a dual rail delay chain having large size, feed forward cross-coupled inverters that interconnect the two rails. Stages of the delay chain include a dual-ended output that provides a data signal and a substantially simultaneous data complement signal to a flip-flop component associated with a sampling circuit. In use, the enhanced resolution delay chain and the reduced metastability window flop-flop increase the precision of the digital voltage regulator.
摘要翻译：一种数字电压调节器，包括具有大尺寸的双轨延迟链，其互连两个导轨的前馈交叉耦合逆变器。延迟链的阶段包括双端输出，其向与采样电路相关联的触发器组件提供数据信号和基本上同时的数据补码信号。在使用中，增强分辨率延迟链和降低的亚稳态窗触发器提高了数字电压调节器的精度。

2. 发明申请

US20100271099A1 FINE GRAIN TIMING 有权
标题翻译：精细时序
公开(公告)号：US20100271099A1
公开(公告)日：2010-10-28
申请号：US12430854
申请日：2009-04-27
申请人： Hanh-Phuc Le , Robert P. Masleid , David Greenhill
发明人： Hanh-Phuc Le , Robert P. Masleid , David Greenhill
IPC分类号： H03H11/26
CPC分类号： H03K5/131
摘要： A dual rail delay chain having cross-coupled inverters that interconnect the two rails. Delay chain embodiments include cross-coupled inverters that are part of a feed forward signal path between the two rails and are of a larger size than inverters associated with the two rails. The large size feed forward cross-coupled inverters contribute to an enhanced resolution of the delay chain.
摘要翻译：具有互连两个导轨的交叉耦合逆变器的双轨延迟链。延迟链实施例包括交叉耦合的反相器，其是两个轨道之间的前馈信号路径的一部分，并且具有比与两个轨道相关联的逆变器更大的尺寸。大尺寸前馈交叉耦合逆变器有助于提高延迟链的分辨率。

3. 发明申请

US20100271100A1 MINIMAL BUBBLE VOLTAGE REGULATOR 有权
标题翻译：最小泡压稳压器
公开(公告)号：US20100271100A1
公开(公告)日：2010-10-28
申请号：US12430829
申请日：2009-04-27
申请人： Hanh-Phuc Le , Robert P. Masleid , David Greenhill
发明人： Hanh-Phuc Le , Robert P. Masleid , David Greenhill
IPC分类号： H03H11/26
CPC分类号： G05F1/46
摘要： A digital voltage regulator including a dual rail delay chain having large size, feed forward cross-coupled inverters that interconnect the two rails. Stages of the delay chain include a dual-ended output that provides a data signal and a substantially simultaneous data complement signal to a flip-flop component associated with a sampling circuit. In use, the enhanced resolution delay chain and the reduced metastability window flop-flop increase the precision of the digital voltage regulator.
摘要翻译：一种数字电压调节器，包括具有大尺寸的双轨延迟链，其互连两个导轨的前馈交叉耦合逆变器。延迟链的阶段包括双端输出，其向与采样电路相关联的触发器组件提供数据信号和基本上同时的数据补码信号。在使用中，增强分辨率延迟链和降低的亚稳态窗触发器提高了数字电压调节器的精度。

4. 发明授权

US08198931B2 Fine grain timing 有权
标题翻译：细粒时间
公开(公告)号：US08198931B2
公开(公告)日：2012-06-12
申请号：US12430854
申请日：2009-04-27
申请人： Hanh-Phuc Le , Robert P. Masleid , David Greenhill
发明人： Hanh-Phuc Le , Robert P. Masleid , David Greenhill
IPC分类号： H03H11/26
CPC分类号： H03K5/131
摘要： A dual rail delay chain having cross-coupled inverters that interconnect the two rails. Delay chain embodiments include cross-coupled inverters that are part of a feed forward signal path between the two rails and are of a larger size than inverters associated with the two rails. The large size feed forward cross-coupled inverters contribute to an enhanced resolution of the delay chain.
摘要翻译：具有互连两个导轨的交叉耦合逆变器的双轨延迟链。延迟链实施例包括交叉耦合的反相器，其是两个轨道之间的前馈信号路径的一部分，并且具有比与两个轨道相关联的逆变器更大的尺寸。大尺寸前馈交叉耦合逆变器有助于提高延迟链的分辨率。

5. 发明申请

US20100127749A1 PRECISION PULSE GENERATOR 有权
标题翻译：精密脉冲发生器
公开(公告)号：US20100127749A1
公开(公告)日：2010-05-27
申请号：US12277864
申请日：2008-11-25
申请人： Robert P. Masleid , David Greenhill
发明人： Robert P. Masleid , David Greenhill
IPC分类号： H03K3/00
CPC分类号： H03K3/355 , H03K3/011 , H03K3/012 , H03K2005/00293
摘要： A pulse generator circuit. The pulse generator circuit includes a precharge circuit coupled to receive a clock signal alternating between a first logic level and a second logic level, a storage circuit having a storage node, wherein the precharge circuit is configured to precharge the storage node when the clock signal is at the first logic level, a logic circuit having an output, a first input node coupled to receive the clock signal, and a second input node coupled to the storage node and configured to produce a pulse at the second logic level responsive to the clock signal transitioning to the second logic level, and a discharge circuit configured to discharge the storage node at a predetermined delay time subsequent to the clock signal transitioning to the second logic level, wherein the output of the logic circuit transitions to the first logic level responsive to discharging the storage node.
摘要翻译：脉冲发生器电路。所述脉冲发生器电路包括预充电电路，其被耦合以接收在第一逻辑电平和第二逻辑电平之间交替的时钟信号，具有存储节点的存储电路，其中所述预充电电路被配置为当所述时钟信号为在第一逻辑电平处，具有输出的逻辑电路，被耦合以接收时钟信号的第一输入节点和耦合到存储节点的第二输入节点，并且被配置为响应于时钟信号产生处于第二逻辑电平的脉冲转换到第二逻辑电平的放电电路，以及放电电路，被配置为在时钟信号转换到第二逻辑电平之后的预定延迟时间对存储节点放电，其中逻辑电路的输出响应于放电而转变到第一逻辑电平存储节点。

6. 发明授权

US08686778B2 Integrated pulse-control and enable latch circuit 有权
标题翻译：集成脉冲控制和使能锁存电路
公开(公告)号：US08686778B2
公开(公告)日：2014-04-01
申请号：US12546529
申请日：2009-08-24
申请人： Jason M. Hart , Robert P. Masleid
发明人： Jason M. Hart , Robert P. Masleid
IPC分类号： G01R29/02 , H03K9/08 , H03K5/01 , H03K3/017 , H03K5/04 , H03K7/08 , H03K3/00 , H03K3/289
CPC分类号： H03K3/356113 , G06F1/06 , G06F1/10
摘要： The described embodiments provide a configurable clock circuit. The clock circuit includes a control and enable circuit and a clock distribution circuit. During operation, when a signal on an enable input to the control and enable circuit is asserted and the control and enable circuit is configured in a clock mode, the control and enable circuit generates an enable signal on a control output to enable a signal on a clock input to propagate through the clock distribution circuit to the clock output. Alternatively, when a signal on the enable input to the control and enable circuit is asserted and the control and enable circuit is configured in a pulse mode, the control and enable circuit generates a pulsed control signal on the control output to control a length of a pulse generated from the clock input on a clock output by the clock distribution circuit.
摘要翻译：所描述的实施例提供了可配置的时钟电路。时钟电路包括控制和使能电路和时钟分配电路。在操作期间，当控制和使能电路的使能输入上的信号被确认并且控制和使能电路被配置为时钟模式时，控制和使能电路在控制输出上产生使能信号，以使得能够在时钟输入通过时钟分配电路传播到时钟输出。或者，当控制和使能电路的使能输入上的信号被确认并且控制和使能电路被配置为脉冲模式时，控制和使能电路在控制输出上产生脉冲控制信号以控制一个由时钟分配电路输出的时钟上的时钟输入产生的脉冲。

7. 发明授权

US08305126B2 Flop type selection for very large scale integrated circuits 有权
标题翻译：非常大型集成电路的Flop型选择
公开(公告)号：US08305126B2
公开(公告)日：2012-11-06
申请号：US13005835
申请日：2011-01-13
申请人： Alan P. Smith , Robert P. Masleid , Georgios Konstadinidis
发明人： Alan P. Smith , Robert P. Masleid , Georgios Konstadinidis
IPC分类号： H03K3/289 , G01R35/00
CPC分类号： H03K3/0372 , G06F17/505 , G06F17/5068
摘要： A method for determining flop circuit types includes performing a layout of an IC design including arranging master and slave latches of each of a plurality of flops to receive first and second clock signals, respectively. The initial IC design may then be implemented (e.g., on a silicon substrate). After implementation, the IC may be operated in first and second modes. In the first mode, the master latch of each flop is coupled to receive a first clock signal. In the second mode, the first clock signal is inhibited and the master latch is held transparent. The slave latch of each flop operates according to a second clock signal in both the first and second modes. The method further includes determining, for each flop, whether that flop is to operate as a master-slave flip-flop or as a pulse flop in a subsequent revision of the IC.
摘要翻译：用于确定触发器电路类型的方法包括执行IC设计的布局，包括分别布置多个触发器中的每一个的主锁存器和从锁存器以分别接收第一和第二时钟信号。然后可以实现初始IC设计（例如，在硅衬底上）。实施后，IC可以在第一和第二模式下操作。在第一模式中，每个触发器的主锁存器被耦合以接收第一时钟信号。在第二模式中，第一时钟信号被禁止并且主锁存器保持透明。每个触发器的从锁存器根据第一和第二模式中的第二时钟信号进行操作。该方法还包括为每个触发器确定该触发器在IC的后续版本中是作为主从触发器还是作为脉冲触发器。

8. 发明申请

US20120224448A1 DELAY EFFICIENT GATER REPEATER 有权
标题翻译：延时效率高
公开(公告)号：US20120224448A1
公开(公告)日：2012-09-06
申请号：US13040406
申请日：2011-03-04
申请人： Robert P. Masleid
发明人： Robert P. Masleid
IPC分类号： G11C8/10 , H03L7/00
CPC分类号： G11C8/10
摘要： A gater repeater circuit is disclosed. In one embodiment, the circuit includes an activation circuit coupled to receive an input signal and a clock signal and configured to activate an output circuit. The output circuit is configured to drive an output signal. The output circuit includes first and second devices configured to drive the output signal to first and second states, respectively. A feedback circuit is configured to provide a delayed version of the output signal. A deactivation circuit is coupled to receive the clock signal and the delayed version of the output signal, and is configured to, when the clock signal is in the first state, cause the deactivation of an active one of the first and second devices. When the clock is in the second state, the circuit is configured to cause the second device to drive the output signal to the second state.
摘要翻译：公开了一种门控中继器电路。在一个实施例中，电路包括激活电路，其被耦合以接收输入信号和时钟信号，并被配置为激活输出电路。输出电路被配置为驱动输出信号。输出电路包括分别将输出信号驱动到第一和第二状态的第一和第二器件。反馈电路被配置为提供输出信号的延迟版本。耦合去激活电路以接收时钟信号和输出信号的延迟版本，并且被配置为当时钟信号处于第一状态时，导致第一和第二器件中的有效器件的去激活。当时钟处于第二状态时，电路被配置为使得第二设备将输出信号驱动到第二状态。

9. 发明申请

US20120200347A1 SKEWED PLACEMENT GRID FOR VERY LARGE SCALE INTEGRATED CIRCUITS 有权
标题翻译：针对非常大的规模集成电路的摆放布局
公开(公告)号：US20120200347A1
公开(公告)日：2012-08-09
申请号：US13022913
申请日：2011-02-08
申请人： Robert P. Masleid
发明人： Robert P. Masleid
IPC分类号： H01L25/00
CPC分类号： G06F17/5072
摘要： A skewed placement grid for an integrated circuit (IC) is disclosed. In one embodiment, an IC includes a placement grid which includes a plurality of cells. Each of the plurality of cells includes one of a corresponding plurality of circuits. A center point of each of the cells is located at a unique coordinate along a first axis and a second axis with respect to each of the other ones of the plurality of cells. The IC further includes a first plurality of signal interconnections, wherein each of the plurality of signal interconnections is coupled to a corresponding one of the first plurality of circuits.
摘要翻译：公开了用于集成电路（IC）的偏斜放置网格。在一个实施例中，IC包括包括多个单元的放置网格。多个单元中的每个单元包括相应的多个电路中的一个。每个单元的中心点位于相对于多个单元中的其它单元中的每一个的第一轴和第二轴的唯一坐标。 IC还包括第一多个信号互连，其中多个信号互连中的每一个耦合到第一多个电路中的对应的一个。

10. 发明授权

US08208467B2 Method and apparatus for modulating the width of a high-speed link 有权
标题翻译：用于调制高速链路宽度的方法和装置
公开(公告)号：US08208467B2
公开(公告)日：2012-06-26
申请号：US12485395
申请日：2009-06-16
申请人： Sanjiv Kapil , David J. Greenhill , Robert P. Masleid
发明人： Sanjiv Kapil , David J. Greenhill , Robert P. Masleid
IPC分类号： H04L12/28 , H04J3/18 , H04H20/28
CPC分类号： G06F13/385 , G06F2213/3814
摘要： The described embodiments include a system that modulates the width of a high-speed link. The system includes a transmitter circuit coupled to a high-speed link that includes N serial lanes. During operation, while using a first number of lanes to transmit frames on the high-speed link, the transmitter circuit determines a second number of lanes to be used to transmit frames on the high-speed link based on a bandwidth demand on the high-speed link. The transmitter circuit then sends an indicator of the second number of lanes to a receiver on the high-speed link. Upon receiving an error-free acknowledgment of the indicator from the receiver, starting from a predetermined frame, the transmitter circuit transmits subsequent frames on the high-speed link using the second number of lanes.
摘要翻译：所描述的实施例包括调制高速链路的宽度的系统。该系统包括耦合到包括N个串行通道的高速链路的发射机电路。在操作期间，当使用第一数量的通道在高速链路上传送帧时，发送器电路基于高速链路上的带宽需求，确定要用于在高速链路上传送帧的第二数量的通道，速度链接。然后，发射机电路将第二数量的通道的指示符发送到高速链路上的接收机。在从接收机接收到指示符的无错误确认之后，从预定帧开始，发送器电路使用第二数量的通道在高速链路上发送后续帧。

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