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1. 发明申请

US20100271085A1 DELAY CHAIN INITIALIZATION 有权
标题翻译：延迟链初始化
公开(公告)号：US20100271085A1
公开(公告)日：2010-10-28
申请号：US12430846
申请日：2009-04-27
申请人： Hanh-Phuc Le , Robert P. Masleid
发明人： Hanh-Phuc Le , Robert P. Masleid
IPC分类号： H03L7/00
CPC分类号： H03K5/131
摘要： A delay chain initialization circuit that converts a singled-sided signal to a dual sided-signal. The dual-sided delay chain including a data rail and a complement rail. Each of the data rail and data complement rail include inverter chains that are interconnected through cross-coupled inverter pairs. The delay chain initialization circuit being adapted to produce, at an output, a data signal and a data complement signal that are substantially simultaneous.
摘要翻译：延迟链初始化电路，其将单面信号转换为双面信号。双面延迟链包括数据轨和互补轨。数据轨道和数据补充轨道中的每一条都包括通过交叉耦合的逆变器对互连的逆变器链。延迟链初始化电路适于在输出端产生基本同时的数据信号和数据补码信号。

2. 发明申请

US20100271099A1 FINE GRAIN TIMING 有权
标题翻译：精细时序
公开(公告)号：US20100271099A1
公开(公告)日：2010-10-28
申请号：US12430854
申请日：2009-04-27
申请人： Hanh-Phuc Le , Robert P. Masleid , David Greenhill
发明人： Hanh-Phuc Le , Robert P. Masleid , David Greenhill
IPC分类号： H03H11/26
CPC分类号： H03K5/131
摘要： A dual rail delay chain having cross-coupled inverters that interconnect the two rails. Delay chain embodiments include cross-coupled inverters that are part of a feed forward signal path between the two rails and are of a larger size than inverters associated with the two rails. The large size feed forward cross-coupled inverters contribute to an enhanced resolution of the delay chain.
摘要翻译：具有互连两个导轨的交叉耦合逆变器的双轨延迟链。延迟链实施例包括交叉耦合的反相器，其是两个轨道之间的前馈信号路径的一部分，并且具有比与两个轨道相关联的逆变器更大的尺寸。大尺寸前馈交叉耦合逆变器有助于提高延迟链的分辨率。

3. 发明授权

US08242823B2 Delay chain initialization 有权
标题翻译：延迟链初始化
公开(公告)号：US08242823B2
公开(公告)日：2012-08-14
申请号：US12430846
申请日：2009-04-27
申请人： Hanh-Phuc Le , Robert P. Masleid
发明人： Hanh-Phuc Le , Robert P. Masleid
IPC分类号： H03L7/00
CPC分类号： H03K5/131
摘要： A delay chain initialization circuit that converts a singled-sided signal to a dual sided-signal. The dual-sided delay chain including a data rail and a complement rail. Each of the data rail and data complement rail include inverter chains that are interconnected through cross-coupled inverter pairs. The delay chain initialization circuit being adapted to produce, at an output, a data signal and a data complement signal that are substantially simultaneous.
摘要翻译：延迟链初始化电路，其将单面信号转换为双面信号。双面延迟链包括数据轨和互补轨。数据轨道和数据补充轨道中的每一条都包括通过交叉耦合的逆变器对互连的逆变器链。延迟链初始化电路适于在输出端产生基本同时的数据信号和数据补码信号。

4. 发明授权

US08198931B2 Fine grain timing 有权
标题翻译：细粒时间
公开(公告)号：US08198931B2
公开(公告)日：2012-06-12
申请号：US12430854
申请日：2009-04-27
申请人： Hanh-Phuc Le , Robert P. Masleid , David Greenhill
发明人： Hanh-Phuc Le , Robert P. Masleid , David Greenhill
IPC分类号： H03H11/26
CPC分类号： H03K5/131
摘要： A dual rail delay chain having cross-coupled inverters that interconnect the two rails. Delay chain embodiments include cross-coupled inverters that are part of a feed forward signal path between the two rails and are of a larger size than inverters associated with the two rails. The large size feed forward cross-coupled inverters contribute to an enhanced resolution of the delay chain.
摘要翻译：具有互连两个导轨的交叉耦合逆变器的双轨延迟链。延迟链实施例包括交叉耦合的反相器，其是两个轨道之间的前馈信号路径的一部分，并且具有比与两个轨道相关联的逆变器更大的尺寸。大尺寸前馈交叉耦合逆变器有助于提高延迟链的分辨率。

5. 发明申请

US20100271100A1 MINIMAL BUBBLE VOLTAGE REGULATOR 有权
标题翻译：最小泡压稳压器
公开(公告)号：US20100271100A1
公开(公告)日：2010-10-28
申请号：US12430829
申请日：2009-04-27
申请人： Hanh-Phuc Le , Robert P. Masleid , David Greenhill
发明人： Hanh-Phuc Le , Robert P. Masleid , David Greenhill
IPC分类号： H03H11/26
CPC分类号： G05F1/46
摘要： A digital voltage regulator including a dual rail delay chain having large size, feed forward cross-coupled inverters that interconnect the two rails. Stages of the delay chain include a dual-ended output that provides a data signal and a substantially simultaneous data complement signal to a flip-flop component associated with a sampling circuit. In use, the enhanced resolution delay chain and the reduced metastability window flop-flop increase the precision of the digital voltage regulator.
摘要翻译：一种数字电压调节器，包括具有大尺寸的双轨延迟链，其互连两个导轨的前馈交叉耦合逆变器。延迟链的阶段包括双端输出，其向与采样电路相关联的触发器组件提供数据信号和基本上同时的数据补码信号。在使用中，增强分辨率延迟链和降低的亚稳态窗触发器提高了数字电压调节器的精度。

6. 发明申请

US20100271076A1 PRECISION SAMPLING CIRCUIT 有权
标题翻译：精密采样电路
公开(公告)号：US20100271076A1
公开(公告)日：2010-10-28
申请号：US12430840
申请日：2009-04-27
申请人： Hanh-Phuc Le , Robert P. Masleid
发明人： Hanh-Phuc Le , Robert P. Masleid
IPC分类号： H03K5/00
CPC分类号： H03K5/131
摘要： A sampling circuit including a number of state elements or flip-flops. The state elements or flip-flops are each clocked by a signal that causes them to sample their inputs at a predetermined time. In sampling a plurality of digital inputs, a captured delay chain value is stored by the sampling circuit. Each flip-flop holds one bit and together the total number of bits represent this captured delay chain value. Each flip-flop is provided with a data and a data complement signal as an input, the data and data complement signal being substantially simultaneous. In operation each flip-flop includes a direct connection of the data and data complement signals to a pair of transistors that further operate to capture the logical value carried by the input.
摘要翻译：包括多个状态元件或触发器的采样电路。状态元件或触发器每个都由一个信号进行计时，该信号使得它们在预定的时间对其输入进行采样。在对多个数字输入进行采样时，所采集的延迟链值由采样电路存储。每个触发器保持一位，并且总共的位数表示该捕获的延迟链值。每个触发器被提供有数据和数据补码信号作为输入，数据和数据补码信号基本上同时进行。在操作中，每个触发器包括将数据和数据补码信号直接连接到进一步操作以捕获由输入携带的逻辑值的一对晶体管。

7. 发明申请

US20080231115A1 Multiple-Output DC-DC Converter 审中-公开
标题翻译：多输出DC-DC转换器
公开(公告)号：US20080231115A1
公开(公告)日：2008-09-25
申请号：US11687036
申请日：2007-03-16
申请人： Gyuha Cho , Hanh Phuc Le
发明人： Gyuha Cho , Hanh Phuc Le
IPC分类号： H02J1/00
CPC分类号： H02J1/08 , H02M3/158 , H02M3/33561 , H02M2001/009 , Y10T307/484
摘要： The invention relates to a DC/DC converter design. The converter requires only one single inductor to draw energy from one input source and distribute it to more than one outputs, employing Flexible-Order Power-Distributive Control (FOPDC). It include a single inductor, a number of power switches, comparators, only one error amplifier, a detecting circuit and a control block to regulate outputs. This converter can correctly regulate multiple outputs with fast transient response, low cross regulation, and effective switching frequency for each output. It can work in both discontinuous conduction mode (DCM) and continuous conduction mode (CCM). Moreover, with FOPDC, future output extension is simple, making a shorter time-to-market process for next versions of the converter. The design can be applied to different types of DC-DC converter.
摘要翻译：本发明涉及DC / DC转换器设计。该转换器只需要一个单个电感来从一个输入源中抽取能量，并将其分配到多个输出，采用灵活的功率分配控制（FOPDC）。它包括单个电感器，多个电源开关，比较器，仅一个误差放大器，检测电路和用于调节输出的控制块。该转换器可以对每个输出进行快速瞬态响应，低交叉调节和有效开关频率的正确调节多个输出。它可以工作在不连续导通模式（DCM）和连续导通模式（CCM）。此外，通过FOPDC，未来的产品扩展很简单，为下一代转换器的上市时间缩短。该设计可应用于不同类型的DC-DC转换器。

8. 发明授权

US08283960B2 Minimal bubble voltage regulator 有权
标题翻译：最小气泡电压调节器
公开(公告)号：US08283960B2
公开(公告)日：2012-10-09
申请号：US12430829
申请日：2009-04-27
申请人： Hanh-Phuc Le , Robert P. Masleid , David Greenhill
发明人： Hanh-Phuc Le , Robert P. Masleid , David Greenhill
IPC分类号： H03H11/26
CPC分类号： G05F1/46
摘要： A digital voltage regulator including a dual rail delay chain having large size, feed forward cross-coupled inverters that interconnect the two rails. Stages of the delay chain include a dual-ended output that provides a data signal and a substantially simultaneous data complement signal to a flip-flop component associated with a sampling circuit. In use, the enhanced resolution delay chain and the reduced metastability window flop-flop increase the precision of the digital voltage regulator.
摘要翻译：一种数字电压调节器，包括具有大尺寸的双轨延迟链，其互连两个导轨的前馈交叉耦合逆变器。延迟链的阶段包括双端输出，其向与采样电路相关联的触发器组件提供数据信号和基本上同时的数据补码信号。在使用中，增强分辨率延迟链和降低的亚稳态窗触发器提高了数字电压调节器的精度。

9. 发明授权

US08179165B2 Precision sampling circuit 有权
标题翻译：精密采样电路
公开(公告)号：US08179165B2
公开(公告)日：2012-05-15
申请号：US12430840
申请日：2009-04-27
申请人： Hanh-Phuc Le , Robert P. Masleid
发明人： Hanh-Phuc Le , Robert P. Masleid
IPC分类号： G11C27/02
CPC分类号： H03K5/131
摘要： A sampling circuit including a number of state elements or flip-flops. The state elements or flip-flops are each clocked by a signal that causes them to sample their inputs at a predetermined time. In sampling a plurality of digital inputs, a captured delay chain value is stored by the sampling circuit. Each flip-flop holds one bit and together the total number of bits represent this captured delay chain value. Each flip-flop is provided with a data and a data complement signal as an input, the data and data complement signal being substantially simultaneous. In operation each flip-flop includes a direct connection of the data and data complement signals to a pair of transistors that further operate to capture the logical value carried by the input.
摘要翻译：包括多个状态元件或触发器的采样电路。状态元件或触发器每个都由一个信号进行计时，该信号使得它们在预定的时间对其输入进行采样。在对多个数字输入进行采样时，所采集的延迟链值由采样电路存储。每个触发器保持一位，并且总共的位数表示该捕获的延迟链值。每个触发器被提供有数据和数据补码信号作为输入，数据和数据补码信号基本上同时进行。在操作中，每个触发器包括将数据和数据补码信号直接连接到一对晶体管，其进一步操作以捕获由输入携带的逻辑值。

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